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Costmetic changes during review of MAX3421E logic.

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This commit is contained in:
Gregory Nutt
2018-08-02 13:58:04 -06:00
parent ee21bcfaa8
commit f649db2405
6 changed files with 13 additions and 10 deletions
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configs/metro-m4/README.txt
+2 -1
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@@ -42,7 +42,8 @@ STATUS
Unfortunately, the board seems to have become unusable after the first Unfortunately, the board seems to have become unusable after the first
NuttX image was written to FLASH. I am unable to connect the JTAG NuttX image was written to FLASH. I am unable to connect the JTAG
debugger and so am dead in the water on this unless I get replacement debugger and so am dead in the water on this unless I get replacement
hardware. hardware. The primary JTAG problem seems to be that it is now unable
to halt the CPU.
Unlocking FLASH Unlocking FLASH
=============== ===============
configs/viewtool-stm32f107/README.txt
+2 -2
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@@ -732,7 +732,7 @@ MAX3421E Integration
MOSI J8 Pin 10 PA7/MOSI1 D11 MOSI (label CLK) MOSI J8 Pin 10 PA7/MOSI1 D11 MOSI (label CLK)
INT# J18 Pin 10 PA0 D9 INT INT# J18 Pin 10 PA0 D9 INT
RST# J18 Pin 8 PA1 D7 MAX_RST RST# J18 Pin 8 PA1 D7 MAX_RST
GPX D8 GPX GPX J18 Pin 6 PC5 D8 GPX (not used)
VBUS J18 Pin 2 5V VIN V_BUS VBUS J18 Pin 2 5V VIN V_BUS
3.3V J8 Pin 7 N/C VCC 3.3V J8 Pin 7 N/C VCC
GND J8 Pin 8 GND GND (no label) GND J8 Pin 8 GND GND (no label)
@@ -748,7 +748,7 @@ MAX3421E Integration
MOSI J8 Pin 4 PB15/MOSI2 D11 MOSI (label CLK) MOSI J8 Pin 4 PB15/MOSI2 D11 MOSI (label CLK)
INT# J18 Pin 10 PA0 D9 INT INT# J18 Pin 10 PA0 D9 INT
RST# J18 Pin 8 PA1 D7 MAX_RST RST# J18 Pin 8 PA1 D7 MAX_RST
GPX D8 GPX GPX J18 Pin 6 PC5 D8 GPX (not used)
VBUS J18 Pin 2 5V VIN V_BUS VBUS J18 Pin 2 5V VIN V_BUS
3.3V J8 Pin 1 N/C VCC 3.3V J8 Pin 1 N/C VCC
GND J8 Pin 2 GND GND (no label) GND J8 Pin 2 GND GND (no label)
configs/viewtool-stm32f107/src/stm32_max3421e.c
+2
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@@ -231,6 +231,8 @@ static void max3421e_acknowledge(FAR const struct max3421e_lowerhalf_s *lower)
static void max3421e_power(FAR const struct max3421e_lowerhalf_s *lower, static void max3421e_power(FAR const struct max3421e_lowerhalf_s *lower,
bool enable) bool enable)
{ {
/* We currently have no control over VBUS power */
#ifdef CONFIG_VIEWTOOL_MAX3421E_PWR #ifdef CONFIG_VIEWTOOL_MAX3421E_PWR
stm32_gpiowrite(GPIO_MAX3421E_PWR, enable); stm32_gpiowrite(GPIO_MAX3421E_PWR, enable);
#endif #endif
configs/viewtool-stm32f107/src/viewtool_stm32f107.h
+3
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@@ -335,6 +335,7 @@
* CS# J8 Pin 6 PB12/NSS2 (For SPI2) * CS# J8 Pin 6 PB12/NSS2 (For SPI2)
* INT# J18 Pin 10 PA0 * INT# J18 Pin 10 PA0
* RST# J18 Pin 8 PA1 * RST# J18 Pin 8 PA1
* GPX J18 Pin 6 PC5 (not used)
*/ */
#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) #if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1)
@@ -350,6 +351,8 @@
GPIO_EXTI | GPIO_PORTA | GPIO_PIN0) GPIO_EXTI | GPIO_PORTA | GPIO_PIN0)
#define GPIO_MAX3421E_RST (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz | \ #define GPIO_MAX3421E_RST (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1) GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1)
#define GPIO_MAX3421E_GPX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | \
GPIO_PORTC | GPIO_PIN5)
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
drivers/usbhost/usbhost_max3421e.c
+1 -5
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@@ -4875,11 +4875,7 @@ max3421e_usbhost_initialize(FAR const struct max3421e_lowerhalf_s *lower)
goto errout_with_alloc; goto errout_with_alloc;
} }
/* Drive Vbus +5V (the smoke test). /* Drive Vbus +5V (the smoke test). */
*
* REVISIT: Should be done elsewhere in order to support device self-
* powered mode? How does the MAX3421E VBUS detect logic work?
*/
lower->power(lower, true); lower->power(lower, true);
include/nuttx/usb/max3421e.h
+3 -2
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@@ -459,7 +459,8 @@ struct max3421e_lowerhalf_s
* attach - Attach the interrupt handler to the GPIO interrupt * attach - Attach the interrupt handler to the GPIO interrupt
* enable - Enable or disable the GPIO interrupt * enable - Enable or disable the GPIO interrupt
* acknowledge - Acknowledge/clear any pending GPIO interrupt * acknowledge - Acknowledge/clear any pending GPIO interrupt
* power - Enable or disable 5V VBUS power * power - Enable or disable 5V VBUS power. REVISIT: Often a
* GPIO from the MAX3421E is used to control VBUS power.
*/ */
CODE int (*attach)(FAR const struct max3421e_lowerhalf_s *lower, CODE int (*attach)(FAR const struct max3421e_lowerhalf_s *lower,
@@ -468,7 +469,7 @@ struct max3421e_lowerhalf_s
bool enable); bool enable);
CODE void (*acknowledge)(FAR const struct max3421e_lowerhalf_s *lower); CODE void (*acknowledge)(FAR const struct max3421e_lowerhalf_s *lower);
CODE void (*power)(FAR const struct max3421e_lowerhalf_s *lower, CODE void (*power)(FAR const struct max3421e_lowerhalf_s *lower,
bool enable); bool enable);
/* Additional, driver-specific state data may follow */ /* Additional, driver-specific state data may follow */
}; };