diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c
index b194fc9c7ae..ae2b06b25f8 100644
--- a/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -49,6 +49,24 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 78000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_2
+#else
+#  error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -522,16 +540,11 @@ static void stm32_stdclockconfig(void)
   regval |= RCC_CR_HSEON;           /* Enable HSE */
   putreg32(regval, STM32_RCC_CR);
 
-  /* Set flash wait states
-   * Sysclk runs with 72MHz -> 2 waitstates.
-   * 0WS from 0-24MHz
-   * 1WS from 24-48MHz
-   * 2WS from 48-72MHz
-   */
+  /* Enable prefetch buffer and set FLASH wait states */
 
   regval  = getreg32(STM32_FLASH_ACR);
   regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
   putreg32(regval, STM32_FLASH_ACR);
 
   /* Set up PLL input scaling (with source = PLL2) */
@@ -687,11 +700,11 @@ static void stm32_stdclockconfig(void)
 
 #ifndef CONFIG_STM32_VALUELINE
 
-  /* Enable FLASH prefetch buffer and 2 wait states */
+  /* Enable FLASH prefetch buffer and set FLASH wait states */
 
   regval  = getreg32(STM32_FLASH_ACR);
   regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
   putreg32(regval, STM32_FLASH_ACR);
 
 #endif
diff --git a/arch/arm/src/stm32/stm32f20xxx_rcc.c b/arch/arm/src/stm32/stm32f20xxx_rcc.c
index 5347c763016..ac0435cdf27 100644
--- a/arch/arm/src/stm32/stm32f20xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f20xxx_rcc.c
@@ -55,6 +55,27 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-30MHz
+ * 1WS from 30-60MHz
+ * 2WS from 60-90MHz
+ * 3WS from 90-120MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 30000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 60000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 90000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_2
+#elif (STM32_SYSCLK_FREQUENCY <= 120000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_3
+#else
+#  error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -646,10 +667,10 @@ static void stm32_stdclockconfig(void)
       while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
 
       /* Enable FLASH prefetch, instruction cache, data cache,
-       * and 5 wait states.
+       * and set FLASH wait states.
        */
 
-      regval = (FLASH_ACR_LATENCY_5
+      regval = (FLASH_ACR_LATENCY_SETTING
 #ifdef CONFIG_STM32_FLASH_ICACHE
                 | FLASH_ACR_ICEN
 #endif
diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c
index b30a1457020..92b67788919 100644
--- a/arch/arm/src/stm32/stm32f30xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c
@@ -49,6 +49,24 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_2
+#else
+#  error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -431,16 +449,11 @@ static void stm32_stdclockconfig(void)
   regval |= RCC_CR_HSEON;           /* Enable HSE */
   putreg32(regval, STM32_RCC_CR);
 
-  /* Set flash wait states
-   * Sysclk runs with 72MHz -> 2 waitstates.
-   * 0WS from 0-24MHz
-   * 1WS from 24-48MHz
-   * 2WS from 48-72MHz
-   */
+  /* Enable FLASH prefetch buffer and set FLASH wait states */
 
   regval  = getreg32(STM32_FLASH_ACR);
   regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
   putreg32(regval, STM32_FLASH_ACR);
 
   /* Set up PLL input scaling (with source = PLL2) */
@@ -594,11 +607,11 @@ static void stm32_stdclockconfig(void)
 
 #ifndef CONFIG_STM32_VALUELINE
   /* Value-line devices don't implement flash prefetch/waitstates */
-  /* Enable FLASH prefetch buffer and 2 wait states */
+  /* Enable FLASH prefetch buffer and set FLASH wait states */
 
   regval  = getreg32(STM32_FLASH_ACR);
   regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
   putreg32(regval, STM32_FLASH_ACR);
 #endif
 
diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c
index 22ae3583e13..76759fb953c 100644
--- a/arch/arm/src/stm32/stm32f33xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c
@@ -50,6 +50,24 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_2
+#else
+#  error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -435,25 +453,11 @@ static void stm32_stdclockconfig(void)
 
 #endif
 
-  /* Set flash wait states according to sysclk:
-   *
-   *   0WS from 0-24MHz
-   *   1WS from 24-48MHz
-   *   2WS from 48-72MHz
-   */
+  /* Enable FLASH prefetch and wait states */
 
   regval = getreg32(STM32_FLASH_ACR);
   regval &= ~(FLASH_ACR_LATENCY_MASK);
-
-#if STM32_SYSCLK_FREQUENCY <= 24000000
-  regval |= FLASH_ACR_LATENCY_0;
-#elif STM32_SYSCLK_FREQUENCY <= 48000000
-  regval |= FLASH_ACR_LATENCY_1;
-#else
-  regval |= FLASH_ACR_LATENCY_2;
-#endif
-
-  regval |= FLASH_ACR_PRTFBE;
+  regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
   putreg32(regval, STM32_FLASH_ACR);
 
   /* Select the system clock source (probably the PLL) */
diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c
index 41cb1869de8..3dc1db9d9f5 100644
--- a/arch/arm/src/stm32/stm32f37xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c
@@ -50,6 +50,24 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_2
+#else
+#  error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -527,11 +545,11 @@ static void stm32_stdclockconfig(void)
 
 # endif
 
-  /* Enable FLASH prefetch buffer and 2 wait states */
+  /* Enable FLASH prefetch buffer and set FLASH wait states */
 
   regval  = getreg32(STM32_FLASH_ACR);
   regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
   putreg32(regval, STM32_FLASH_ACR);
 
   /* Set the HCLK source/divider */
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index ed3373d89bf..98ee333743b 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -68,6 +68,33 @@
 
 #define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
 
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-30MHz
+ * 1WS from 30-60MHz
+ * 2WS from 60-90MHz
+ * 3WS from 90-120MHz
+ * 4WS from 120-150MHz
+ * 5WS from 150-180MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 30000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 60000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 90000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_2
+#elif (STM32_SYSCLK_FREQUENCY <= 120000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_3
+#elif (STM32_SYSCLK_FREQUENCY <= 150000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_4
+#elif (STM32_SYSCLK_FREQUENCY <= 180000000)
+#  define FLASH_ACR_LATENCY_SETTING  FLASH_ACR_LATENCY_5
+#else
+#  error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -778,10 +805,10 @@ static void stm32_stdclockconfig(void)
 #endif
 
       /* Enable FLASH prefetch, instruction cache, data cache,
-       * and 5 wait states.
+       * and set FLASH wait states.
        */
 
-      regval = (FLASH_ACR_LATENCY_5
+      regval = (FLASH_ACR_LATENCY_SETTING
 #ifdef CONFIG_STM32_FLASH_ICACHE
                 | FLASH_ACR_ICEN
 #endif