diff --git a/arch/risc-v/src/fe310/Kconfig b/arch/risc-v/src/fe310/Kconfig
index 3ccf9bf9df4..c0b522fca85 100644
--- a/arch/risc-v/src/fe310/Kconfig
+++ b/arch/risc-v/src/fe310/Kconfig
@@ -15,7 +15,7 @@ config ARCH_CHIP_FE310_G002
 	select FE310_HAVE_UART0
 	select FE310_HAVE_GPIO
 	---help---
-		FE310, RV32IMAC 32Mbit SPI-Flash, 16KB SRAM
+		FE310, RV32IMAC 16KB SRAM
 
 endchoice
 
@@ -45,18 +45,3 @@ config FE310_UART0
 	select FE310_UART
 
 endmenu
-
-config FE310_UART_RX_BUF_SIZE
-	int "UART RX Bufer size"
-	default 64
-	depends on FE310_UART
-	---help---
-		Size of RX buffers for FE310 UARTs
-
-config FE310_UART_TX_BUF_SIZE
-	int "UART TX Bufer size"
-	default 64
-	depends on FE310_UART
-	---help---
-		Size of TX buffers for FE310 UARTs
-
diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c
index 030351d14ad..90bdbe11262 100644
--- a/arch/risc-v/src/fe310/fe310_irq.c
+++ b/arch/risc-v/src/fe310/fe310_irq.c
@@ -191,14 +191,10 @@ void up_ack_irq(int irq)
 irqstate_t up_irq_save(void)
 {
   uint32_t oldstat;
-  uint32_t newstat;
 
-  /* Clear machine interrupt enable bit */
-
-  asm volatile ("csrr %0, mstatus": "=r" (oldstat));
-  newstat = oldstat & ~MSTATUS_MIE;
-  asm volatile("csrw mstatus, %0" : /* no output */ : "r" (newstat));
+  /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
 
+  asm volatile ("csrrc %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
   return oldstat;
 }
 
@@ -242,11 +238,8 @@ irqstate_t up_irq_enable(void)
   asm volatile("csrw mie, %0" : /* no output */ : "r" (mie));
 #endif
 
-  /* Set machine interrupt enable (MIE) in mstatus */
-
-  asm volatile ("csrr %0, mstatus": "=r" (oldstat));
-  newstat = oldstat | MSTATUS_MIE;
-  asm volatile("csrw mstatus, %0" : /* no output */ : "r" (newstat));
+  /* Read mstatus & set machine interrupt enable (MIE) in mstatus */
 
+  asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
   return oldstat;
 }
diff --git a/arch/risc-v/src/fe310/fe310_memorymap.h b/arch/risc-v/src/fe310/fe310_memorymap.h
index cdefb15e8ea..e06a7f72be5 100644
--- a/arch/risc-v/src/fe310/fe310_memorymap.h
+++ b/arch/risc-v/src/fe310/fe310_memorymap.h
@@ -39,7 +39,7 @@
 
 #include "hardware/fe310_memorymap.h"
 #include "hardware/fe310_uart.h"
-#include "hardware/fe310_clic.h"
+#include "hardware/fe310_clint.h"
 #include "hardware/fe310_plic.h"
 
 /****************************************************************************
diff --git a/arch/risc-v/src/fe310/fe310_timerisr.c b/arch/risc-v/src/fe310/fe310_timerisr.c
index c1ae8451640..e73c1fc341d 100644
--- a/arch/risc-v/src/fe310/fe310_timerisr.c
+++ b/arch/risc-v/src/fe310/fe310_timerisr.c
@@ -81,17 +81,17 @@ static void fe310_reload_mtimecmp(void)
   if (!_b_tick_started)
     {
       _b_tick_started = true;
-      current = getreg64(FE310_CLIC_MTIME);
+      current = getreg64(FE310_CLINT_MTIME);
     }
   else
     {
-      current = getreg64(FE310_CLIC_MTIMECMP);
+      current = getreg64(FE310_CLINT_MTIMECMP);
     }
 
   uint64_t tick = 100000; /* TODO */
   next = current + tick;
 
-  putreg64(next, FE310_CLIC_MTIMECMP);
+  putreg64(next, FE310_CLINT_MTIMECMP);
 
   spin_unlock_irqrestore(flags);
 }
@@ -129,7 +129,7 @@ void riscv_timer_initialize(void)
 
   (void)irq_attach(FE310_IRQ_MTIMER, fe310_timerisr, NULL);
 
-  /* Reload CLIC mtimecmp */
+  /* Reload CLINT mtimecmp */
 
   fe310_reload_mtimecmp();
 
diff --git a/arch/risc-v/src/fe310/hardware/fe310_clic.h b/arch/risc-v/src/fe310/hardware/fe310_clint.h
similarity index 84%
rename from arch/risc-v/src/fe310/hardware/fe310_clic.h
rename to arch/risc-v/src/fe310/hardware/fe310_clint.h
index 24097f3db9b..1dfdb88e178 100644
--- a/arch/risc-v/src/fe310/hardware/fe310_clic.h
+++ b/arch/risc-v/src/fe310/hardware/fe310_clint.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/fe310/hardware/fe310_clic.h
+ * arch/risc-v/src/fe310/hardware/fe310_clint.h
  *
  *   Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
  *   Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
@@ -30,14 +30,14 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H
-#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H
+#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLINT_H
+#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLINT_H
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define FE310_CLIC_MTIMECMP  (FE310_CLIC_BASE + 0x4000)
-#define FE310_CLIC_MTIME     (FE310_CLIC_BASE + 0xbff8)
+#define FE310_CLINT_MTIMECMP  (FE310_CLINT_BASE + 0x4000)
+#define FE310_CLINT_MTIME     (FE310_CLINT_BASE + 0xbff8)
 
-#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H */
+#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLINT_H */
diff --git a/arch/risc-v/src/fe310/hardware/fe310_memorymap.h b/arch/risc-v/src/fe310/hardware/fe310_memorymap.h
index 0d534f0b729..bbcfc7a6537 100644
--- a/arch/risc-v/src/fe310/hardware/fe310_memorymap.h
+++ b/arch/risc-v/src/fe310/hardware/fe310_memorymap.h
@@ -39,7 +39,7 @@
 
 /* Register Base Address ****************************************************/
 
-#define FE310_CLIC_BASE    0x02000000
+#define FE310_CLINT_BASE   0x02000000
 #define FE310_PLIC_BASE    0x0c000000
 
 #define FE310_GPIO_BASE    0x10012000  /* 0x10012000 - 0x10012fff: GPIO  */
diff --git a/boards/risc-v/fe310/hifive1-revb/README.txt b/boards/risc-v/fe310/hifive1-revb/README.txt
new file mode 100644
index 00000000000..56e050984fc
--- /dev/null
+++ b/boards/risc-v/fe310/hifive1-revb/README.txt
@@ -0,0 +1,32 @@
+1. Download and install toolchain
+
+  $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
+
+2. Build and install qemu
+
+  $ git clone https://github.com/qemu/qemu
+  $ cd qemu
+  $ ./configure --target-list=riscv32-softmmu
+  $ make
+  $ sudo make install
+
+3. Configure and build NuttX
+
+  $ mkdir ./nuttx; cd ./nuttx
+  $ git clone https://bitbucket.org/nuttx/nuttx.git
+  $ git clone https://bitbucket.org/nuttx/apps.git
+  $ cd nuttx
+  $ make distclean
+  $ ./tools/configure.sh hifive1-revb:nsh
+  $ make V=1
+
+4. Run the nuttx with qemu
+
+  $ qemu-system-riscv32 -nographic -machine sifive_e -kernel ./nuttx
+
+5. TODO
+
+  Configure PLL and UART divisor
+  Run nuttx on HiFive1-Rev.B board
+  Support GPIO/SPI/I2C/RTC/WDT/PWM
+  Support RISC-V User mode
diff --git a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig
index 231c422058e..42e5ad3c433 100644
--- a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig
+++ b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig
@@ -21,9 +21,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BINFMT_DISABLE=y
 CONFIG_BOARD_LOOPSPERMSEC=15000
 CONFIG_BUILTIN=y
-CONFIG_DEBUG_ASSERTIONS=y
-CONFIG_DEBUG_ERROR=y
-CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEFAULT_SMALL=y
@@ -68,6 +65,8 @@ CONFIG_STDIO_DISABLE_BUFFERING=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=12
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
+CONFIG_UART0_RXBUFSIZE=8
 CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_UART0_TXBUFSIZE=4
 CONFIG_USER_ENTRYPOINT="nsh_main"
 CONFIG_WDOG_INTRESERVE=0