diff --git a/arch/arm64/src/common/arm64_arch_timer.c b/arch/arm64/src/common/arm64_arch_timer.c
index fbc57a9f997..45170807077 100644
--- a/arch/arm64/src/common/arm64_arch_timer.c
+++ b/arch/arm64/src/common/arm64_arch_timer.c
@@ -92,11 +92,6 @@ static inline void arm64_arch_timer_set_relative(uint64_t value)
   write_sysreg(value, cntv_tval_el0);
 }
 
-static inline uint64_t arm64_arch_timer_get_compare(void)
-{
-  return read_sysreg(cntv_cval_el0);
-}
-
 static inline void arm64_arch_timer_enable(bool enable)
 {
   uint64_t value;
diff --git a/arch/arm64/src/common/arm64_cache.c b/arch/arm64/src/common/arm64_cache.c
index d711bb1581a..71cac0f274e 100644
--- a/arch/arm64/src/common/arm64_cache.c
+++ b/arch/arm64/src/common/arm64_cache.c
@@ -85,17 +85,6 @@
     __asm__ volatile ("ic " op ", %0" : : "r" (val) : "memory"); \
   })
 
-/* IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
- * Purpose
- * Invalidate all instruction caches in the Inner Shareable domain of
- * the PE executing the instruction to the Point of Unification.
- */
-
-static inline void __ic_iallu(void)
-{
-  __asm__ volatile ("ic  iallu" : : : "memory");
-}
-
 /* IC IALLU, Instruction Cache Invalidate All to PoU
  * Purpose
  * Invalidate all instruction caches of the PE executing
diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c
index d52f12139e9..7480bc6297b 100644
--- a/arch/arm64/src/common/arm64_gicv3.c
+++ b/arch/arm64/src/common/arm64_gicv3.c
@@ -118,20 +118,6 @@ static inline unsigned long gic_get_rdist(void)
   return g_gic_rdists[this_cpu()];
 }
 
-static inline uint32_t read_gicd_wait_rwp(void)
-{
-  uint32_t value;
-
-  value = getreg32(GICD_CTLR);
-
-  while (value & BIT(GICD_CTLR_RWP))
-    {
-      value = getreg32(GICD_CTLR);
-    }
-
-  return value;
-}
-
 /* Wait for register write pending
  * TODO: add timed wait
  */