diff --git a/Documentation/README.html b/Documentation/README.html index e0094833806..b70ce0f27fc 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

NuttX README Files

-

Last Updated: January 5, 2019

+

Last Updated: January 22, 2019

@@ -125,6 +125,8 @@ nuttx/ | | `- README.txt | |- kwikstik-k40/ | | `- README.txt + | |- launchxl-cc1310/ + | | `- README.txt | |- launchxl-cc1312r1/ | | `- README.txt | |- launchxl-tms57004/ diff --git a/README.txt b/README.txt index 85a2be36ca9..8ec8769bd28 100644 --- a/README.txt +++ b/README.txt @@ -1799,6 +1799,8 @@ nuttx/ | | `- README.txt | |- kwikstik-k40/ | | `- README.txt + | |- launchxl-cc1310/ + | | `- README.txt | |- launchxl-cc1312r1/ | | `- README.txt | |- launchxl-tms57004/ diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs index 31aef3f9dda..ee8b83dcccd 100644 --- a/arch/arm/src/tiva/Make.defs +++ b/arch/arm/src/tiva/Make.defs @@ -103,13 +103,13 @@ endif else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y) CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c - CHIP_CSRCS += cc13x0_trim.c + CHIP_CSRCS += cc13x0_trim.c cc13x0_rom.c else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y) CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c CHIP_CSRCS += cc13x2_aux_sysif.c ifeq ($(CONFIG_ARCH_CHIP_CC13XX_V1),y) - CHIP_CSRCS += cc13x2_v1_trim.c + CHIP_CSRCS += cc13x2_v1_trim.c cc13x2_cc26x2_v1_rom.c else CHIP_CSRCS += cc13x2_v2_trim.c endif diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_rom.c b/arch/arm/src/tiva/cc13xx/cc13x0_rom.c new file mode 100644 index 00000000000..90c21b59600 --- /dev/null +++ b/arch/arm/src/tiva/cc13xx/cc13x0_rom.c @@ -0,0 +1,1110 @@ +/************************************************************************************ + * arch/arm/src/tiva/cc13xx/cc13x0_rom.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This is a port of TI's setup_rom.c file which has a fully compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "hardware/tiva_adi2_refsys.h" +#include "hardware/tiva_adi3_refsys.h" +#include "hardware/tiva_adi4_aux.h" +#include "hardware/tiva_aon_batmon.h" +#include "hardware/tiva_aon_sysctl.h" +#include "hardware/tiva_ccfg.h" +#include "hardware/tiva_ddi0_osc.h" +#include "hardware/tiva_fcfg1.h" + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rom_set_vddr_level + ************************************************************************************/ + +static void rom_set_vddr_level(uint32_t ccfg_modeconf) +{ + uint32_t newTrimRaw; + int32_t targetTrim; + int32_t currentTrim; + int32_t deltaTrim; + + /* VDDS_BOD_LEVEL = 1 means that boost mode is selected - Step up VDDR_TRIM + * to FCFG1..VDDR_TRIM_HH */ + + newTrimRaw = ((HWREG(TIVA_FCFG1_VOLT_TRIM) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_MASK) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_SHIFT); + + targetTrim = rom_signextend_vddrtrim(newTrimRaw); + currentTrim = + rom_signextend_vddrtrim((HWREGB(TIVA_ADI3_REFSYS_DCDCCTL0) & + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK) >> + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT); + + if (currentTrim != targetTrim) + { + /* Disable VDDR BOD */ + + HWREGBITW(TIVA_AON_SYSCTL_RESETCTL, + AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN) = 0; + + while (currentTrim != targetTrim) + { + deltaTrim = targetTrim - currentTrim; + if (deltaTrim > 2) + deltaTrim = 2; + if (deltaTrim < -2) + deltaTrim = -2; + currentTrim += deltaTrim; + + HWREG(TIVA_AON_RTC_SYNC); /* Wait one SCLK_LF period */ + + HWREGH(TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET * 2)) = + (ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK << 8) | ((currentTrim << + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) + & + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK); + + HWREG(TIVA_AON_RTC_SYNC) = 1; /* Force SCLK_LF period + * wait on next read */ + + } + + HWREG(TIVA_AON_RTC_SYNC); /* Wait one SCLK_LF period */ + + HWREG(TIVA_AON_RTC_SYNC) = 1; /* Force SCLK_LF period wait on + * next read */ + + HWREG(TIVA_AON_RTC_SYNC); /* Wait one more SCLK_LF period + * before re-enabling VDDR BOD */ + + HWREGBITW(TIVA_AON_SYSCTL_RESETCTL, + AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN) = 1; + HWREG(TIVA_AON_RTC_SYNC); /* And finally wait for + * VDDR_LOSS_EN setting to + * propagate */ + + } +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rom_setup_coldreset_from_shutdown_cfg1 + ************************************************************************************/ + +void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) +{ + int32_t vddr_sleeptrim; + int32_t vddr_sleepdelta; + + /* Check for CC13xx boost mode The combination VDDR_EXT_LOAD=0 and + * VDDS_BOD_LEVEL=1 is defined to select boost mode */ + + if (((ccfg_modeconf & CCFG_MODE_CONF_VDDR_EXT_LOAD) == 0) && + ((ccfg_modeconf & CCFG_MODE_CONF_VDDS_BOD_LEVEL) != 0)) + { + /* Set VDDS_BOD trim - using masked write {MASK8:DATA8} - TRIM_VDDS_BOD + * is bits[7:3] of ADI3..REFSYSCTL1 - Needs a positive transition on + * BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. Set to 0 + * first to guarantee a positive transition. */ + + HWREGB(TIVA_ADI3_REFSYS_CLR + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET) = + ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + /* VDDS_BOD_LEVEL = 1 means that boost mode is selected + * -Max out the VDDS_BOD trim( = VDDS_BOD_POS_31) + */ + + HWREGH(TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2)) = + (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) | + (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31); + HWREGB(TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET) = + ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + rom_set_vddr_level(ccfg_modeconf); + + vddr_sleeptrim = + rom_signextend_vddrtrim((HWREG(TIVA_FCFG1_VOLT_TRIM) & + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_MASK) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_SHIFT); + } + else + { + vddr_sleeptrim = + rom_signextend_vddrtrim((HWREG(TIVA_FCFG1_LDO_TRIM) & + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_MASK) >> + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_SHIFT); + } + + /* Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer + * (CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA) Read and sign extend VddrSleepDelta + * (in range -8 to +7) */ + + vddr_sleepdelta = + (((int32_t) + (ccfg_modeconf << + (32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_WIDTH - + CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_SHIFT))) >> (32 - + CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_WIDTH)); + /* Calculate new VDDR sleep trim */ + + vddr_sleeptrim = (vddr_sleeptrim + vddr_sleepdelta + 1); + if (vddr_sleeptrim > 21) + vddr_sleeptrim = 21; + if (vddr_sleeptrim < -10) + vddr_sleeptrim = -10; + + /* Write adjusted value using MASKED write (MASK8) */ + + HWREGH(TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_DCDCCTL1_OFFSET * 2)) = + ((ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MASK << 8) | + ((vddr_sleeptrim << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) & + ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MASK)); + + /* 1. Do not allow DCDC to be enabled if in external regulator mode. + * Preventing this by setting both the RECHARGE and the ACTIVE bits bit in + * the CCFG_MODE_CONF copy register (ccfg_modeconf). 2. Adjusted battery + * monitor low limit in internal regulator mode. This is done by setting + * AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + */ + + if (HWREG(TIVA_AON_SYSCTL_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + ccfg_modeconf |= + (CCFG_MODE_CONF_DCDC_RECHARGE_MASK | CCFG_MODE_CONF_DCDC_ACTIVE_MASK); + } + else + { + HWREGBITW(TIVA_AON_BATMON_FLASHPUMPP0, + AON_BATMON_FLASHPUMPP0_LOWLIM_BITN) = 0; + } + + /* Set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE Note: + * Inverse polarity */ + + HWREGBITW(TIVA_AON_SYSCTL_PWRCTL, + AON_SYSCTL_PWRCTL_DCDC_EN_BITN) = + (((ccfg_modeconf >> CCFG_MODE_CONF_DCDC_RECHARGE_SHIFT) & 1) ^ 1); + + /* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE Note: Inverse + * polarity */ + + HWREGBITW(TIVA_AON_SYSCTL_PWRCTL, + AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN) = + (((ccfg_modeconf >> CCFG_MODE_CONF_DCDC_ACTIVE_SHIFT) & 1) ^ 1); +} + +/************************************************************************************ + * Name: rom_setup_coldreset_from_shutdown_cfg2 + ************************************************************************************/ + +void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, + uint32_t ccfg_modeconf) +{ + uint32_t trim; + + /* Following sequence is required for using XOSCHF, if not included devices + * crashes when trying to switch to XOSCHF. Trim CAP settings. Get and set + * trim value for the ANABYPASS_VALUE1 register */ + + trim = rom_setup_get_trim_anabypass_value1(ccfg_modeconf); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_ANABYPASSVAL1_OFFSET, trim); + + /* Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + * RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. */ + + trim = rom_setup_get_trim_rcosc_lfrtunectuntrim(); + rom_ddi_bitfield_write16(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_LFOSCCTL_OFFSET, + (DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM | + DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM), + DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT, trim); + + /* Trim XOSCHF IBIAS THERM. Get and set trim value for the XOSCHF IBIAS THERM + * bit field in the ANABYPASS_VALUE2 register. Other register bit fields are + * set to 0. */ + + trim = rom_setup_get_trim_xosc_hfibiastherm(); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_ANABYPASSVAL2_OFFSET, + trim << DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_SHIFT); + + /* Trim AMPCOMP settings required before switch to XOSCHF */ + + trim = rom_setup_get_trim_ampcompth2(); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_AMPCOMPTH2_OFFSET, trim); + trim = rom_setup_get_trim_ampcompth1(); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_AMPCOMPTH1_OFFSET, trim); + trim = rom_setup_get_trim_ampcompctrl(fcfg1_revision); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_AMPCOMPCTL_OFFSET, trim); + + /* Set trim for DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance + * to FCFG1 setting This is bit[5] in the TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL + * register Using MASK4 write + 1 => writing to bits[7:4] */ + + trim = rom_setup_get_trim_adcshmodeen(fcfg1_revision); + HWREGB(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET + + (TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET * 2) + 1) = (0x20 | (trim << 1)); + + /* Set trim for DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance + * to FCFG1 setting This is bit[4] in the TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL + * register Using MASK4 write + 1 => writing to bits[7:4] */ + + trim = rom_setup_get_trim_adcshvbufen(fcfg1_revision); + HWREGB(TIVA_AUX_DDI0_OSC_BASE + DTIVA_DI_MASK4B_OFFSET + + (TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET * 2) + 1) = (0x10 | (trim)); + + /* Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + * in the TIVA_DDI0_OSC_XOSCHFCTL register in accordance to FCFG1 setting. + * Remaining register bit fields are set to their reset values of 0. */ + + trim = rom_setup_get_trim_xosc_hfctrl(fcfg1_revision); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_XOSCHFCTL_OFFSET, trim); + + /* Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + * (This is bits [18:17] in TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL) (Using MASK4 + * write + 4 => writing to bits[19:16] => (4*4)) (Assuming: + * DDI0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_SHIFT = 17 and + * that DDI0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_MASK = + * 0x00060000) */ + + trim = rom_setup_get_trim_dblrloopfilter_resetvoltage(fcfg1_revision); + HWREGB(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET + + (TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET * 2) + 4) = (0x60 | (trim << 1)); + + /* Update DDI0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + * FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM This is TIVA_DDI0_OSC_ATESTCTL + * bit[7] ( TIVA_DDI0_OSC_ATESTCTL is currently hidden (but=0x00000020)) Using + * MASK4 write + 1 => writing to bits[7:4] */ + + trim = rom_setup_get_trim_rcosc_lfibiastrim(fcfg1_revision); + HWREGB(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET + (0x00000020 * 2) + 1) = + (0x80 | (trim << 3)); + + /* Update DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + * DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write This can be + * simplified since the registers are packed together in the same order both + * in FCFG1 and in the HW register. This spans TIVA_DDI0_OSC_LFOSCCTL + * bits[23:18] Using MASK8 write + 4 => writing to bits[23:16] */ + + trim = rom_setup_get_trim_lfregulator_cmirrwr_ratio(fcfg1_revision); + HWREGH(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET + (TIVA_DDI0_OSC_LFOSCCTL_OFFSET * 2) + 4) = + (0xfc00 | (trim << 2)); + + /* Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + * fields in the TIVA_DDI0_OSC_RADCEXTCFG register in accordance to FCFG1 + * setting. Remaining register bit fields are set to their reset values of 0. */ + + trim = rom_setup_get_trim_radc_extcfg(fcfg1_revision); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0OSC_RADCEXTCFG_OFFSET, trim); + + /* Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done + * for PG2 (This is bit 22 in TIVA_DDI0_OSC_CTL0) */ + + HWREG(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI0_OSC_CTL0_OFFSET) = + DDI0_OSC_CTL0_FORCE_KICKSTART_EN; +} + +/************************************************************************************ + * Name: rom_setup_coldreset_from_shutdown_cfg13 + ************************************************************************************/ + +void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) +{ + uint32_t fcfg1OscConf; + uint32_t trim; + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; + + /* Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz + * XOSC */ + + switch ((ccfg_modeconf & CCFG_MODE_CONF_XOSC_FREQ_MASK) >> + CCFG_MODE_CONF_XOSC_FREQ_SHIFT) + { + case 2: + /* XOSC source is a 48 MHz crystal Do nothing (since this is the reset + * setting) */ + + break; + case 1: + /* XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, + * otherwise skip trimming and default to 24 MHz XOSC) */ + + fcfg1OscConf = HWREG(TIVA_FCFG1_OSC_CONF); + + if ((fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION) == 0) + { + /* This is a HPOSC chip, apply HPOSC settings Set bit + * DDI0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in TIVA_DDI0_OSC_CTL0) */ + + HWREG(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI_OSC_CTL0_OFFSET) = + DDI0_OSC_CTL0_HPOSC_MODE_EN; + + /* ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = + * FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + * ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = + * FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + * ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET = + * FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + * ADI2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN + * (1 bit) ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = + * FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + * ADI2_REFSYS_HPOSCCTL0_SERIES_CAP = + * FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + * ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS = + * FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) */ + + HWREG(TIVA_ADI2_REFSYS_HPOSCCTL2) = + ((HWREG(TIVA_ADI2_REFSYS_HPOSCCTL2) & + ~(ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_MASK | + ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_MASK)) | (((fcfg1OscConf & + FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_MASK) + >> + FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_SHIFT) + << + ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_SHIFT) + | + (((fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_MASK) >> + FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_SHIFT) << + ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)); + HWREG(TIVA_ADI2_REFSYS_HPOSCCTL1) = + ((HWREG(TIVA_ADI2_REFSYS_HPOSCCTL1) & + ~(ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_MASK)) | + (((fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_MASK) >> + FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_SHIFT) << + ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)); + HWREG(TIVA_ADI2_REFSYS_HPOSCCTL0) = + ((HWREG(TIVA_ADI2_REFSYS_HPOSCCTL0) & + ~(ADI2_REFSYS_HPOSCCTL0_FILTER_EN_MASK | + ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MASK | + ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_MASK | + ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_MASK)) | (((fcfg1OscConf & + FCFG1_OSC_CONF_HPOSC_FILTER_EN_MASK) + >> + FCFG1_OSC_CONF_HPOSC_FILTER_EN_SHIFT) + << + ADI2_REFSYS_HPOSCCTL0_FILTER_EN_SHIFT) + | + (((fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_MASK) >> + FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_SHIFT) << + ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT) | + (((fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_MASK) >> + FCFG1_OSC_CONF_HPOSC_SERIES_CAP_SHIFT) << + ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT) | + (((fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_MASK) >> + FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_SHIFT) << + ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_SHIFT)); + break; + } + /* Not a HPOSC chip - fall through to default */ + + default: + /* XOSC source is a 24 MHz crystal (default) Set bit + * DDI0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in TIVA_DDI0_OSC_CTL0) */ + + HWREG(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI0_OSC_CTL0_OFFSET) = + DDI0_OSC_CTL0_XTAL_IS_24M; + break; + } + + /* Set XOSC_HF in bypass mode if CCFG is configured for external TCXO Please + * note that it is up to the customer to make sure that the external clock + * source is up and running before XOSC_HF can be used. */ + + if ((HWREG(TIVA_CCFG_SIZE_AND_DIS_FLAGS) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO) == 0) + { + HWREG(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI0_OSC_XOSCHFCTL_OFFSET) = + DDI0_OSC_XOSCHFCTL_BYPASS; + } + + /* Clear DDI0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 + * in TIVA_DDI0_OSC_CTL0. This is typically already 0 except on Lizard where it + * is set in ROM-boot */ + + HWREG(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_CLR_OFFSET + TIVA_DDI0_OSC_CTL0_OFFSET) = + DDI0_OSC_CTL0_CLK_LOSS_EN; + + /* Setting DDI0_OSC_CTL1_XOSC_HF_FAST_START according to value found in + * FCFG1 + */ + + trim = rom_setup_get_trim_xosc_hffaststart(); + HWREGB(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET + (TIVA_DDI0_OSC_CTL1_OFFSET * 2)) = + (0x30 | trim); + + /* setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION */ + + switch ((ccfg_modeconf & CCFG_MODE_CONF_SCLK_LF_OPTION_MASK) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_SHIFT) + { + case 0: /* XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 + * Hz) */ + + rom_osc_set_clocksource(OSC_SRC_CLK_LF, OSC_XOSC_HF); + rom_setup_aonrtc_subsecinc(0x8637bd); /* RTC_INCREMENT = 2^38 / + * frequency */ + + break; + case 1: /* EXTERNAL signal -> SCLK_LF + * (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + * * Set SCLK_LF to use the same source as SCLK_HF + * * Can be simplified a bit since possible return + * values for HF matches LF settings */ + + currentHfClock = rom_osc_get_clocksource(OSC_SRC_CLK_HF); + rom_osc_set_clocksource(OSC_SRC_CLK_LF, currentHfClock); + while (rom_osc_get_clocksource(OSC_SRC_CLK_LF) != currentHfClock) + { + /* Wait until switched */ + + } + ccfgExtLfClk = HWREG(TIVA_CCFG_EXT_LF_CLK); + rom_setup_aonrtc_subsecinc((ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK) + >> CCFG_EXT_LF_CLK_RTC_INCREMENT_SHIFT); + + /* Route external clock to AON IOC w/hysteresis. Set XOSC_LF in + * bypass mode to allow external 32 kHz clock + */ + + rom_iocport_set_configuration((ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_MASK) >> CCFG_EXT_LF_CLK_DIO_SHIFT, IOC_PORT_AON_CLK32K, IOC_STD_INPUT | IOC_HYST_ENABLE); + + HWREG(TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI0_OSC_CTL0_OFFSET) = + DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + + /* Fall through to set XOSC_LF as SCLK_LF source */ + + case 2: /* XOSC_LF -> SLCK_LF (32768 Hz) */ + + rom_osc_set_clocksource(OSC_SRC_CLK_LF, OSC_XOSC_LF); + break; + default: /* (=3) RCOSC_LF */ + + rom_osc_set_clocksource(OSC_SRC_CLK_LF, OSC_RCOSC_LF); + break; + } + + /* Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 */ + + HWREGB(TIVA_ADI4_AUX_ADCREF1) = + (((HWREG(TIVA_FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_SHIFT) + << ADI_4_AUX_ADCREF1_VTRIM_SHIFT) & ADI_4_AUX_ADCREF1_VTRIM_MASK); + + /* Sync with AON */ + + SysCtrlAonSync(); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_anabypass_value1 + ************************************************************************************/ + +uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf) +{ + uint32_t ui32Fcfg1Value; + uint32_t ui32XoscHfRow; + uint32_t ui32XoscHfCol; + uint32_t trimValue; + + /* Use device specific trim values located in factory configuration area for + * the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in the + * ANABYPASS_VALUE1 register. Value for the other bit fields are set to 0. */ + + ui32Fcfg1Value = HWREG(TIVA_FCFG1_CONFIG_OSC_TOP); + ui32XoscHfRow = ((ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_MASK) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_SHIFT); + ui32XoscHfCol = ((ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_MASK) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_SHIFT); + + if ((ccfg_modeconf & CCFG_MODE_CONF_XOSC_CAP_MOD) == 0) + { + /* XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply + * compensation XOSC_CAPARRAY_DELTA is located in bit[15:8] of + * ccfg_modeconf Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is + * not given by a define and sign extension must therefore be hard coded. + * ( A small test program is created verifying the code lines below: Ref.: + * ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) */ + + int32_t i32CustomerDeltaAdjust = + (((int32_t) + (ccfg_modeconf << + (32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_WIDTH - + CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_SHIFT))) >> (32 - + CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_WIDTH)); + + while (i32CustomerDeltaAdjust < 0) + { + ui32XoscHfCol >>= 1; /* COL 1 step down */ + + if (ui32XoscHfCol == 0) + { /* if COL below minimum */ + + ui32XoscHfCol = 0xffff; /* Set COL to maximum */ + + ui32XoscHfRow >>= 1; /* ROW 1 step down */ + + if (ui32XoscHfRow == 0) + { /* if ROW below minimum */ + + ui32XoscHfRow = 1; /* Set both ROW and COL */ + + ui32XoscHfCol = 1; /* to minimum */ + + } + } + i32CustomerDeltaAdjust++; + } + while (i32CustomerDeltaAdjust > 0) + { + ui32XoscHfCol = (ui32XoscHfCol << 1) | 1; /* COL 1 step up */ + + if (ui32XoscHfCol > 0xffff) + { /* if COL above maximum */ + + ui32XoscHfCol = 1; /* Set COL to minimum */ + + ui32XoscHfRow = (ui32XoscHfRow << 1) | 1; /* ROW 1 step up */ + + if (ui32XoscHfRow > 0xf) + { /* if ROW above maximum */ + + ui32XoscHfRow = 0xf; /* Set both ROW and COL */ + + ui32XoscHfCol = 0xffff; /* to maximum */ + + } + } + i32CustomerDeltaAdjust--; + } + } + + trimValue = + ((ui32XoscHfRow << DDI0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_SHIFT) | + (ui32XoscHfCol << DDI0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_SHIFT)); + + return (trimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_rcosc_lfrtunectuntrim + ************************************************************************************/ + +uint32_t rom_setup_get_trim_rcosc_lfrtunectuntrim(void) +{ + uint32_t trimValue; + + /* Use device specific trim values located in factory configuration area */ + + trimValue = + ((HWREG(TIVA_FCFG1_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_MASK) >> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_SHIFT) << + DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + trimValue |= + ((HWREG(TIVA_FCFG1_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_MASK) >> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_SHIFT) << + DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return (trimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_xosc_hfibiastherm + ************************************************************************************/ + +uint32_t rom_setup_get_trim_xosc_hfibiastherm(void) +{ + uint32_t trimValue; + + /* Use device specific trim value located in factory configuration area */ + + trimValue = + (HWREG(TIVA_FCFG1_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_MASK) >> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return (trimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_ampcompth2 + ************************************************************************************/ + +uint32_t rom_setup_get_trim_ampcompth2(void) +{ + uint32_t trimValue; + uint32_t ui32Fcfg1Value; + + /* Use device specific trim value located in factory configuration area. All + * defined register bit fields have corresponding trim value in the factory + * configuration area */ + + ui32Fcfg1Value = HWREG(TIVA_FCFG1_AMPCOMP_TH2); + trimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_MASK) >> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_SHIFT) << + DDI0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_MASK) >> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_SHIFT) << + DDI0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_MASK) >> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_SHIFT) << + DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_MASK) >> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_SHIFT) << + DDI0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_SHIFT); + + return (trimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_ampcompth1 + ************************************************************************************/ + +uint32_t rom_setup_get_trim_ampcompth1(void) +{ + uint32_t trimValue; + uint32_t ui32Fcfg1Value; + + /* Use device specific trim values located in factory configuration area. All + * defined register bit fields have a corresponding trim value in the factory + * configuration area */ + + ui32Fcfg1Value = HWREG(TIVA_FCFG1_AMPCOMP_TH1); + trimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_MASK) >> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_SHIFT) << + DDI0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_MASK) >> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_SHIFT) << + DDI0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_MASK) >> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_SHIFT) << + DDI0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_MASK) >> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_SHIFT) << + DDI0_OSC_AMPCOMPTH1_HPMRAMP1_TH_SHIFT); + + return (trimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_ampcompctrl + ************************************************************************************/ + +uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) +{ + uint32_t trimValue; + uint32_t ui32Fcfg1Value; + uint32_t ibiasOffset; + uint32_t ibiasInit; + uint32_t modeConf1; + int32_t deltaAdjust; + + /* Use device specific trim values located in factory configuration area. + * Register bit fields without trim values in the factory configuration area + * will be set to the value of 0. */ + + ui32Fcfg1Value = HWREG(TIVA_FCFG1_AMPCOMP_CTRL1); + + ibiasOffset = (ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_MASK) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_SHIFT; + ibiasInit = (ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_MASK) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_SHIFT; + + if ((HWREG(TIVA_CCFG_SIZE_AND_DIS_FLAGS) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_MASK) == 0) + { + /* Adjust with TIVA_DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG */ + + modeConf1 = HWREG(TIVA_CCFG_MODE_CONF_1); + + /* Both fields are signed 4-bit values. This is an assumption when doing + * the sign extension. */ + + deltaAdjust = + (((int32_t) + (modeConf1 << + (32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_WIDTH - + CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_SHIFT))) >> + (32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_WIDTH)); + deltaAdjust += (int32_t) ibiasOffset; + if (deltaAdjust < 0) + { + deltaAdjust = 0; + } + if (deltaAdjust > + (DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_MASK >> + DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT)) + { + deltaAdjust = + (DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_MASK >> + DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT); + } + ibiasOffset = (uint32_t) deltaAdjust; + + deltaAdjust = + (((int32_t) + (modeConf1 << + (32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_WIDTH - + CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_SHIFT))) >> (32 - + CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_WIDTH)); + deltaAdjust += (int32_t)ibiasInit; + if (deltaAdjust < 0) + { + deltaAdjust = 0; + } + if (deltaAdjust > + (DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_MASK >> + DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT)) + { + deltaAdjust = + (DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_MASK >> + DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT); + } + ibiasInit = (uint32_t) deltaAdjust; + } + trimValue = (ibiasOffset << DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT) | + (ibiasInit << DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT); + + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_MASK) >> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_SHIFT) << + DDI0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_MASK) >> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_SHIFT) << + DDI0_OSC_AMPCOMPCTL_CAP_STEP_SHIFT); + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_MASK) >> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_SHIFT) << + DDI0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_SHIFT); + + if (fcfg1_revision >= 0x00000022) + { + trimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_MASK) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_SHIFT) << + DDI0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_SHIFT); + } + + return (trimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_dblrloopfilter_resetvoltage + ************************************************************************************/ + +uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision) +{ + uint32_t dblrLoopFilterResetVoltageValue = 0; /* Reset value */ + + if (fcfg1_revision >= 0x00000020) + { + dblrLoopFilterResetVoltageValue = + (HWREG(TIVA_FCFG1_MISC_OTP_DATA_1) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_MASK) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return (dblrLoopFilterResetVoltageValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_adcshmodeen + ************************************************************************************/ + +uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision) +{ + uint32_t getTrimForAdcShModeEnValue = 1; /* Recommended default setting */ + + if (fcfg1_revision >= 0x00000022) + { + getTrimForAdcShModeEnValue = (HWREG(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_MASK) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return (getTrimForAdcShModeEnValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_adcshvbufen + ************************************************************************************/ + +uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision) +{ + uint32_t getTrimForAdcShVbufEnValue = 1; /* Recommended default setting */ + + if (fcfg1_revision >= 0x00000022) + { + getTrimForAdcShVbufEnValue = (HWREG(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_MASK) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return (getTrimForAdcShVbufEnValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_xosc_hfctrl + ************************************************************************************/ + +uint32_t rom_setup_get_trim_xosc_hfctrl(uint32_t fcfg1_revision) +{ + uint32_t getTrimForXoschfCtlValue = 0; /* Recommended default setting */ + + uint32_t fcfg1Data; + + if (fcfg1_revision >= 0x00000020) + { + fcfg1Data = HWREG(TIVA_FCFG1_MISC_OTP_DATA_1); + getTrimForXoschfCtlValue = + (((fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_MASK) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_SHIFT) << + DDI0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_SHIFT); + + getTrimForXoschfCtlValue |= + (((fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_MASK) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_SHIFT) << + DDI0_OSC_XOSCHFCTL_HP_BUF_ITRIM_SHIFT); + + getTrimForXoschfCtlValue |= + (((fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_MASK) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_SHIFT) << + DDI0_OSC_XOSCHFCTL_LP_BUF_ITRIM_SHIFT); + } + + return (getTrimForXoschfCtlValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_xosc_hffaststart + ************************************************************************************/ + +uint32_t rom_setup_get_trim_xosc_hffaststart(void) +{ + uint32_t ui32XoscHfFastStartValue; + + /* Get value from FCFG1 */ + + ui32XoscHfFastStartValue = (HWREG(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_MASK) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return (ui32XoscHfFastStartValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_radc_extcfg + ************************************************************************************/ + +uint32_t rom_setup_get_trim_radc_extcfg(uint32_t fcfg1_revision) +{ + uint32_t getTrimForRadcExtCfgValue = 0x403f8000; /* Recommended default + * setting */ + + uint32_t fcfg1Data; + + if (fcfg1_revision >= 0x00000020) + { + fcfg1Data = HWREG(TIVA_FCFG1_MISC_OTP_DATA_1); + getTrimForRadcExtCfgValue = + (((fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_MASK) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_SHIFT) << + DDI0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_SHIFT); + + getTrimForRadcExtCfgValue |= + (((fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_MASK) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_SHIFT) << + DDI0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_SHIFT); + + getTrimForRadcExtCfgValue |= + (((fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_MASK) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_SHIFT) << + DDI0_OSC_RADCEXTCFG_IDAC_STEP_SHIFT); + } + + return (getTrimForRadcExtCfgValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_rcosc_lfibiastrim + ************************************************************************************/ + +uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision) +{ + uint32_t trimForRcOscLfIBiasTrimValue = 0; /* Default value */ + + if (fcfg1_revision >= 0x00000022) + { + trimForRcOscLfIBiasTrimValue = (HWREG(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_MASK) + >> FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S; + } + + return (trimForRcOscLfIBiasTrimValue); +} + +/************************************************************************************ + * Name: rom_setup_get_trim_lfregulator_cmirrwr_ratio + ************************************************************************************/ + +uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision) +{ + /* Default value for both fields */ + + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; + + if (fcfg1_revision >= 0x00000022) + { + trimForXoscLfRegulatorAndCmirrwrRatioValue = + (HWREG(TIVA_FCFG1_OSC_CONF) & + (FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_MASK | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_MASK)) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S; + } + + return (trimForXoscLfRegulatorAndCmirrwrRatioValue); +} + +/************************************************************************************ + * Name: rom_setup_cachemode + ************************************************************************************/ + +void rom_setup_cachemode(void) +{ + /* - Make sure to enable aggressive VIMS clock gating for power optimization + * Only for PG2 devices. - Enable cache prefetch enable as default setting + * (Slightly higher power consumption, but higher CPU performance) - IF ( + * CCFG_..._DIS_GPRAM == 1 ) then: Enable cache (set cache mode = 1), even if + * set by ROM boot code (This is done because it's not set by boot code when + * running inside a debugger supporting the Halt In Boot (HIB) + * functionality). else: Set MODE_GPRAM if not already set (see inline + * comments as well) */ + + uint32_t vimsCtlMode0; + + while (HWREGBITW(TIVA_VIMS_STAT, VIMS_STAT_MODE_CHANGING_BITN)) + { + /* Do nothing - wait for an eventual ongoing mode change to complete. + * (There should typically be no wait time here, but need to be sure) */ + + } + + /* Note that Mode=0 is equal to MODE_GPRAM */ + + vimsCtlMode0 = + ((HWREG(TIVA_VIMS_CTL) & ~VIMS_CTL_MODE_MASK) | VIMS_CTL_DYN_CG_EN_MASK | + VIMS_CTL_PREF_EN_MASK); + + if (HWREG(TIVA_CCFG_SIZE_AND_DIS_FLAGS) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM) + { + /* Enable cache (and hence disable GPRAM) */ + + HWREG(TIVA_VIMS_CTL) = (vimsCtlMode0 | VIMS_CTL_MODE_CACHE); + } + else if ((HWREG(TIVA_VIMS_STAT) & VIMS_STAT_MODE_MASK) != + VIMS_STAT_MODE_GPRAM) + { + /* GPRAM is enabled in CCFG but not selected Note: It is recommended to + * go via MODE_OFF when switching to MODE_GPRAM */ + + HWREG(TIVA_VIMS_CTL) = (vimsCtlMode0 | VIMS_CTL_MODE_OFF); + while ((HWREG(TIVA_VIMS_STAT) & VIMS_STAT_MODE_MASK) != + VIMS_STAT_MODE_OFF) + { + /* Do nothing - wait for an eventual mode change to complete (This + * goes fast). */ + + } + HWREG(TIVA_VIMS_CTL) = vimsCtlMode0; + } + else + { + /* Correct mode, but make sure PREF_EN and DYN_CG_EN always are set */ + + HWREG(TIVA_VIMS_CTL) = vimsCtlMode0; + } +} + +/************************************************************************************ + * Name: rom_setup_aonrtc_subsecinc + ************************************************************************************/ + +void rom_setup_aonrtc_subsecinc(uint32_t subsecinc) +{ + /* Loading a new RTCSUBSECINC value is done in 5 steps: 1. Write bit[15:0] of + * new SUBSECINC value to TIVA_AUX_WUC_RTCSUBSECINC0 2. Write bit[23:16] of new + * SUBSECINC value to TIVA_AUX_WUC_RTCSUBSECINC1 3. Set + * AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 4. Wait for + * AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ */ + + HWREG(TIVA_AUX_WUC_RTCSUBSECINC0) = + ((subsecinc) & AUX_WUC_RTCSUBSECINC0_INC15_0_MASK); + HWREG(TIVA_AUX_WUC_RTCSUBSECINC1) = + ((subsecinc >> 16) & AUX_WUC_RTCSUBSECINC1_INC23_16_MASK); + + HWREG(TIVA_AUX_WUC_RTCSUBSECINCCTL) = + AUX_WUC_RTCSUBSECINCCTL_UPD_REQ; + while (! + (HWREGBITW + (TIVA_AUX_WUC_RTCSUBSECINCCTL, + AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN))); + HWREG(TIVA_AUX_WUC_RTCSUBSECINCCTL) = 0; +} diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_rom.h b/arch/arm/src/tiva/cc13xx/cc13x0_rom.h index c086efcc8b4..c53ce3b6ef2 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x0_rom.h @@ -158,426 +158,437 @@ /* AON_EVENT FUNCTIONS */ -#define ROM_AONEventMcuWakeUpSet \ - ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ +#define rom_aon_set_mcuwakeup_event \ + ((void (*)(uint32_t mcuwuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[0]) -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ +#define rom_aon_get_mcuwakeup_event \ + ((uint32_t (*)(uint32_t mcuwuevent)) \ ROM_API_AON_EVENT_TABLE[1]) -#define ROM_AONEventAuxWakeUpSet \ - ((void (*)(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc)) \ +#define rom_aonevent_set_auxwakeup \ + ((void (*)(uint32_t auxwuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[2]) -#define ROM_AONEventAuxWakeUpGet \ - ((uint32_t (*)(uint32_t ui32AUXWUEvent)) \ +#define rom_aonevent_get_auxwakeup \ + ((uint32_t (*)(uint32_t auxwuevent)) \ ROM_API_AON_EVENT_TABLE[3]) -#define ROM_AONEventMcuSet \ - ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ +#define rom_aon_set_mcu_event \ + ((void (*)(uint32_t mcuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[4]) -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ +#define rom_aon_get_mcu_event \ + ((uint32_t (*)(uint32_t mcuevent)) \ ROM_API_AON_EVENT_TABLE[5]) /* AON_WUC FUNCTIONS */ -#define ROM_AONWUCAuxReset \ +#define rom_aonwuc_reset_aux \ ((void (*)(void)) \ ROM_API_AON_WUC_TABLE[3]) -#define ROM_AONWUCRechargeCtrlConfigSet \ - ((void (*)(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)) \ +#define rom_aonwuc_set_rechargectrl_config \ + ((void (*)(bool adaptenable, uint32_t adaptrate, uint32_t period,\ + uint32_t maxperiod)) \ ROM_API_AON_WUC_TABLE[4]) -#define ROM_AONWUCOscConfig \ - ((void (*)(uint32_t ui32Period)) \ +#define rom_aonwuc_oscconfig \ + ((void (*)(uint32_t period)) \ ROM_API_AON_WUC_TABLE[5]) /* AUX_TDC FUNCTIONS */ -#define ROM_AUXTDCConfigSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ +#define rom_aux_set_tdc_config \ + ((void (*)(uint32_t base, uint32_t startcondition, uint32_t stopcondition)) \ ROM_API_AUX_TDC_TABLE[0]) -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_aux_tcd_measurement_done \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_AUX_TDC_TABLE[1]) /* AUX_WUC FUNCTIONS */ -#define ROM_AUXWUCClockEnable \ - ((void (*)(uint32_t ui32Clocks)) \ +#define rom_aonwuc_enable_clock \ + ((void (*)(uint32_t clocks)) \ ROM_API_AUX_WUC_TABLE[0]) -#define ROM_AUXWUCClockDisable \ - ((void (*)(uint32_t ui32Clocks)) \ +#define rom_aonwuc_disable_clock \ + ((void (*)(uint32_t clocks)) \ ROM_API_AUX_WUC_TABLE[1]) -#define ROM_AUXWUCClockStatus \ - ((uint32_t (*)(uint32_t ui32Clocks)) \ +#define rom_aonwuc_status_clock \ + ((uint32_t (*)(uint32_t clocks)) \ ROM_API_AUX_WUC_TABLE[2]) -#define ROM_AUXWUCPowerCtrl \ - ((void (*)(uint32_t ui32PowerMode)) \ +#define rom_aonwuc_powerctrl \ + ((void (*)(uint32_t powermode)) \ ROM_API_AUX_WUC_TABLE[3]) /* DDI FUNCTIONS */ -#define ROM_DDI16BitWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ +#define rom_ddi_write16 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t wrdata)) \ ROM_API_DDI_TABLE[0]) -#define ROM_DDI16BitfieldWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ +#define rom_ddi_bitfield_write16 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t shift, \ + uint16_t data)) \ ROM_API_DDI_TABLE[1]) -#define ROM_DDI16BitRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ +#define rom_ddi_read16 \ + ((uint16_t (*)(uint32_t base, uint32_t regoffset, uint32_t mask)) \ ROM_API_DDI_TABLE[2]) -#define ROM_DDI16BitfieldRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ +#define rom_ddi_bitfield_read16 \ + ((uint16_t (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t shift)) \ ROM_API_DDI_TABLE[3]) /* FLASH FUNCTIONS */ -#define ROM_FlashPowerModeGet \ +#define rom_flash_get_powermode \ ((uint32_t (*)(void)) \ ROM_API_FLASH_TABLE[1]) -#define ROM_FlashProtectionSet \ - ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ +#define rom_set_protection \ + ((void (*)(uint32_t sectoraddress, uint32_t protectmode)) \ ROM_API_FLASH_TABLE[2]) -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ +#define rom_get_protection \ + ((uint32_t (*)(uint32_t sectoraddress)) \ ROM_API_FLASH_TABLE[3]) -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ +#define rom_save_protection \ + ((uint32_t (*)(uint32_t sectoraddress)) \ ROM_API_FLASH_TABLE[4]) -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ +#define rom_read_efuserow \ + ((bool (*)(uint32_t *efusedata, uint32_t rowaddress)) \ ROM_API_FLASH_TABLE[8]) -#define ROM_FlashDisableSectorsForWrite \ +#define rom_disable_writesectors \ ((void (*)(void)) \ ROM_API_FLASH_TABLE[9]) /* I2C FUNCTIONS */ -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ +#define rom_i2cmaster_init_expclk \ + ((void (*)(uint32_t base, uint32_t i2cclk, bool fast)) \ ROM_API_I2C_TABLE[0]) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_i2cmaster_err \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_I2C_TABLE[1]) /* INTERRUPT FUNCTIONS */ -#define ROM_IntPriorityGroupingSet \ - ((void (*)(uint32_t ui32Bits)) \ +#define rom_int_set_prioritygrouping \ + ((void (*)(uint32_t bits)) \ ROM_API_INTERRUPT_TABLE[0]) -#define ROM_IntPriorityGroupingGet \ +#define rom_int_get_prioritygrouping \ ((uint32_t (*)(void)) \ ROM_API_INTERRUPT_TABLE[1]) -#define ROM_IntPrioritySet \ - ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ +#define rom_int_set_priority \ + ((void (*)(uint32_t interrupt, uint8_t priority)) \ ROM_API_INTERRUPT_TABLE[2]) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ +#define rom_int_get_priority \ + ((int32_t (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[3]) -#define ROM_IntEnable \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_enable \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[4]) -#define ROM_IntDisable \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_disable \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[5]) -#define ROM_IntPendSet \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_set_pending \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[6]) -#define ROM_IntPendGet \ - ((bool (*)(uint32_t ui32Interrupt)) \ +#define rom_int_get_pending \ + ((bool (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[7]) -#define ROM_IntPendClear \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_clear_pending \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[8]) /* IOC FUNCTIONS */ -#define ROM_IOCPortConfigureSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ +#define rom_iocport_set_configuration \ + ((void (*)(uint32_t ioid, uint32_t portid, uint32_t ioconfig)) \ ROM_API_IOC_TABLE[0]) -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ +#define rom_iocport_get_configuration \ + ((uint32_t (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[1]) -#define ROM_IOCIOShutdownSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ +#define rom_iocio_set_shutdown \ + ((void (*)(uint32_t ioid, uint32_t shutdown)) \ ROM_API_IOC_TABLE[2]) -#define ROM_IOCIOModeSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ +#define rom_iocio_set_mode \ + ((void (*)(uint32_t ioid, uint32_t iomode)) \ ROM_API_IOC_TABLE[4]) -#define ROM_IOCIOIntSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ +#define rom_iocio_set_int \ + ((void (*)(uint32_t ioid, uint32_t int, uint32_t edgedet)) \ ROM_API_IOC_TABLE[5]) -#define ROM_IOCIOPortPullSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ +#define rom_iocio_set_portpullset \ + ((void (*)(uint32_t ioid, uint32_t pull)) \ ROM_API_IOC_TABLE[6]) -#define ROM_IOCIOHystSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ +#define rom_iocio_set_hyst \ + ((void (*)(uint32_t ioid, uint32_t hysteresis)) \ ROM_API_IOC_TABLE[7]) -#define ROM_IOCIOInputSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ +#define rom_iocio_set_input \ + ((void (*)(uint32_t ioid, uint32_t input)) \ ROM_API_IOC_TABLE[8]) -#define ROM_IOCIOSlewCtrlSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ +#define rom_iocio_set_slewctrl \ + ((void (*)(uint32_t ioid, uint32_t slewenable)) \ ROM_API_IOC_TABLE[9]) -#define ROM_IOCIODrvStrengthSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ +#define rom_iocio_set_drvstrength \ + ((void (*)(uint32_t ioid, uint32_t iocurrent, uint32_t drvstrength)) \ ROM_API_IOC_TABLE[10]) -#define ROM_IOCIOPortIdSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ +#define rom_iocio_set_portid \ + ((void (*)(uint32_t ioid, uint32_t portid)) \ ROM_API_IOC_TABLE[11]) -#define ROM_IOCIntEnable \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocint_enable \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[12]) -#define ROM_IOCIntDisable \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocint_disable \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[13]) -#define ROM_IOCPinTypeGpioInput \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_gpioinput \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[14]) -#define ROM_IOCPinTypeGpioOutput \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_gpiooutput \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[15]) -#define ROM_IOCPinTypeUart \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ +#define rom_iocpintype_uart \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t cts, uint32_t rts)) \ ROM_API_IOC_TABLE[16]) -#define ROM_IOCPinTypeSsiMaster \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ +#define rom_iocpintype_ssimaster \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t fss, uint32_t clk)) \ ROM_API_IOC_TABLE[17]) -#define ROM_IOCPinTypeSsiSlave \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ +#define rom_iocpintype_ssislave \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t fss, uint32_t clk)) \ ROM_API_IOC_TABLE[18]) -#define ROM_IOCPinTypeI2c \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ +#define rom_iocpintype_i2c \ + ((void (*)(uint32_t base, uint32_t data, uint32_t clk)) \ ROM_API_IOC_TABLE[19]) -#define ROM_IOCPinTypeAux \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_aux \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[21]) /* PRCM FUNCTIONS */ -#define ROM_PRCMInfClockConfigureSet \ - ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ +#define rom_prcm_set_clockconfig \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t powermode)) \ ROM_API_PRCM_TABLE[0]) -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ +#define rom_prcm_get_clockconfig \ + ((uint32_t (*)(uint32_t powermode)) \ ROM_API_PRCM_TABLE[1]) -#define ROM_PRCMAudioClockConfigSet \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ +#define rom_prcm_set_audioclockconfig \ + ((void (*)(uint32_t clkconfig, uint32_t samplerate)) \ ROM_API_PRCM_TABLE[4]) -#define ROM_PRCMPowerDomainOn \ - ((void (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_on \ + ((void (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[5]) -#define ROM_PRCMPowerDomainOff \ - ((void (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_off \ + ((void (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[6]) -#define ROM_PRCMPeripheralRunEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphrun \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[7]) -#define ROM_PRCMPeripheralRunDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_disable_periphrun \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[8]) -#define ROM_PRCMPeripheralSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[9]) -#define ROM_PRCMPeripheralSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_disable_periphsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[10]) -#define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphdeepsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[11]) -#define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_disable_periphdeepsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[12]) -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_staus \ + ((uint32_t (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[13]) -#define ROM_PRCMDeepSleep \ +#define rom_prcm_deepsleep \ ((void (*)(void)) \ ROM_API_PRCM_TABLE[14]) /* SMPH FUNCTIONS */ -#define ROM_SMPHAcquire \ - ((void (*)(uint32_t ui32Semaphore)) \ +#define rom_smph_acquire \ + ((void (*)(uint32_t semaphore)) \ ROM_API_SMPH_TABLE[0]) /* SSI FUNCTIONS */ -#define ROM_SSIConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ +#define rom_ssi_set_expclkconfig \ + ((void (*)(uint32_t base, uint32_t ssiclk, uint32_t protocol, uint32_t mode, uint32_t \ + bitrate, uint32_t datawidth)) \ ROM_API_SSI_TABLE[0]) -#define ROM_SSIDataPut \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ +#define rom_ssi_put_data \ + ((void (*)(uint32_t base, uint32_t data)) \ ROM_API_SSI_TABLE[1]) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ +#define rom_ssi_put_dataNonBlocking \ + ((int32_t (*)(uint32_t base, uint32_t data)) \ ROM_API_SSI_TABLE[2]) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ +#define rom_ssi_get \ + ((void (*)(uint32_t base, uint32_t *data)) \ ROM_API_SSI_TABLE[3]) -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ +#define rom_ssi_getNonBlocking \ + ((int32_t (*)(uint32_t base, uint32_t *data)) \ ROM_API_SSI_TABLE[4]) /* TIMER FUNCTIONS */ -#define ROM_TimerConfigure \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ +#define rom_timer_configure \ + ((void (*)(uint32_t base, uint32_t config)) \ ROM_API_TIMER_TABLE[0]) -#define ROM_TimerLevelControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ +#define rom_timer_levelcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool invert)) \ ROM_API_TIMER_TABLE[1]) -#define ROM_TimerStallControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ +#define rom_timer_stallcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool stall)) \ ROM_API_TIMER_TABLE[3]) -#define ROM_TimerWaitOnTriggerControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ +#define rom_timer_wait_trigcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool wait)) \ ROM_API_TIMER_TABLE[4]) /* TRNG FUNCTIONS */ -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ +#define rom_trng_get_number \ + ((uint32_t (*)(uint32_t word)) \ ROM_API_TRNG_TABLE[1]) /* UART FUNCTIONS */ -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ +#define rom_uart_get_fifolevel \ + ((void (*)(uint32_t base, uint32_t *txlevel, uint32_t *rxlevel)) \ ROM_API_UART_TABLE[0]) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ +#define rom_uart_set_expclk \ + ((void (*)(uint32_t base, uint32_t uartclk, uint32_t buad, uint32_t config)) \ ROM_API_UART_TABLE[1]) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ +#define rom_uart_get_expclk \ + ((void (*)(uint32_t base, uint32_t uartclk, uint32_t *baud, uint32_t *config)) \ ROM_API_UART_TABLE[2]) -#define ROM_UARTDisable \ - ((void (*)(uint32_t ui32Base)) \ +#define rom_uart_disable \ + ((void (*)(uint32_t base)) \ ROM_API_UART_TABLE[3]) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ +#define rom_uart_getchar_nonblocking \ + ((int32_t (*)(uint32_t base)) \ ROM_API_UART_TABLE[4]) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ +#define rom_uart_getchar \ + ((int32_t (*)(uint32_t base)) \ ROM_API_UART_TABLE[5]) -#define ROM_UARTCharPutNonBlocking \ - ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ +#define rom_uart_putchar_nonblocking \ + ((bool (*)(uint32_t base, uint8_t data)) \ ROM_API_UART_TABLE[6]) -#define ROM_UARTCharPut \ - ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ +#define rom_uart_putchar \ + ((void (*)(uint32_t base, uint8_t data)) \ ROM_API_UART_TABLE[7]) /* UDMA FUNCTIONS */ -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ +#define rom_udmach_enable_attribute \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t attr)) \ ROM_API_UDMA_TABLE[0]) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ +#define rom_udmach_disable_attribute \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t attr)) \ ROM_API_UDMA_TABLE[1]) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ +#define rom_udmach_get_attribute \ + ((uint32_t (*)(uint32_t base, uint32_t channum)) \ ROM_API_UDMA_TABLE[2]) -#define ROM_uDMAChannelControlSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ +#define rom_udmach_set_control \ + ((void (*)(uint32_t base, uint32_t channdx, uint32_t control)) \ ROM_API_UDMA_TABLE[3]) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ +#define rom_udmach_set_scattergather \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t taskcount, void *tasklist, uint32_t periphsg)) \ ROM_API_UDMA_TABLE[5]) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ +#define rom_udmach_set_size \ + ((uint32_t (*)(uint32_t base, uint32_t channdx)) \ ROM_API_UDMA_TABLE[6]) -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ +#define rom_udmach_get_mode \ + ((uint32_t (*)(uint32_t base, uint32_t channdx)) \ ROM_API_UDMA_TABLE[7]) /* VIMS FUNCTIONS */ -#define ROM_VIMSConfigure \ - ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ +#define rom_vims_configure \ + ((void (*)(uint32_t base, bool roundrobin, bool prefetch)) \ ROM_API_VIMS_TABLE[0]) -#define ROM_VIMSModeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ +#define rom_vims_set_mode \ + ((void (*)(uint32_t base, uint32_t mode)) \ ROM_API_VIMS_TABLE[1]) +/* Defines for the AUX power control. Inputs to rom_aonwuc_powerctrl. + * NOTE: These come from the file aux_wuc.h in the TI DriverLib + */ + +#define AUX_WUC_POWER_OFF 0x00000001 +#define AUX_WUC_POWER_DOWN 0x00000002 +#define AUX_WUC_POWER_ACTIVE 0x00000004 + /************************************************************************************ * Public Types ************************************************************************************/ @@ -659,5 +670,66 @@ struct hard_api_s typedef struct hard_api_s hard_api_t; +/************************************************************************************ + * Global Function Prototypes + ************************************************************************************/ + +/* ROM functions implemented in FLASH */ + +void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf); +void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, + uint32_t ccfg_modeconf); +void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf); +uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf); +uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf); +uint32_t rom_setup_get_trim_rcosc_lfrtunectuntrim(void); +uint32_t rom_setup_get_trim_xosc_hfibiastherm(void); +uint32_t rom_setup_get_trim_ampcompth1(void); +uint32_t rom_setup_get_trim_ampcompth2(void); +uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_xosc_hfctrl(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_xosc_hffaststart(void); +uint32_t rom_setup_get_trim_radc_extcfg(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision); +uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision); +void rom_setup_cachemode(void); +void rom_setup_aonrtc_subsecinc(uint32_t subsecinc); + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rom_signextend_vddrtrim + * + * Description: + * Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) + * + * Input Parameters + * vddrtrim - VDDR_TRIM setting + * + * Returned Value: + * Returns sign extended VDDR_TRIM setting. + * + ************************************************************************************/ + +static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) +{ + /* The VDDR trim value is 5 bits representing the range from -10 to +21 + * (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + */ + + int32_t signed_vaddrtrim = vddrtrim; + if (signed_vaddrtrim > 0x15) + { + signed_vaddrtrim -= 0x20; + } + + return signed_vaddrtrim; +} + #endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H */ diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c index bc00b8abc90..655d004e3b3 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c +++ b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c @@ -136,11 +136,18 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) TIVA_ADI3_REFSYS_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2)); } - /* Enable for JTAG to be powered down(will still be powered on if debugger - * is connected) + /* Enable for JTAG to be powered down. The JTAG domain is automatically + * powered up on if a debugger is connected. If a debugger is not + * connected this function can be used to power off the JTAG domain. + * Achieving the lowest power modes (shutdown/powerdown) requires the + * JTAG domain to be turned off. In general the JTAG domain should never + * be powered in production code. + * + * NOTE: This logic comes from the aon_wuc.h header file in the TI + * DriverLib. */ - AONWUCJtagPowerOff(); + putreg32(0, TIVA_AON_WUC_JTAGCFG); /* read the MODE_CONF register in CCFG */ @@ -151,14 +158,13 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * -Configure DCDC. */ - SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg1(ccfg_modeconf); /* Second part of trim done after cold reset and wakeup from shutdown: * -Configure XOSC. */ - SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision, - ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg2(fcfg1_revision, ccfg_modeconf); /* Increased margin between digital supply voltage and VDD BOD during * standby. VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7) @@ -213,11 +219,11 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * -Configure HPOSC. -Setup the LF clock. */ - SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg3(ccfg_modeconf); /* Allow AUX to power down */ - AUXWUCPowerCtrl(AUX_WUC_POWER_DOWN); + rom_aonwuc_powerctrl(AUX_WUC_POWER_DOWN); /* Leaving on AUX and clock for AUX_DDI0_OSC on but turn off clock for * AUX_ADI4 @@ -309,7 +315,7 @@ void cc13xx_trim_device(void) /* Select correct CACHE mode and set correct CACHE configuration */ - SetupSetCacheModeAccordingToCcfgSetting(); + rom_setup_cachemode(); /* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none * of the above. It is always assumed that the application will freeze the diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c new file mode 100644 index 00000000000..4e2d4ff9755 --- /dev/null +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c @@ -0,0 +1,228 @@ +/************************************************************************************ + * arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This is a port of TI's setup_rom.c file which has a fully compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "up_arch.h" + +#include "hardware/tiva_adi2_refsys.h" +#include "hardware/tiva_adi3_refsys.h" +#include "hardware/tiva_adi4_aux.h" +#include "hardware/tiva_aon_batmon.h" +#include "hardware/tiva_aon_pmctl.h" +#include "hardware/tiva_aon_rtc.h" +#include "hardware/tiva_aux_sysif.h" +#include "hardware/tiva_ccfg.h" +#include "hardware/tiva_ddi0_osc.h" +#include "hardware/tiva_fcfg1.h" + +#include "cc13xx/cc13x2_cc26x2_v1_rom.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rom_setup_stepvaddrtrimto + ************************************************************************************/ + +void rom_setup_stepvaddrtrimto(uint32_t tocode) +{ + uint32_t pmctl_regsetctrl; + int32_t target_trim; + int32_t current_trim; + + target_trim = + rom_signextend_vddrtrim(tocode & + (ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK >> + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)); + current_trim = + rom_signextend_vddrtrim((getreg16(TIVA_ADI3_REFSYS_DCDCCTL0) & + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK) >> + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT); + + if (target_trim != current_trim) + { + pmctl_regsetctrl = + (getreg32(TIVA_AON_PMCTL_RESETCTL) & + ~AON_PMCTL_RESETCTL_MCU_WARM_RESET); + if (pmctl_regsetctrl & AON_PMCTL_RESETCTL_VDDR_LOSS_EN) + { + putreg32(pmctl_regsetctrl & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN, + TIVA_AON_PMCTL_RESETCTL); + (void)getreg32(TIVA_AON_RTC_SYNC); /* Wait for VDDR_LOSS_EN + * setting to propagate */ + } + + while (target_trim != current_trim) + { + (void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge + * on SCLK_LF (positive + * or negative) */ + + if (target_trim > current_trim) + current_trim++; + else + current_trim--; + + putreg8(((getreg8(TIVA_ADI3_REFSYS_DCDCCTL0) & + ~ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK) | + ((((uint32_t)current_trim) << + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) & + ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK)), + TIVA_ADI3_REFSYS_DCDCCTL0); + } + + (void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge on + * SCLK_LF (positive or + * negative) */ + + if (pmctl_regsetctrl & AON_PMCTL_RESETCTL_VDDR_LOSS_EN) + { + (void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge + * on SCLK_LF (positive + * or negative) */ + + (void)getreg32(TIVA_AON_RTC_SYNCLF); /* Wait for next edge + * on SCLK_LF (positive + * or negative) */ + + putreg32(pmctl_regsetctrl, TIVA_AON_PMCTL_RESETCTL); + (void)getreg32(TIVA_AON_RTC_SYNC); /* And finally wait for + * VDDR_LOSS_EN setting to + * propagate */ + + } + } +} + +/************************************************************************************ + * Name: rom_setup_coldreset_from_shutdown_cfg1 + ************************************************************************************/ + +void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) +{ + uint32_t setbits; + uint32_t clrbits; + + /* Check for CC1352 boost mode The combination VDDR_EXT_LOAD=0 and + * VDDS_BOD_LEVEL=1 is defined to select boost mode */ + + if (((ccfg_modeconf & CCFG_MODE_CONF_VDDR_EXT_LOAD) == 0) && + ((ccfg_modeconf & CCFG_MODE_CONF_VDDS_BOD_LEVEL) != 0)) + { + /* Set VDDS_BOD trim - using masked write {MASK8:DATA8} - TRIM_VDDS_BOD + * is bits[7:3] of ADI3..REFSYSCTL1 - Needs a positive transition on + * BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. Set to 0 + * first to guarantee a positive transition. */ + + putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN, + TIVA_ADI3_REFSYS_CLR + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET); + + /* VDDS_BOD_LEVEL = 1 means that boost mode is selected + * -Max out the VDDS_BOD trim( = VDDS_BOD_POS_31) + */ + + putreg16((ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) | + (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31), + TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2)); + + putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN, + TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET); + + rom_setup_stepvaddrtrimto((getreg32(TIVA_FCFG1_VOLT_TRIM) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_MASK) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_SHIFT); + } + + /* 1. Do not allow DCDC to be enabled if in external regulator mode. + * Preventing this by setting both the RECHARGE and the ACTIVE bits bit in + * the CCFG_MODE_CONF copy register (ccfg_modeconf). 2. Adjusted battery + * monitor low limit in internal regulator mode. This is done by setting + * AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + */ + + if (getreg32(TIVA_AON_PMCTL_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + ccfg_modeconf |= (CCFG_MODE_CONF_DCDC_RECHARGE | + CCFG_MODE_CONF_DCDC_ACTIVE); + } + else + { + modifyreg32(TIVA_AON_BATMON_FLASHPUMPP0, + AON_BATMON_FLASHPUMPP0_LOWLIM, 0); + } + + /* Set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE Note: + * Inverse polarity + */ + + setbits = 0; + clrbits = 0; + + if ((ccfg_modeconf & CCFG_MODE_CONF_DCDC_RECHARGE) != 0) + { + clrbits |= AON_PMCTL_PWRCTL_DCDC_EN; + } + else + { + setbits |= AON_PMCTL_PWRCTL_DCDC_EN; + } + + /* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE Note: Inverse + * polarity + */ + + if ((ccfg_modeconf & CCFG_MODE_CONF_DCDC_ACTIVE) != 0) + { + clrbits |= AON_PMCTL_PWRCTL_DCDC_ACTIVE; + } + else + { + setbits |= AON_PMCTL_PWRCTL_DCDC_ACTIVE; + } + + modifyreg32(TIVA_AON_PMCTL_PWRCTL, clrbits, setbits); +} diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h index 7a4cb16a266..403d361485d 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h @@ -160,654 +160,654 @@ /* AON_EVENT FUNCTIONS */ -#define ROM_AONEventMcuWakeUpSet \ - ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ +#define rom_aon_set_mcuwakeup_event \ + ((void (*)(uint32_t mcuwuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[0]) -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ +#define rom_aon_get_mcuwakeup_event \ + ((uint32_t (*)(uint32_t mcuwuevent)) \ ROM_API_AON_EVENT_TABLE[1]) -#define ROM_AONEventMcuSet \ - ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ +#define rom_aon_set_mcu_event \ + ((void (*)(uint32_t mcuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[4]) -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ +#define rom_aon_get_mcu_event \ + ((uint32_t (*)(uint32_t mcuevent)) \ ROM_API_AON_EVENT_TABLE[5]) /* AON_RTC FUNCTIONS */ -#define ROM_AONRTCCurrent64BitValueGet \ +#define rom_aon_rtc_get64 \ ((uint64_t (*)(void)) \ ROM_API_AON_RTC_TABLE[12]) /* AUX_TDC FUNCTIONS */ -#define ROM_AUXTDCConfigSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ +#define rom_aux_set_tdc_config \ + ((void (*)(uint32_t base, uint32_t startcondition, uint32_t stopcondition)) \ ROM_API_AUX_TDC_TABLE[0]) -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_aux_tcd_measurement_done \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_AUX_TDC_TABLE[1]) /* DDI FUNCTIONS */ -#define ROM_DDI16BitWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ +#define rom_ddi_write16 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t wrdata)) \ ROM_API_DDI_TABLE[0]) -#define ROM_DDI16BitfieldWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ +#define rom_ddi_bitfield_write16 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t shift, uint16_t data)) \ ROM_API_DDI_TABLE[1]) -#define ROM_DDI16BitRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ +#define rom_ddi_read16 \ + ((uint16_t (*)(uint32_t base, uint32_t regoffset, uint32_t mask)) \ ROM_API_DDI_TABLE[2]) -#define ROM_DDI16BitfieldRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ +#define rom_ddi_bitfield_read16 \ + ((uint16_t (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t shift)) \ ROM_API_DDI_TABLE[3]) -#define ROM_DDI32RegWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \ +#define rom_ddi_write32 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t regval)) \ ROM_API_DDI_TABLE[4]) /* FLASH FUNCTIONS */ -#define ROM_FlashPowerModeSet \ - ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \ +#define rom_flash_set_powermode \ + ((void (*)(uint32_t powermode, uint32_t bank_graceperiod, uint32_t pump_graceperiod)) \ ROM_API_FLASH_TABLE[0]) -#define ROM_FlashPowerModeGet \ +#define rom_flash_get_powermode \ ((uint32_t (*)(void)) \ ROM_API_FLASH_TABLE[1]) -#define ROM_FlashProtectionSet \ - ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ +#define rom_set_protection \ + ((void (*)(uint32_t sectoraddress, uint32_t protectmode)) \ ROM_API_FLASH_TABLE[2]) -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ +#define rom_get_protection \ + ((uint32_t (*)(uint32_t sectoraddress)) \ ROM_API_FLASH_TABLE[3]) -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ +#define rom_save_protection \ + ((uint32_t (*)(uint32_t sectoraddress)) \ ROM_API_FLASH_TABLE[4]) -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ +#define rom_read_efuserow \ + ((bool (*)(uint32_t *efusedata, uint32_t rowaddress)) \ ROM_API_FLASH_TABLE[8]) -#define ROM_FlashDisableSectorsForWrite \ +#define rom_disable_writesectors \ ((void (*)(void)) \ ROM_API_FLASH_TABLE[9]) /* I2C FUNCTIONS */ -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ +#define rom_i2cmaster_init_expclk \ + ((void (*)(uint32_t base, uint32_t i2cclk, bool fast)) \ ROM_API_I2C_TABLE[0]) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_i2cmaster_err \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_I2C_TABLE[1]) /* INTERRUPT FUNCTIONS */ -#define ROM_IntPriorityGroupingSet \ - ((void (*)(uint32_t ui32Bits)) \ +#define rom_int_set_prioritygrouping \ + ((void (*)(uint32_t bits)) \ ROM_API_INTERRUPT_TABLE[0]) -#define ROM_IntPriorityGroupingGet \ +#define rom_int_get_prioritygrouping \ ((uint32_t (*)(void)) \ ROM_API_INTERRUPT_TABLE[1]) -#define ROM_IntPrioritySet \ - ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ +#define rom_int_set_priority \ + ((void (*)(uint32_t interrupt, uint8_t priority)) \ ROM_API_INTERRUPT_TABLE[2]) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ +#define rom_int_get_priority \ + ((int32_t (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[3]) -#define ROM_IntEnable \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_enable \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[4]) -#define ROM_IntDisable \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_disable \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[5]) -#define ROM_IntPendSet \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_set_pending \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[6]) -#define ROM_IntPendGet \ - ((bool (*)(uint32_t ui32Interrupt)) \ +#define rom_int_get_pending \ + ((bool (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[7]) -#define ROM_IntPendClear \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_clear_pending \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[8]) /* IOC FUNCTIONS */ -#define ROM_IOCPortConfigureSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ +#define rom_iocport_set_configuration \ + ((void (*)(uint32_t ioid, uint32_t portid, uint32_t ioconfig)) \ ROM_API_IOC_TABLE[0]) -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ +#define rom_iocport_get_configuration \ + ((uint32_t (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[1]) -#define ROM_IOCIOShutdownSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ +#define rom_iocio_set_shutdown \ + ((void (*)(uint32_t ioid, uint32_t shutdown)) \ ROM_API_IOC_TABLE[2]) -#define ROM_IOCIOModeSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ +#define rom_iocio_set_mode \ + ((void (*)(uint32_t ioid, uint32_t iomode)) \ ROM_API_IOC_TABLE[4]) -#define ROM_IOCIOIntSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ +#define rom_iocio_set_int \ + ((void (*)(uint32_t ioid, uint32_t int, uint32_t edgedet)) \ ROM_API_IOC_TABLE[5]) -#define ROM_IOCIOPortPullSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ +#define rom_iocio_set_portpullset \ + ((void (*)(uint32_t ioid, uint32_t pull)) \ ROM_API_IOC_TABLE[6]) -#define ROM_IOCIOHystSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ +#define rom_iocio_set_hyst \ + ((void (*)(uint32_t ioid, uint32_t hysteresis)) \ ROM_API_IOC_TABLE[7]) -#define ROM_IOCIOInputSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ +#define rom_iocio_set_input \ + ((void (*)(uint32_t ioid, uint32_t input)) \ ROM_API_IOC_TABLE[8]) -#define ROM_IOCIOSlewCtrlSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ +#define rom_iocio_set_slewctrl \ + ((void (*)(uint32_t ioid, uint32_t slewenable)) \ ROM_API_IOC_TABLE[9]) -#define ROM_IOCIODrvStrengthSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ +#define rom_iocio_set_drvstrength \ + ((void (*)(uint32_t ioid, uint32_t iocurrent, uint32_t drvstrength)) \ ROM_API_IOC_TABLE[10]) -#define ROM_IOCIOPortIdSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ +#define rom_iocio_set_portid \ + ((void (*)(uint32_t ioid, uint32_t portid)) \ ROM_API_IOC_TABLE[11]) -#define ROM_IOCIntEnable \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocint_enable \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[12]) -#define ROM_IOCIntDisable \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocint_disable \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[13]) -#define ROM_IOCPinTypeGpioInput \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_gpioinput \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[14]) -#define ROM_IOCPinTypeGpioOutput \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_gpiooutput \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[15]) -#define ROM_IOCPinTypeUart \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ +#define rom_iocpintype_uart \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t cts, uint32_t rts)) \ ROM_API_IOC_TABLE[16]) -#define ROM_IOCPinTypeSsiMaster \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ +#define rom_iocpintype_ssimaster \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t fss, uint32_t ioid)) \ ROM_API_IOC_TABLE[17]) -#define ROM_IOCPinTypeSsiSlave \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ +#define rom_iocpintype_ssislave \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t fss, uint32_t ioid)) \ ROM_API_IOC_TABLE[18]) -#define ROM_IOCPinTypeI2c \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ +#define rom_iocpintype_i2c \ + ((void (*)(uint32_t base, uint32_t data, uint32_t ioid)) \ ROM_API_IOC_TABLE[19]) -#define ROM_IOCPinTypeAux \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_aux \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[21]) /* PRCM FUNCTIONS */ -#define ROM_PRCMInfClockConfigureSet \ - ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ +#define rom_prcm_set_clockconfig \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t powermode)) \ ROM_API_PRCM_TABLE[0]) -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ +#define rom_prcm_get_clockconfig \ + ((uint32_t (*)(uint32_t powermode)) \ ROM_API_PRCM_TABLE[1]) -#define ROM_PRCMAudioClockConfigSet \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ +#define rom_prcm_set_audioclockconfig \ + ((void (*)(uint32_t clkconfig, uint32_t samplerate)) \ ROM_API_PRCM_TABLE[4]) -#define ROM_PRCMPowerDomainOn \ - ((void (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_on \ + ((void (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[5]) -#define ROM_PRCMPowerDomainOff \ - ((void (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_off \ + ((void (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[6]) -#define ROM_PRCMPeripheralRunEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphrun \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[7]) -#define ROM_PRCMPeripheralRunDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_disable_periphrun \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[8]) -#define ROM_PRCMPeripheralSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[9]) -#define ROM_PRCMPeripheralSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_disable_periphsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[10]) -#define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphdeepsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[11]) -#define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_disable_periphdeepsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[12]) -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_staus \ + ((uint32_t (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[13]) -#define ROM_PRCMDeepSleep \ +#define rom_prcm_deepsleep \ ((void (*)(void)) \ ROM_API_PRCM_TABLE[14]) -#define ROM_PRCMAudioClockConfigSetOverride \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \ +#define rom_prcm_set_audioclockconfigOverride \ + ((void (*)(uint32_t clkconfig, uint32_t mstdiv, uint32_t bitdiv, uint32_t worddiv)) \ ROM_API_PRCM_TABLE[17]) /* SMPH FUNCTIONS */ -#define ROM_SMPHAcquire \ - ((void (*)(uint32_t ui32Semaphore)) \ +#define rom_smph_acquire \ + ((void (*)(uint32_t semaphore)) \ ROM_API_SMPH_TABLE[0]) /* SSI FUNCTIONS */ -#define ROM_SSIConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ +#define rom_ssi_set_expclkconfig \ + ((void (*)(uint32_t base, uint32_t ssiclk, uint32_t protocol, uint32_t mode, uint32_t bitrate, uint32_t datawidth)) \ ROM_API_SSI_TABLE[0]) -#define ROM_SSIDataPut \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ +#define rom_ssi_put_data \ + ((void (*)(uint32_t base, uint32_t data)) \ ROM_API_SSI_TABLE[1]) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ +#define rom_ssi_put_dataNonBlocking \ + ((int32_t (*)(uint32_t base, uint32_t data)) \ ROM_API_SSI_TABLE[2]) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ +#define rom_ssi_get \ + ((void (*)(uint32_t base, uint32_t *data)) \ ROM_API_SSI_TABLE[3]) -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ +#define rom_ssi_getNonBlocking \ + ((int32_t (*)(uint32_t base, uint32_t *data)) \ ROM_API_SSI_TABLE[4]) /* TIMER FUNCTIONS */ -#define ROM_TimerConfigure \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ +#define rom_timer_configure \ + ((void (*)(uint32_t base, uint32_t config)) \ ROM_API_TIMER_TABLE[0]) -#define ROM_TimerLevelControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ +#define rom_timer_levelcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool invert)) \ ROM_API_TIMER_TABLE[1]) -#define ROM_TimerStallControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ +#define rom_timer_stallcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool stall)) \ ROM_API_TIMER_TABLE[3]) -#define ROM_TimerWaitOnTriggerControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ +#define rom_timer_wait_trigcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool wait)) \ ROM_API_TIMER_TABLE[4]) -#define ROM_TimerIntervalLoadMode \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ +#define rom_timer_interval_loadmode \ + ((void (*)(uint32_t base, uint32_t timer, uint32_t mode)) \ ROM_API_TIMER_TABLE[5]) -#define ROM_TimerMatchUpdateMode \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ +#define rom_timer_update_matchmode \ + ((void (*)(uint32_t base, uint32_t timer, uint32_t mode)) \ ROM_API_TIMER_TABLE[6]) /* TRNG FUNCTIONS */ -#define ROM_TRNGConfigure \ - ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \ +#define rom_trng_configure \ + ((void (*)(uint32_t min_sampespercycle, uint32_t max_sampespercycle, uint32_t clockspercycle)) \ ROM_API_TRNG_TABLE[0]) -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ +#define rom_trng_get_number \ + ((uint32_t (*)(uint32_t word)) \ ROM_API_TRNG_TABLE[1]) /* UART FUNCTIONS */ -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ +#define rom_uart_get_fifolevel \ + ((void (*)(uint32_t base, uint32_t *txlevel, uint32_t *rxlevel)) \ ROM_API_UART_TABLE[0]) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ +#define rom_uart_set_expclk \ + ((void (*)(uint32_t base, uint32_t uartclk, uint32_t baud, uint32_t config)) \ ROM_API_UART_TABLE[1]) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ +#define rom_uart_get_expclk \ + ((void (*)(uint32_t base, uint32_t uartclk, uint32_t *baud, uint32_t *config)) \ ROM_API_UART_TABLE[2]) -#define ROM_UARTDisable \ - ((void (*)(uint32_t ui32Base)) \ +#define rom_uart_disable \ + ((void (*)(uint32_t base)) \ ROM_API_UART_TABLE[3]) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ +#define rom_uart_getchar_nonblocking \ + ((int32_t (*)(uint32_t base)) \ ROM_API_UART_TABLE[4]) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ +#define rom_uart_getchar \ + ((int32_t (*)(uint32_t base)) \ ROM_API_UART_TABLE[5]) -#define ROM_UARTCharPutNonBlocking \ - ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ +#define rom_uart_putchar_nonblocking \ + ((bool (*)(uint32_t base, uint8_t data)) \ ROM_API_UART_TABLE[6]) -#define ROM_UARTCharPut \ - ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ +#define rom_uart_putchar \ + ((void (*)(uint32_t base, uint8_t data)) \ ROM_API_UART_TABLE[7]) /* UDMA FUNCTIONS */ -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ +#define rom_udmach_enable_attribute \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t attr)) \ ROM_API_UDMA_TABLE[0]) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ +#define rom_udmach_disable_attribute \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t attr)) \ ROM_API_UDMA_TABLE[1]) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ +#define rom_udmach_get_attribute \ + ((uint32_t (*)(uint32_t base, uint32_t channum)) \ ROM_API_UDMA_TABLE[2]) -#define ROM_uDMAChannelControlSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ +#define rom_udmach_set_control \ + ((void (*)(uint32_t base, uint32_t channdx, uint32_t control)) \ ROM_API_UDMA_TABLE[3]) -#define ROM_uDMAChannelTransferSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \ +#define rom_udmach_set_transfer \ + ((void (*)(uint32_t base, uint32_t channdx, uint32_t mode, void *srcaddr, void *destaddr, uint32_t xfrsize)) \ ROM_API_UDMA_TABLE[4]) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ +#define rom_udmach_set_scattergather \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t taskcount, void *tasklist, uint32_t periphsg)) \ ROM_API_UDMA_TABLE[5]) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ +#define rom_udmach_set_size \ + ((uint32_t (*)(uint32_t base, uint32_t channdx)) \ ROM_API_UDMA_TABLE[6]) -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ +#define rom_udmach_get_mode \ + ((uint32_t (*)(uint32_t base, uint32_t channdx)) \ ROM_API_UDMA_TABLE[7]) /* VIMS FUNCTIONS */ -#define ROM_VIMSConfigure \ - ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ +#define rom_vims_configure \ + ((void (*)(uint32_t base, bool roundrobin, bool prefetch)) \ ROM_API_VIMS_TABLE[0]) -#define ROM_VIMSModeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ +#define rom_vims_set_mode \ + ((void (*)(uint32_t base, uint32_t mode)) \ ROM_API_VIMS_TABLE[1]) -#define ROM_VIMSModeGet \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_vims_get_mode \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_VIMS_TABLE[2]) -#define ROM_VIMSModeSafeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ +#define rom_vims_set_modesafe \ + ((void (*)(uint32_t base, uint32_t newmode, bool blocking)) \ ROM_API_VIMS_TABLE[3]) /* CRYPTO FUNCTIONS */ -#define ROM_CRYPTOAesEcb \ - ((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \ +#define rom_crypto_aesecb \ + ((uint32_t (*)(uint32_t *msgin, uint32_t *msgout, uint32_t keylocation, bool encrypt, bool brom_int_enable)) \ ROM_API_CRYPTO_TABLE[0]) -#define ROM_CRYPTOAesEcbStatus \ +#define rom_crypto_aesecbStatus \ ((uint32_t (*)(void)) \ ROM_API_CRYPTO_TABLE[1]) -#define ROM_CRYPTOCcmAuthEncrypt \ - ((uint32_t (*)(bool bEncrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32PlainText, uint32_t ui32PlainTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \ +#define rom_crypto_encrypt_ccmauth \ + ((uint32_t (*)(bool encrypt, uint32_t authlen, uint32_t *nonce, uint32_t *plaintext, uint32_t plaintextlen, uint32_t *header, uint32_t headerlen, uint32_t keylocation, uint32_t fieldlen, bool brom_int_enable)) \ ROM_API_CRYPTO_TABLE[3]) -#define ROM_CRYPTOCcmAuthEncryptResultGet \ - ((uint32_t (*)(uint32_t ui32TagLength, uint32_t *pui32CcmTag)) \ +#define rom_crypto_encrypt_ccmauthResultGet \ + ((uint32_t (*)(uint32_t ui32TagLength, uint32_t *ccmtag)) \ ROM_API_CRYPTO_TABLE[4]) -#define ROM_CRYPTOCcmAuthEncryptStatus \ +#define rom_crypto_encrypt_ccmauthStatus \ ((uint32_t (*)(void)) \ ROM_API_CRYPTO_TABLE[5]) -#define ROM_CRYPTOCcmInvAuthDecrypt \ - ((uint32_t (*)(bool bDecrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \ +#define rom_crypto_decrypt_ccminvauth \ + ((uint32_t (*)(bool decrypt, uint32_t authlen, uint32_t *nonce, uint32_t *ciphertext, uint32_t ciphertextlen, uint32_t *header, uint32_t headerlen, uint32_t keylocation, uint32_t fieldlen, bool brom_int_enable)) \ ROM_API_CRYPTO_TABLE[6]) -#define ROM_CRYPTOCcmInvAuthDecryptResultGet \ - ((uint32_t (*)(uint32_t ui32AuthLength, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32CcmTag)) \ +#define rom_crypto_decrypt_ccminvauthResultGet \ + ((uint32_t (*)(uint32_t authlen, uint32_t *ciphertext, uint32_t ciphertextlen, uint32_t *ccmtag)) \ ROM_API_CRYPTO_TABLE[7]) -#define ROM_CRYPTOCcmInvAuthDecryptStatus \ +#define rom_crypto_decrypt_ccminvauthStatus \ ((uint32_t (*)(void)) \ ROM_API_CRYPTO_TABLE[8]) -#define ROM_CRYPTOAesCbc \ - ((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, uint32_t *pui32Nonce, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \ +#define rom_crypto_aescbc \ + ((uint32_t (*)(uint32_t *msgin, uint32_t *msgout, uint32_t msglen, uint32_t *nonce, uint32_t keylocation, bool encrypt, bool brom_int_enable)) \ ROM_API_CRYPTO_TABLE[9]) -#define ROM_CRYPTOAesCbcStatus \ +#define rom_crypto_aescbcStatus \ ((uint32_t (*)(void)) \ ROM_API_CRYPTO_TABLE[10]) -#define ROM_CRYPTODmaDisable \ - ((void (*)(uint32_t ui32Channels)) \ +#define rom_crypto_disable_dma \ + ((void (*)(uint32_t channels)) \ ROM_API_CRYPTO_TABLE[11]) -#define ROM_CRYPTODmaEnable \ - ((void (*)(uint32_t ui32Channels)) \ +#define rom_crypto_enable_dma \ + ((void (*)(uint32_t channels)) \ ROM_API_CRYPTO_TABLE[12]) /* OSC FUNCTIONS */ -#define ROM_OSCClockSourceGet \ - ((uint32_t (*)(uint32_t ui32SrcClk)) \ +#define rom_osc_get_clocksource \ + ((uint32_t (*)(uint32_t srcclk)) \ ROM_API_OSC_TABLE[0]) -#define ROM_OSCClockSourceSet \ - ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ +#define rom_osc_set_clocksource \ + ((void (*)(uint32_t srcclk, uint32_t osc)) \ ROM_API_OSC_TABLE[1]) -#define ROM_OSC_HPOSCRelativeFrequencyOffsetGet \ - ((int32_t (*)(int32_t tempDegC)) \ +#define rom_hposc_get_relfrequencyoffset \ + ((int32_t (*)(int32_t tempdegC)) \ ROM_API_OSC_TABLE[2]) -#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ - ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ +#define rom_hposc_convert_relfrequencyoffset_to_rfcoreformat \ + ((int16_t (*)(int32_t hposc_relfreqoffset)) \ ROM_API_OSC_TABLE[3]) /* AUX_ADC FUNCTIONS */ -#define ROM_AUXADCAdjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ +#define rom_auxadc_adjust_gainoffset \ + ((int32_t (*)(int32_t adcvalue, int32_t gain, int32_t offset)) \ ROM_API_AUX_ADC_TABLE[0]) -#define ROM_AUXADCDisable \ +#define rom_auxadc_disable \ ((void (*)(void)) \ ROM_API_AUX_ADC_TABLE[1]) -#define ROM_AUXADCDisableInputScaling \ +#define rom_auxadc_disableInputScaling \ ((void (*)(void)) \ ROM_API_AUX_ADC_TABLE[2]) -#define ROM_AUXADCEnableAsync \ - ((void (*)(uint32_t refSource, uint32_t trigger)) \ +#define rom_auxadc_enable_async \ + ((void (*)(uint32_t refsource, uint32_t trigger)) \ ROM_API_AUX_ADC_TABLE[3]) -#define ROM_AUXADCEnableSync \ - ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \ +#define rom_auxadc_enable_sync \ + ((void (*)(uint32_t refsource, uint32_t sampletime, uint32_t trigger)) \ ROM_API_AUX_ADC_TABLE[4]) -#define ROM_AUXADCFlushFifo \ +#define rom_auxadc_flush_fifo \ ((void (*)(void)) \ ROM_API_AUX_ADC_TABLE[5]) -#define ROM_AUXADCGetAdjustmentGain \ - ((int32_t (*)(uint32_t refSource)) \ +#define rom_auxadc_get_adjustmentgain \ + ((int32_t (*)(uint32_t refsource)) \ ROM_API_AUX_ADC_TABLE[6]) -#define ROM_AUXADCGetAdjustmentOffset \ - ((int32_t (*)(uint32_t refSource)) \ +#define rom_auxadc_get_adjustoffset \ + ((int32_t (*)(uint32_t refsource)) \ ROM_API_AUX_ADC_TABLE[7]) -#define ROM_AUXADCMicrovoltsToValue \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \ +#define rom_auxadc_microvolts_to_value \ + ((int32_t (*)(int32_t fixedrefvoltage, int32_t microvolts)) \ ROM_API_AUX_ADC_TABLE[8]) -#define ROM_AUXADCPopFifo \ +#define rom_auxadc_pop_fifo \ ((uint32_t (*)(void)) \ ROM_API_AUX_ADC_TABLE[9]) -#define ROM_AUXADCReadFifo \ +#define rom_auxadc_read_fifo \ ((uint32_t (*)(void)) \ ROM_API_AUX_ADC_TABLE[10]) -#define ROM_AUXADCUnadjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ +#define rom_auxadc_unadjust_gainoffset \ + ((int32_t (*)(int32_t adcvalue, int32_t gain, int32_t offset)) \ ROM_API_AUX_ADC_TABLE[11]) -#define ROM_AUXADCValueToMicrovolts \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \ +#define rom_auxadc_value_to_microvolts \ + ((int32_t (*)(int32_t fixedrefvoltage, int32_t adcvalue)) \ ROM_API_AUX_ADC_TABLE[12]) /* SYS_CTRL FUNCTIONS */ -#define ROM_SysCtrlResetSourceGet \ +#define rom_sysctrl_get_resetsource \ ((uint32_t (*)(void)) \ ROM_API_SYS_CTRL_TABLE[0]) -#define ROM_SysCtrl_DCDC_VoltageConditionalControl \ +#define rom_sysctrl_dcdc_voltagecondcontrol \ ((void (*)(void)) \ ROM_API_SYS_CTRL_TABLE[1]) /* AON_BATMON FUNCTIONS */ -#define ROM_AONBatMonTemperatureGetDegC \ +#define rom_aonbatmaon_get_temperatureC \ ((int32_t (*)(void)) \ ROM_API_AON_BATMON_TABLE[0]) /* SETUP_ROM FUNCTIONS */ -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ - ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_coldreset_from_shutdown_cfg2 \ + ((void (*)(uint32_t fcfg1_revision, uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[1]) -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_coldreset_from_shutdown_cfg3 \ + ((void (*)(uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[2]) -#define ROM_SetupGetTrimForAdcShModeEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_adcshmodeen \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[3]) -#define ROM_SetupGetTrimForAdcShVbufEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_adcshvbufen \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[4]) -#define ROM_SetupGetTrimForAmpcompCtrl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_ampcompctrl \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[5]) -#define ROM_SetupGetTrimForAmpcompTh1 \ +#define rom_setup_get_trim_ampcompth1 \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[6]) -#define ROM_SetupGetTrimForAmpcompTh2 \ +#define rom_setup_get_trim_ampcompth2 \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[7]) -#define ROM_SetupGetTrimForAnabypassValue1 \ - ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_get_trim_anabypass_value1 \ + ((uint32_t (*)(uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[8]) -#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_dblrloopfilter_resetvoltage \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[9]) -#define ROM_SetupGetTrimForRadcExtCfg \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_radc_extcfg \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[10]) -#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_rcosc_lfibiastrim \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[11]) -#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \ +#define rom_setup_get_trim_rcosc_lfrtunectuntrim \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[12]) -#define ROM_SetupGetTrimForXoscHfCtl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_xosc_hfctrl \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[13]) -#define ROM_SetupGetTrimForXoscHfFastStart \ +#define rom_setup_get_trim_xosc_hffaststart \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[14]) -#define ROM_SetupGetTrimForXoscHfIbiastherm \ +#define rom_setup_get_trim_xosc_hfibiastherm \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[15]) -#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_lfregulator_cmirrwr_ratio \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[16]) -#define ROM_SetupSetAonRtcSubSecInc \ - ((void (*)(uint32_t subSecInc)) \ +#define rom_setup_aonrtc_subsecinc \ + ((void (*)(uint32_t subsecinc)) \ ROM_API_SETUP_ROM_TABLE[17]) -#define ROM_SetupSetCacheModeAccordingToCcfgSetting \ +#define rom_setup_cachemode \ ((void (*)(void)) \ ROM_API_SETUP_ROM_TABLE[18]) /* I2S FUNCTIONS */ -#define ROM_I2SPointerSet \ - ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \ +#define rom_i2s_set_pointer \ + ((void (*)(uint32_t base, bool input, void *nextpointer)) \ ROM_API_I2S_TABLE[0]) -#define ROM_I2SSampleStampGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \ +#define rom_i2s_get_samplestamp \ + ((uint32_t (*)(uint32_t base, uint32_t channel)) \ ROM_API_I2S_TABLE[1]) /* PWR_CTRL FUNCTIONS */ -#define ROM_PowerCtrlSourceSet \ - ((void (*)(uint32_t ui32PowerConfig)) \ +#define rom_powerctrl_set_source \ + ((void (*)(uint32_t powerconfig)) \ ROM_API_PWR_CTRL_TABLE[0]) /************************************************************************************ @@ -891,5 +891,48 @@ struct hard_api_s typedef struct hard_api_s hard_api_t; +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rom_signextend_vddrtrim + * + * Description: + * Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) + * + * Input Parameters + * vddrtrim - VDDR_TRIM setting + * + * Returned Value: + * Returns sign extended VDDR_TRIM setting. + * + ************************************************************************************/ + +static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) +{ + /* The VDDR trim value is 5 bits representing the range from -10 to +21 + * (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + */ + + int32_t signed_vaddrtrim = vddrtrim; + if (signed_vaddrtrim > 0x15) + { + signed_vaddrtrim -= 0x20; + } + + return signed_vaddrtrim; +} + +/************************************************************************************ + * Global Function Prototypes + ************************************************************************************/ + +/* ROM functions implemented in FLASH */ + +void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf); +void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf); +void rom_setup_stepvaddrtrimto(uint32_t tocode); + #endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H */ diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h index 6284f6d44ee..fc85b572f80 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h @@ -163,773 +163,806 @@ /* AON_EVENT FUNCTIONS */ -#define ROM_AONEventMcuWakeUpSet \ - ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ +#define rom_aon_set_mcuwakeup_event \ + ((void (*)(uint32_t mcuwuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[0]) -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ +#define rom_aon_get_mcuwakeup_event \ + ((uint32_t (*)(uint32_t mcuwuevent)) \ ROM_API_AON_EVENT_TABLE[1]) -#define ROM_AONEventMcuSet \ - ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ +#define rom_aon_set_mcu_event \ + ((void (*)(uint32_t mcuevent, uint32_t eventsrc)) \ ROM_API_AON_EVENT_TABLE[4]) -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ +#define rom_aon_get_mcu_event \ + ((uint32_t (*)(uint32_t mcuevent)) \ ROM_API_AON_EVENT_TABLE[5]) /* AON_RTC FUNCTIONS */ -#define ROM_AONRTCCurrent64BitValueGet \ +#define rom_aon_rtc_get64 \ ((uint64_t (*)(void)) \ ROM_API_AON_RTC_TABLE[12]) /* AUX_TDC FUNCTIONS */ -#define ROM_AUXTDCConfigSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ +#define rom_aux_set_tdc_config \ + ((void (*)(uint32_t base, uint32_t startcondition, uint32_t stopcondition)) \ ROM_API_AUX_TDC_TABLE[0]) -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_aux_tcd_measurement_done \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_AUX_TDC_TABLE[1]) /* DDI FUNCTIONS */ -#define ROM_DDI16BitWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ +#define rom_ddi_write16 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t wrdata)) \ ROM_API_DDI_TABLE[0]) -#define ROM_DDI16BitfieldWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ +#define rom_ddi_bitfield_write16 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t shift, \ + uint16_t data)) \ ROM_API_DDI_TABLE[1]) -#define ROM_DDI16BitRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ +#define rom_ddi_read16 \ + ((uint16_t (*)(uint32_t base, uint32_t regoffset, uint32_t mask)) \ ROM_API_DDI_TABLE[2]) -#define ROM_DDI16BitfieldRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ +#define rom_ddi_bitfield_read16 \ + ((uint16_t (*)(uint32_t base, uint32_t regoffset, uint32_t mask, uint32_t shift)) \ ROM_API_DDI_TABLE[3]) -#define ROM_DDI32RegWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \ +#define rom_ddi_write32 \ + ((void (*)(uint32_t base, uint32_t regoffset, uint32_t regval)) \ ROM_API_DDI_TABLE[4]) /* FLASH FUNCTIONS */ -#define ROM_FlashPowerModeSet \ - ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \ +#define rom_flash_set_powermode \ + ((void (*)(uint32_t powermode, uint32_t bank_graceperiod, uint32_t pump_graceperiod)) \ ROM_API_FLASH_TABLE[0]) -#define ROM_FlashPowerModeGet \ +#define rom_flash_get_powermode \ ((uint32_t (*)(void)) \ ROM_API_FLASH_TABLE[1]) -#define ROM_FlashProtectionSet \ - ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ +#define rom_set_protection \ + ((void (*)(uint32_t sectoraddress, uint32_t protectmode)) \ ROM_API_FLASH_TABLE[2]) -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ +#define rom_get_protection \ + ((uint32_t (*)(uint32_t sectoraddress)) \ ROM_API_FLASH_TABLE[3]) -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ +#define rom_save_protection \ + ((uint32_t (*)(uint32_t sectoraddress)) \ ROM_API_FLASH_TABLE[4]) -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ +#define rom_read_efuserow \ + ((bool (*)(uint32_t *efusedata, uint32_t rowaddress)) \ ROM_API_FLASH_TABLE[8]) -#define ROM_FlashDisableSectorsForWrite \ +#define rom_disable_writesectors \ ((void (*)(void)) \ ROM_API_FLASH_TABLE[9]) /* I2C FUNCTIONS */ -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ +#define rom_i2cmaster_init_expclk \ + ((void (*)(uint32_t base, uint32_t i2cclk, bool fast)) \ ROM_API_I2C_TABLE[0]) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_i2cmaster_err \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_I2C_TABLE[1]) /* INTERRUPT FUNCTIONS */ -#define ROM_IntPriorityGroupingSet \ - ((void (*)(uint32_t ui32Bits)) \ +#define rom_int_set_prioritygrouping \ + ((void (*)(uint32_t bits)) \ ROM_API_INTERRUPT_TABLE[0]) -#define ROM_IntPriorityGroupingGet \ +#define rom_int_get_prioritygrouping \ ((uint32_t (*)(void)) \ ROM_API_INTERRUPT_TABLE[1]) -#define ROM_IntPrioritySet \ - ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ +#define rom_int_set_priority \ + ((void (*)(uint32_t interrupt, uint8_t priority)) \ ROM_API_INTERRUPT_TABLE[2]) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ +#define rom_int_get_priority \ + ((int32_t (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[3]) -#define ROM_IntEnable \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_enable \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[4]) -#define ROM_IntDisable \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_disable \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[5]) -#define ROM_IntPendSet \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_set_pending \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[6]) -#define ROM_IntPendGet \ - ((bool (*)(uint32_t ui32Interrupt)) \ +#define rom_int_get_pending \ + ((bool (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[7]) -#define ROM_IntPendClear \ - ((void (*)(uint32_t ui32Interrupt)) \ +#define rom_int_clear_pending \ + ((void (*)(uint32_t interrupt)) \ ROM_API_INTERRUPT_TABLE[8]) /* IOC FUNCTIONS */ -#define ROM_IOCPortConfigureSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ +#define rom_iocport_set_configuration \ + ((void (*)(uint32_t ioid, uint32_t portid, uint32_t ioconfig)) \ ROM_API_IOC_TABLE[0]) -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ +#define rom_iocport_get_configuration \ + ((uint32_t (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[1]) -#define ROM_IOCIOShutdownSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ +#define rom_iocio_set_shutdown \ + ((void (*)(uint32_t ioid, uint32_t shutdown)) \ ROM_API_IOC_TABLE[2]) -#define ROM_IOCIOModeSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ +#define rom_iocio_set_mode \ + ((void (*)(uint32_t ioid, uint32_t iomode)) \ ROM_API_IOC_TABLE[4]) -#define ROM_IOCIOIntSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ +#define rom_iocio_set_int \ + ((void (*)(uint32_t ioid, uint32_t int, uint32_t edgedet)) \ ROM_API_IOC_TABLE[5]) -#define ROM_IOCIOPortPullSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ +#define rom_iocio_set_portpullset \ + ((void (*)(uint32_t ioid, uint32_t pull)) \ ROM_API_IOC_TABLE[6]) -#define ROM_IOCIOHystSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ +#define rom_iocio_set_hyst \ + ((void (*)(uint32_t ioid, uint32_t hysteresis)) \ ROM_API_IOC_TABLE[7]) -#define ROM_IOCIOInputSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ +#define rom_iocio_set_input \ + ((void (*)(uint32_t ioid, uint32_t input)) \ ROM_API_IOC_TABLE[8]) -#define ROM_IOCIOSlewCtrlSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ +#define rom_iocio_set_slewctrl \ + ((void (*)(uint32_t ioid, uint32_t slewenable)) \ ROM_API_IOC_TABLE[9]) -#define ROM_IOCIODrvStrengthSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ +#define rom_iocio_set_drvstrength \ + ((void (*)(uint32_t ioid, uint32_t iocurrent, uint32_t drvstrength)) \ ROM_API_IOC_TABLE[10]) -#define ROM_IOCIOPortIdSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ +#define rom_iocio_set_portid \ + ((void (*)(uint32_t ioid, uint32_t portid)) \ ROM_API_IOC_TABLE[11]) -#define ROM_IOCIntEnable \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocint_enable \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[12]) -#define ROM_IOCIntDisable \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocint_disable \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[13]) -#define ROM_IOCPinTypeGpioInput \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_gpioinput \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[14]) -#define ROM_IOCPinTypeGpioOutput \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_gpiooutput \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[15]) -#define ROM_IOCPinTypeUart \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ +#define rom_iocpintype_uart \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t cts, uint32_t rts)) \ ROM_API_IOC_TABLE[16]) -#define ROM_IOCPinTypeSsiMaster \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ +#define rom_iocpintype_ssimaster \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t fss, uint32_t ioid)) \ ROM_API_IOC_TABLE[17]) -#define ROM_IOCPinTypeSsiSlave \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ +#define rom_iocpintype_ssislave \ + ((void (*)(uint32_t base, uint32_t rx, uint32_t tx, uint32_t fss, uint32_t ioid)) \ ROM_API_IOC_TABLE[18]) -#define ROM_IOCPinTypeI2c \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ +#define rom_iocpintype_i2c \ + ((void (*)(uint32_t base, uint32_t data, uint32_t ioid)) \ ROM_API_IOC_TABLE[19]) -#define ROM_IOCPinTypeAux \ - ((void (*)(uint32_t ui32IOId)) \ +#define rom_iocpintype_aux \ + ((void (*)(uint32_t ioid)) \ ROM_API_IOC_TABLE[21]) /* PRCM FUNCTIONS */ -#define ROM_PRCMInfClockConfigureSet \ - ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ +#define rom_prcm_set_clockconfig \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t powermode)) \ ROM_API_PRCM_TABLE[0]) -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ +#define rom_prcm_get_clockconfig \ + ((uint32_t (*)(uint32_t powermode)) \ ROM_API_PRCM_TABLE[1]) -#define ROM_PRCMAudioClockConfigSet \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ +#define rom_prcm_set_audioclockconfig \ + ((void (*)(uint32_t clkconfig, uint32_t samplerate)) \ ROM_API_PRCM_TABLE[4]) -#define ROM_PRCMPowerDomainOn \ - ((void (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_on \ + ((void (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[5]) -#define ROM_PRCMPowerDomainOff \ - ((void (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_off \ + ((void (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[6]) -#define ROM_PRCMPeripheralRunEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphrun \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[7]) -#define ROM_PRCMPeripheralRunDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_disable_periphrun \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[8]) -#define ROM_PRCMPeripheralSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[9]) -#define ROM_PRCMPeripheralSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_disable_periphsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[10]) -#define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_enable_periphdeepsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[11]) -#define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ +#define rom_prcm_disable_periphdeepsleep \ + ((void (*)(uint32_t peripheral)) \ ROM_API_PRCM_TABLE[12]) -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ +#define rom_prcm_powerdomain_staus \ + ((uint32_t (*)(uint32_t domains)) \ ROM_API_PRCM_TABLE[13]) -#define ROM_PRCMDeepSleep \ +#define rom_prcm_deepsleep \ ((void (*)(void)) \ ROM_API_PRCM_TABLE[14]) -#define ROM_PRCMAudioClockConfigSetOverride \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \ +#define rom_prcm_set_audioclockconfigOverride \ + ((void (*)(uint32_t clkconfig, uint32_t mstdiv, uint32_t bitdiv, uint32_t worddiv)) \ ROM_API_PRCM_TABLE[17]) /* SMPH FUNCTIONS */ -#define ROM_SMPHAcquire \ - ((void (*)(uint32_t ui32Semaphore)) \ +#define rom_smph_acquire \ + ((void (*)(uint32_t semaphore)) \ ROM_API_SMPH_TABLE[0]) /* SSI FUNCTIONS */ -#define ROM_SSIConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ +#define rom_ssi_set_expclkconfig \ + ((void (*)(uint32_t base, uint32_t ssiclk, uint32_t protocol, uint32_t mode, \ + uint32_t bitrate, uint32_t datawidth)) \ ROM_API_SSI_TABLE[0]) -#define ROM_SSIDataPut \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ +#define rom_ssi_put_data \ + ((void (*)(uint32_t base, uint32_t data)) \ ROM_API_SSI_TABLE[1]) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ +#define rom_ssi_put_dataNonBlocking \ + ((int32_t (*)(uint32_t base, uint32_t data)) \ ROM_API_SSI_TABLE[2]) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ +#define rom_ssi_get \ + ((void (*)(uint32_t base, uint32_t *data)) \ ROM_API_SSI_TABLE[3]) -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ +#define rom_ssi_getNonBlocking \ + ((int32_t (*)(uint32_t base, uint32_t *data)) \ ROM_API_SSI_TABLE[4]) /* TIMER FUNCTIONS */ -#define ROM_TimerConfigure \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ +#define rom_timer_configure \ + ((void (*)(uint32_t base, uint32_t config)) \ ROM_API_TIMER_TABLE[0]) -#define ROM_TimerLevelControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ +#define rom_timer_levelcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool invert)) \ ROM_API_TIMER_TABLE[1]) -#define ROM_TimerStallControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ +#define rom_timer_stallcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool stall)) \ ROM_API_TIMER_TABLE[3]) -#define ROM_TimerWaitOnTriggerControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ +#define rom_timer_wait_trigcontrol \ + ((void (*)(uint32_t base, uint32_t timer, bool wait)) \ ROM_API_TIMER_TABLE[4]) -#define ROM_TimerIntervalLoadMode \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ +#define rom_timer_interval_loadmode \ + ((void (*)(uint32_t base, uint32_t timer, uint32_t mode)) \ ROM_API_TIMER_TABLE[5]) -#define ROM_TimerMatchUpdateMode \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ +#define rom_timer_update_matchmode \ + ((void (*)(uint32_t base, uint32_t timer, uint32_t mode)) \ ROM_API_TIMER_TABLE[6]) /* TRNG FUNCTIONS */ -#define ROM_TRNGConfigure \ - ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \ +#define rom_trng_configure \ + ((void (*)(uint32_t min_sampespercycle, uint32_t max_sampespercycle, \ + uint32_t clockspercycle)) \ ROM_API_TRNG_TABLE[0]) -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ +#define rom_trng_get_number \ + ((uint32_t (*)(uint32_t word)) \ ROM_API_TRNG_TABLE[1]) /* UART FUNCTIONS */ -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ +#define rom_uart_get_fifolevel \ + ((void (*)(uint32_t base, uint32_t *txlevel, uint32_t *rxlevel)) \ ROM_API_UART_TABLE[0]) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ +#define rom_uart_set_expclk \ + ((void (*)(uint32_t base, uint32_t uartclk, uint32_t baud, uint32_t config)) \ ROM_API_UART_TABLE[1]) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ +#define rom_uart_get_expclk \ + ((void (*)(uint32_t base, uint32_t uartclk, uint32_t *baud, uint32_t *config)) \ ROM_API_UART_TABLE[2]) -#define ROM_UARTDisable \ - ((void (*)(uint32_t ui32Base)) \ +#define rom_uart_disable \ + ((void (*)(uint32_t base)) \ ROM_API_UART_TABLE[3]) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ +#define rom_uart_getchar_nonblocking \ + ((int32_t (*)(uint32_t base)) \ ROM_API_UART_TABLE[4]) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ +#define rom_uart_getchar \ + ((int32_t (*)(uint32_t base)) \ ROM_API_UART_TABLE[5]) -#define ROM_UARTCharPutNonBlocking \ - ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ +#define rom_uart_putchar_nonblocking \ + ((bool (*)(uint32_t base, uint8_t data)) \ ROM_API_UART_TABLE[6]) -#define ROM_UARTCharPut \ - ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ +#define rom_uart_putchar \ + ((void (*)(uint32_t base, uint8_t data)) \ ROM_API_UART_TABLE[7]) /* UDMA FUNCTIONS */ -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ +#define rom_udmach_enable_attribute \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t attr)) \ ROM_API_UDMA_TABLE[0]) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ +#define rom_udmach_disable_attribute \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t attr)) \ ROM_API_UDMA_TABLE[1]) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ +#define rom_udmach_get_attribute \ + ((uint32_t (*)(uint32_t base, uint32_t channum)) \ ROM_API_UDMA_TABLE[2]) -#define ROM_uDMAChannelControlSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ +#define rom_udmach_set_control \ + ((void (*)(uint32_t base, uint32_t channdx, uint32_t control)) \ ROM_API_UDMA_TABLE[3]) -#define ROM_uDMAChannelTransferSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \ +#define rom_udmach_set_transfer \ + ((void (*)(uint32_t base, uint32_t channdx, uint32_t mode, void *srcaddr, \ + void *destaddr, uint32_t xfrsize)) \ ROM_API_UDMA_TABLE[4]) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ +#define rom_udmach_set_scattergather \ + ((void (*)(uint32_t base, uint32_t channum, uint32_t taskcount, void *tasklist, \ + uint32_t periphsg)) \ ROM_API_UDMA_TABLE[5]) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ +#define rom_udmach_set_size \ + ((uint32_t (*)(uint32_t base, uint32_t channdx)) \ ROM_API_UDMA_TABLE[6]) -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ +#define rom_udmach_get_mode \ + ((uint32_t (*)(uint32_t base, uint32_t channdx)) \ ROM_API_UDMA_TABLE[7]) /* VIMS FUNCTIONS */ -#define ROM_VIMSConfigure \ - ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ +#define rom_vims_configure \ + ((void (*)(uint32_t base, bool roundrobin, bool bPrefetch)) \ ROM_API_VIMS_TABLE[0]) -#define ROM_VIMSModeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ +#define rom_vims_set_mode \ + ((void (*)(uint32_t base, uint32_t mode)) \ ROM_API_VIMS_TABLE[1]) -#define ROM_VIMSModeGet \ - ((uint32_t (*)(uint32_t ui32Base)) \ +#define rom_vims_get_mode \ + ((uint32_t (*)(uint32_t base)) \ ROM_API_VIMS_TABLE[2]) -#define ROM_VIMSModeSafeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ +#define rom_vims_set_modesafe \ + ((void (*)(uint32_t base, uint32_t newmode, bool blocking)) \ ROM_API_VIMS_TABLE[3]) /* OSC FUNCTIONS */ -#define ROM_OSCClockSourceGet \ - ((uint32_t (*)(uint32_t ui32SrcClk)) \ +#define rom_osc_get_clocksource \ + ((uint32_t (*)(uint32_t srcclk)) \ ROM_API_OSC_TABLE[0]) -#define ROM_OSCClockSourceSet \ - ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ +#define rom_osc_set_clocksource \ + ((void (*)(uint32_t srcclk, uint32_t osc)) \ ROM_API_OSC_TABLE[1]) -#define ROM_OSC_HPOSCRelativeFrequencyOffsetGet \ - ((int32_t (*)(int32_t tempDegC)) \ +#define rom_hposc_get_relfrequencyoffset \ + ((int32_t (*)(int32_t tempdegC)) \ ROM_API_OSC_TABLE[2]) -#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ - ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ +#define rom_hposc_convert_relfrequencyoffset_to_rfcoreformat \ + ((int16_t (*)(int32_t hposc_relfreqoffset)) \ ROM_API_OSC_TABLE[3]) /* AUX_ADC FUNCTIONS */ -#define ROM_AUXADCAdjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ +#define rom_auxadc_adjust_gainoffset \ + ((int32_t (*)(int32_t adcvalue, int32_t gain, int32_t offset)) \ ROM_API_AUX_ADC_TABLE[0]) -#define ROM_AUXADCDisable \ +#define rom_auxadc_disable \ ((void (*)(void)) \ ROM_API_AUX_ADC_TABLE[1]) -#define ROM_AUXADCDisableInputScaling \ +#define rom_auxadc_disableInputScaling \ ((void (*)(void)) \ ROM_API_AUX_ADC_TABLE[2]) -#define ROM_AUXADCEnableAsync \ - ((void (*)(uint32_t refSource, uint32_t trigger)) \ +#define rom_auxadc_enable_async \ + ((void (*)(uint32_t refsource, uint32_t trigger)) \ ROM_API_AUX_ADC_TABLE[3]) -#define ROM_AUXADCEnableSync \ - ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \ +#define rom_auxadc_enable_sync \ + ((void (*)(uint32_t refsource, uint32_t sampletime, uint32_t trigger)) \ ROM_API_AUX_ADC_TABLE[4]) -#define ROM_AUXADCFlushFifo \ +#define rom_auxadc_flush_fifo \ ((void (*)(void)) \ ROM_API_AUX_ADC_TABLE[5]) -#define ROM_AUXADCGetAdjustmentGain \ - ((int32_t (*)(uint32_t refSource)) \ +#define rom_auxadc_get_adjustmentgain \ + ((int32_t (*)(uint32_t refsource)) \ ROM_API_AUX_ADC_TABLE[6]) -#define ROM_AUXADCGetAdjustmentOffset \ - ((int32_t (*)(uint32_t refSource)) \ +#define rom_auxadc_get_adjustoffset \ + ((int32_t (*)(uint32_t refsource)) \ ROM_API_AUX_ADC_TABLE[7]) -#define ROM_AUXADCMicrovoltsToValue \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \ +#define rom_auxadc_microvolts_to_value \ + ((int32_t (*)(int32_t fixedrefvoltage, int32_t microvolts)) \ ROM_API_AUX_ADC_TABLE[8]) -#define ROM_AUXADCPopFifo \ +#define rom_auxadc_pop_fifo \ ((uint32_t (*)(void)) \ ROM_API_AUX_ADC_TABLE[9]) -#define ROM_AUXADCReadFifo \ +#define rom_auxadc_read_fifo \ ((uint32_t (*)(void)) \ ROM_API_AUX_ADC_TABLE[10]) -#define ROM_AUXADCUnadjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ +#define rom_auxadc_unadjust_gainoffset \ + ((int32_t (*)(int32_t adcvalue, int32_t gain, int32_t offset)) \ ROM_API_AUX_ADC_TABLE[11]) -#define ROM_AUXADCValueToMicrovolts \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \ +#define rom_auxadc_value_to_microvolts \ + ((int32_t (*)(int32_t fixedrefvoltage, int32_t adcvalue)) \ ROM_API_AUX_ADC_TABLE[12]) /* SYS_CTRL FUNCTIONS */ -#define ROM_SysCtrlResetSourceGet \ +#define rom_sysctrl_get_resetsource \ ((uint32_t (*)(void)) \ ROM_API_SYS_CTRL_TABLE[0]) -#define ROM_SysCtrl_DCDC_VoltageConditionalControl \ +#define rom_sysctrl_dcdc_voltagecondcontrol \ ((void (*)(void)) \ ROM_API_SYS_CTRL_TABLE[1]) /* AON_BATMON FUNCTIONS */ -#define ROM_AONBatMonTemperatureGetDegC \ +#define rom_aonbatmaon_get_temperatureC \ ((int32_t (*)(void)) \ ROM_API_AON_BATMON_TABLE[0]) /* SETUP_ROM FUNCTIONS */ -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_coldreset_from_shutdown_cfg1 \ + ((void (*)(uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[0]) -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ - ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_coldreset_from_shutdown_cfg2 \ + ((void (*)(uint32_t fcfg1_revision, uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[1]) -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_coldreset_from_shutdown_cfg3 \ + ((void (*)(uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[2]) -#define ROM_SetupGetTrimForAdcShModeEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_adcshmodeen \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[3]) -#define ROM_SetupGetTrimForAdcShVbufEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_adcshvbufen \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[4]) -#define ROM_SetupGetTrimForAmpcompCtrl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_ampcompctrl \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[5]) -#define ROM_SetupGetTrimForAmpcompTh1 \ +#define rom_setup_get_trim_ampcompth1 \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[6]) -#define ROM_SetupGetTrimForAmpcompTh2 \ +#define rom_setup_get_trim_ampcompth2 \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[7]) -#define ROM_SetupGetTrimForAnabypassValue1 \ - ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \ +#define rom_setup_get_trim_anabypass_value1 \ + ((uint32_t (*)(uint32_t ccfg_modeconf)) \ ROM_API_SETUP_ROM_TABLE[8]) -#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_dblrloopfilter_resetvoltage \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[9]) -#define ROM_SetupGetTrimForRadcExtCfg \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_radc_extcfg \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[10]) -#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_rcosc_lfibiastrim \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[11]) -#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \ +#define rom_setup_get_trim_rcosc_lfrtunectuntrim \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[12]) -#define ROM_SetupGetTrimForXoscHfCtl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_xosc_hfctrl \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[13]) -#define ROM_SetupGetTrimForXoscHfFastStart \ +#define rom_setup_get_trim_xosc_hffaststart \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[14]) -#define ROM_SetupGetTrimForXoscHfIbiastherm \ +#define rom_setup_get_trim_xosc_hfibiastherm \ ((uint32_t (*)(void)) \ ROM_API_SETUP_ROM_TABLE[15]) -#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ +#define rom_setup_get_trim_lfregulator_cmirrwr_ratio \ + ((uint32_t (*)(uint32_t fcfg1_revision)) \ ROM_API_SETUP_ROM_TABLE[16]) -#define ROM_SetupSetAonRtcSubSecInc \ - ((void (*)(uint32_t subSecInc)) \ +#define rom_setup_aonrtc_subsecinc \ + ((void (*)(uint32_t subsecinc)) \ ROM_API_SETUP_ROM_TABLE[17]) -#define ROM_SetupSetCacheModeAccordingToCcfgSetting \ +#define rom_setup_cachemode \ ((void (*)(void)) \ ROM_API_SETUP_ROM_TABLE[18]) -#define ROM_SetupStepVddrTrimTo \ - ((void (*)(uint32_t toCode)) \ +#define rom_setup_stepvaddrtrimto \ + ((void (*)(uint32_t tocode)) \ ROM_API_SETUP_ROM_TABLE[19]) /* I2S FUNCTIONS */ -#define ROM_I2SPointerSet \ - ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \ +#define rom_i2s_set_pointer \ + ((void (*)(uint32_t base, bool input, void *nextpointer)) \ ROM_API_I2S_TABLE[0]) -#define ROM_I2SSampleStampGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \ +#define rom_i2s_get_samplestamp \ + ((uint32_t (*)(uint32_t base, uint32_t channel)) \ ROM_API_I2S_TABLE[1]) /* PWR_CTRL FUNCTIONS */ -#define ROM_PowerCtrlSourceSet \ - ((void (*)(uint32_t ui32PowerConfig)) \ +#define rom_powerctrl_set_source \ + ((void (*)(uint32_t powerconfig)) \ ROM_API_PWR_CTRL_TABLE[0]) /* AES FUNCTIONS */ -#define ROM_AESConfigureCCMCtrl \ - ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \ +#define rom_aes_configure_ccmctrl \ + ((void (*)(uint32_t noncelen, uint32_t maclen, bool encrypt)) \ ROM_API_AES_TABLE[0]) -#define ROM_AESReadFromKeyStore \ - ((uint32_t (*)(uint32_t keyStoreArea)) \ +#define rom_aes_read_keystore \ + ((uint32_t (*)(uint32_t keystorearea)) \ ROM_API_AES_TABLE[1]) -#define ROM_AESReadTag \ - ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \ +#define rom_aes_read_tag \ + ((uint32_t (*)(uint8_t *tag, uint32_t taglen)) \ ROM_API_AES_TABLE[2]) -#define ROM_AESSetInitializationVector \ - ((void (*)(const uint32_t *initializationVector)) \ +#define rom_aes_initialize_vector \ + ((void (*)(const uint32_t *initialize_vector)) \ ROM_API_AES_TABLE[3]) -#define ROM_AESStartDMAOperation \ - ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ +#define rom_aes_start_dmaoperation \ + ((void (*)(const uint8_t *channel0Addr, uint32_t chan0len, \ + uint8_t *chan1addr, uint32_t chan1len)) \ ROM_API_AES_TABLE[4]) -#define ROM_AESVerifyTag \ - ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \ +#define rom_aes_verify_tag \ + ((uint32_t (*)(const uint8_t *tag, uint32_t taglen)) \ ROM_API_AES_TABLE[5]) -#define ROM_AESWaitForIRQFlags \ +#define rom_aes_wait_irqflags \ ((uint32_t (*)(uint32_t irqFlags)) \ ROM_API_AES_TABLE[6]) -#define ROM_AESWriteCCMInitializationVector \ - ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \ +#define rom_aes_write_ccminitvector \ + ((void (*)(const uint8_t *nonce, uint32_t noncelen)) \ ROM_API_AES_TABLE[7]) -#define ROM_AESWriteToKeyStore \ - ((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \ +#define rom_aes_write_keystore \ + ((uint32_t (*)(const uint8_t *aeskey, uint32_t aesKeyLength, uint32_t keystorearea)) \ ROM_API_AES_TABLE[8]) /* PKA FUNCTIONS */ -#define ROM_PKABigNumAddGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ +#define rom_pka_get_bignumadd \ + ((uint32_t (*)(uint8_t *result, uint32_t *resultlen, uint32_t pka_memaddr)) \ ROM_API_PKA_TABLE[0]) -#define ROM_PKABigNumCmpGetResult \ +#define rom_pka_get_bignumcmp \ ((uint32_t (*)(void)) \ ROM_API_PKA_TABLE[1]) -#define ROM_PKABigNumInvModGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ +#define rom_pka_get_bignuminvmod \ + ((uint32_t (*)(uint8_t *result, uint32_t length, uint32_t pka_memaddr)) \ ROM_API_PKA_TABLE[2]) -#define ROM_PKABigNumModGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ +#define rom_pka_get_bignummod \ + ((uint32_t (*)(uint8_t *result, uint32_t length, uint32_t pka_memaddr)) \ ROM_API_PKA_TABLE[3]) -#define ROM_PKABigNumMultGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ +#define rom_pka_get_bignummult \ + ((uint32_t (*)(uint8_t *result, uint32_t *resultlen, uint32_t pka_memaddr)) \ ROM_API_PKA_TABLE[4]) -#define ROM_PKAEccAddGetResult \ - ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ +#define rom_pka_get_eccadd \ + ((uint32_t (*)(uint8_t *curvepointX, uint8_t *curvepointY, uint32_t pka_memaddr, \ + uint32_t length)) \ ROM_API_PKA_TABLE[5]) -#define ROM_PKAEccAddStart \ - ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_get_eccstart \ + ((uint32_t (*)(const uint8_t *curvepoint1X, const uint8_t *curvepoint1Y, \ + const uint8_t *curvepoint2X, const uint8_t *curvepoint2Y, \ + const uint8_t *prime, const uint8_t *a, uint32_t length, \ + uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[6]) -#define ROM_PKAEccMultiplyGetResult \ - ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ +#define rom_pka_get_eccmultiply \ + ((uint32_t (*)(uint8_t *curvepointX, uint8_t *curvepointY, uint32_t pka_memaddr, \ + uint32_t length)) \ ROM_API_PKA_TABLE[7]) -#define ROM_PKAEccMultiplyStart \ - ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_get_eecmultiplystart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvepointX, \ + const uint8_t *curvepointY, const uint8_t *prime, \ + const uint8_t *a, const uint8_t *b, uint32_t length, \ + uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[8]) -#define ROM_PKAGetOpsStatus \ +#define rom_pka_opsstatus \ ((uint32_t (*)(void)) \ ROM_API_PKA_TABLE[9]) -#define ROM_PKABigNumAddStart \ - ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_start_bignumadd \ + ((uint32_t (*)(const uint8_t *bignum1, uint32_t bignum1len, const uint8_t *bignum2, \ + uint32_t bignum2len, uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[10]) -#define ROM_PKABigNumCmpStart \ - ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ +#define rom_pka_start_bignumcmp \ + ((uint32_t (*)(const uint8_t *bignum1, const uint8_t *bignum2, uint32_t length)) \ ROM_API_PKA_TABLE[11]) -#define ROM_PKABigNumInvModStart \ - ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_start_bignuminvmod \ + ((uint32_t (*)(const uint8_t *bignum, uint32_t bignumlen, const uint8_t *modulus, \ + uint32_t moduluslen, uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[12]) -#define ROM_PKABigNumModStart \ - ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_start_bignummod \ + ((uint32_t (*)(const uint8_t *bignum, uint32_t bignumlen, const uint8_t *modulus, \ + uint32_t moduluslen, uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[13]) -#define ROM_PKABigNumMultiplyStart \ - ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_start_bignummult \ + ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandlen, \ + const uint8_t *multiplier, uint32_t multiplierlen, \ + uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[14]) -#define ROM_PKABigNumSubGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ +#define rom_pka_get_bignumsub \ + ((uint32_t (*)(uint8_t *result, uint32_t *resultlen, uint32_t pka_memaddr)) \ ROM_API_PKA_TABLE[15]) -#define ROM_PKABigNumSubStart \ - ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_start_bignumsub \ + ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendlen, \ + const uint8_t *subtrahend, uint32_t subtrahendlen, \ + uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[16]) -#define ROM_PKAArrayAllZeros \ - ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \ +#define rom_pka_zero_array \ + ((bool (*)(const uint8_t *array, uint32_t arraylen)) \ ROM_API_PKA_TABLE[17]) -#define ROM_PKABigNumDivideGetQuotient \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \ +#define rom_pka_get_bignumquotient \ + ((uint32_t (*)(uint8_t *result, uint32_t *length, uint32_t quotient_memaddr)) \ ROM_API_PKA_TABLE[18]) -#define ROM_PKABigNumDivideGetRemainder \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \ +#define rom_pka_get_bignumremainder \ + ((uint32_t (*)(uint8_t *result, uint32_t *length, uint32_t remainder_memaddr)) \ ROM_API_PKA_TABLE[19]) -#define ROM_PKABigNumDivideStart \ - ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ +#define rom_pka_start_bignumdiv \ + ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendlen, \ + const uint8_t *divisor, uint32_t divisorlen, \ + uint32_t *quotient_memaddr, uint32_t *remainder_memaddr)) \ ROM_API_PKA_TABLE[20]) -#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ - ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ +#define rom_pka_start_verifypublickey_weierstrass \ + ((uint32_t (*)(const uint8_t *curvepointX, const uint8_t *curvepointY, \ + const uint8_t *prime, const uint8_t *a, const uint8_t *b, \ + const uint8_t *order, uint32_t length)) \ ROM_API_PKA_TABLE[21]) -#define ROM_PKAZeroOutArray \ - ((void (*)(const uint8_t *array, uint32_t arrayLength)) \ +#define rom_pka_zero_outarry \ + ((void (*)(const uint8_t *array, uint32_t arraylen)) \ ROM_API_PKA_TABLE[22]) -#define ROM_PKAEccMontgomeryMultiplyStart \ - ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ +#define rom_pka_start_montgomerymult \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvepointX, \ + const uint8_t *prime, const uint8_t *a, uint32_t length, \ + uint32_t *pka_memaddr)) \ ROM_API_PKA_TABLE[23]) /* SHA2 FUNCTIONS */ -#define ROM_SHA2ComputeFinalHash \ - ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ +#define rom_sha1_compute_finalhash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *result_digest, \ + uint32_t *intermediate_digest, uint32_t total_msglen, \ + uint32_t messageLength, uint32_t hashalgorithm)) \ ROM_API_SHA2_TABLE[0]) -#define ROM_SHA2ComputeHash \ - ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ +#define rom_sha1_compute_hash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *result_digest, \ + uint32_t total_msglen, uint32_t hashalgorithm)) \ ROM_API_SHA2_TABLE[1]) -#define ROM_SHA2ComputeInitialHash \ - ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ +#define rom_sha1_compute_initialhash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediate_digest, \ + uint32_t hashalgorithm, uint32_t initial_msglen)) \ ROM_API_SHA2_TABLE[2]) -#define ROM_SHA2ComputeIntermediateHash \ - ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ +#define rom_sha1_compute_intermediatehash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediate_digest, \ + uint32_t hashalgorithm, uint32_t intermediate_msglen)) \ ROM_API_SHA2_TABLE[3]) -#define ROM_SHA2StartDMAOperation \ - ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ +#define rom_sha1_start_dmaoperation \ + ((void (*)(uint8_t *channel0Addr, uint32_t chan0len, uint8_t *chan1addr, \ + uint32_t chan1len)) \ ROM_API_SHA2_TABLE[4]) -#define ROM_SHA2WaitForIRQFlags \ +#define rom_sha1_wait_irqflags \ ((uint32_t (*)(uint32_t irqFlags)) \ ROM_API_SHA2_TABLE[5]) @@ -1014,4 +1047,37 @@ struct hard_api_s typedef struct hard_api_s hard_api_t; +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rom_signextend_vddrtrim + * + * Description: + * Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) + * + * Input Parameters + * vddrtrim - VDDR_TRIM setting + * + * Returned Value: + * Returns sign extended VDDR_TRIM setting. + * + ************************************************************************************/ + +static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) +{ + /* The VDDR trim value is 5 bits representing the range from -10 to +21 + * (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + */ + + int32_t signed_vaddrtrim = vddrtrim; + if (signed_vaddrtrim > 0x15) + { + signed_vaddrtrim -= 0x20; + } + + return signed_vaddrtrim; +} + #endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V2_ROM_H */ diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c index 97882cf756b..6f84b2be966 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c +++ b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c @@ -261,13 +261,13 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * the VDDR_TRIM_SLEEP value. -Configure DCDC. */ - SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg1(ccfg_modeconf); /* Second part of trim done after cold reset and wakeup from shutdown: * -Configure XOSC. */ - SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision, + rom_setup_coldreset_from_shutdown_cfg2(fcfg1_revision, ccfg_modeconf); /* Special shadow register trim propagation on first batch of devices */ @@ -345,7 +345,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) /* The VDDS_BOD trim and the VDDR trim is already stepped up to max/HH if * "CC1352 boost mode" is requested. See function - * SetupAfterColdResetWakeupFromShutDownCfg1() in setup_rom.c for details. + * rom_setup_coldreset_from_shutdown_cfg1() in setup_rom.c for details. */ if (((ccfg_modeconf & CCFG_MODE_CONF_VDDR_EXT_LOAD) != 0) || @@ -390,7 +390,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) regval8 |= ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; putreg8(regval8, TIVA_ADI3_REFSYS_REFSYSCTL3); - SetupStepVddrTrimTo((fusedata & + rom_setup_stepvaddrtrimto((fusedata & FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_MASK) >> FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_SHIFT); } @@ -458,7 +458,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * -Configure HPOSC. -Setup the LF clock. */ - SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg3(ccfg_modeconf); /* Set AUX into power down active mode */ @@ -531,7 +531,7 @@ void cc13xx_trim_device(void) /* Select correct CACHE mode and set correct CACHE configuration */ - SetupSetCacheModeAccordingToCcfgSetting(); + rom_setup_cachemode(); /* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none * of the above. It is always assumed that the application will freeze the diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c index 45b74904495..eb83958097e 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c +++ b/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c @@ -141,13 +141,13 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * the VDDR_TRIM_SLEEP value. -Configure DCDC. */ - SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg1(ccfg_modeconf); /* Second part of trim done after cold reset and wakeup from shutdown: * -Configure XOSC. */ - SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision, + rom_setup_coldreset_from_shutdown_cfg2(fcfg1_revision, ccfg_modeconf); { @@ -202,7 +202,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * -Configure HPOSC. -Setup the LF clock. */ - SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf); + rom_setup_coldreset_from_shutdown_cfg3(ccfg_modeconf); /* Set AUX into power down active mode */ @@ -277,7 +277,7 @@ void cc13xx_trim_device(void) /* Select correct CACHE mode and set correct CACHE configuration */ - SetupSetCacheModeAccordingToCcfgSetting(); + rom_setup_cachemode(); /* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none * of the above. It is always assumed that the application will freeze the diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_prcm.h b/arch/arm/src/tiva/cc13xx/cc13xx_prcm.h index 7823fe1f0f9..6cd5d744139 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_prcm.h +++ b/arch/arm/src/tiva/cc13xx/cc13xx_prcm.h @@ -81,7 +81,7 @@ * domain. */ #define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \ - 0x00020010 /* For function PRCMPowerDomainOff() + 0x00020010 /* For function rom_prcm_powerdomain_off() * it is an option to select that * VIMS power domain shall not * power up during the next wake diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h new file mode 100644 index 00000000000..cab60d4cd3e --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h @@ -0,0 +1,181 @@ +/******************************************************************************************************************** + * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H + +/******************************************************************************************************************** + * Included Files + ********************************************************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/******************************************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************************************/ + +/* AON BATMON Register Offsets **************************************************************************************/ + +#define TIVA_AON_BATMON_CTL_OFFSET 0x0000 +#define TIVA_AON_BATMON_MEASCFG_OFFSET 0x0004 +#define TIVA_AON_BATMON_TEMPP0_OFFSET 0x000c +#define TIVA_AON_BATMON_TEMPP1_OFFSET 0x0010 +#define TIVA_AON_BATMON_TEMPP2_OFFSET 0x0014 +#define TIVA_AON_BATMON_BATMONP0_OFFSET 0x0018 +#define TIVA_AON_BATMON_BATMONP1_OFFSET 0x001c +#define TIVA_AON_BATMON_IOSTRP0_OFFSET 0x0020 +#define TIVA_AON_BATMON_FLASHPUMPP0_OFFSET 0x0024 +#define TIVA_AON_BATMON_BAT_OFFSET 0x0028 /* Last Measured Battery Voltage */ +#define TIVA_AON_BATMON_BATUPD_OFFSET 0x002c /* Battery Update */ +#define TIVA_AON_BATMON_TEMP_OFFSET 0x0030 /* Temperature */ +#define TIVA_AON_BATMON_TEMPUPD_OFFSET 0x0034 /* Temperature Update */ + +/* AON BATMON Register Addresses ************************************************************************************/ + +#define TIVA_AON_BATMON_CTL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_CTL_OFFSET) +#define TIVA_AON_BATMON_MEASCFG (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_MEASCFG_OFFSET) +#define TIVA_AON_BATMON_TEMPP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPP0_OFFSET) +#define TIVA_AON_BATMON_TEMPP1 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPP1_OFFSET) +#define TIVA_AON_BATMON_TEMPP2 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPP2_OFFSET) +#define TIVA_AON_BATMON_BATMONP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATMONP0_OFFSET) +#define TIVA_AON_BATMON_BATMONP1 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATMONP1_OFFSET) +#define TIVA_AON_BATMON_IOSTRP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_IOSTRP0_OFFSET) +#define TIVA_AON_BATMON_FLASHPUMPP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_FLASHPUMPP0_OFFSET) +#define TIVA_AON_BATMON_BAT (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BAT_OFFSET) +#define TIVA_AON_BATMON_BATUPD (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATUPD_OFFSET) +#define TIVA_AON_BATMON_TEMP (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMP_OFFSET) +#define TIVA_AON_BATMON_TEMPUPD (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUPD_OFFSET) + +/* AON BATMON Register Bitfield Definitions *************************************************************************/ + +/* AON_BATMON_CTL */ + +#define AON_BATMON_CTL_MEAS_EN (1 << 0) /* Bit 0 */ +#define AON_BATMON_CTL_CALC_EN (1 << 1) /* Bit 1 */ + +/* AON_BATMON_MEASCFG */ + +#define AON_BATMON_MEASCFG_PER_SHIFT (0) /* Bits 0-1 */ +#define AON_BATMON_MEASCFG_PER_MASK (3 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER(n) ((uint32_t)(n) << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_CONT (0 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_8CYC (1 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_16CYC (2 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_32CYC (3 << AON_BATMON_MEASCFG_PER_SHIFT) + +/* AON_BATMON_TEMPP0 */ + +#define AON_BATMON_TEMPP0_CFG_SHIFT (0) /* Bits 0-7 */ +#define AON_BATMON_TEMPP0_CFG_MASK (0xff << AON_BATMON_TEMPP0_CFG_SHIFT) +# define AON_BATMON_TEMPP0_CFG(n) ((uint32_t)(n) << AON_BATMON_TEMPP0_CFG_SHIFT) + +/* AON_BATMON_TEMPP1 */ + +#define AON_BATMON_TEMPP1_CFG_SHIFT (0) /* Bits 0-5 */ +#define AON_BATMON_TEMPP1_CFG_MASK (0x3f << AON_BATMON_TEMPP1_CFG_SHIFT) +# define AON_BATMON_TEMPP1_CFG(n) ((uint32_t)(n) << AON_BATMON_TEMPP1_CFG_SHIFT) + +/* AON_BATMON_TEMPP2 */ + +#define AON_BATMON_TEMPP2_CFG_SHIFT (0) /* Bits 0-4 */ +#define AON_BATMON_TEMPP2_CFG_MASK (0x2f << AON_BATMON_TEMPP2_CFG_SHIFT) +# define AON_BATMON_TEMPP2_CFG(n) ((uint32_t)(n) << AON_BATMON_TEMPP2_CFG_SHIFT) + +/* AON_BATMON_BATMONP0 */ + +#define AON_BATMON_BATMONP0_CFG_SHIFT (0) /* Bits 0-5 */ +#define AON_BATMON_BATMONP0_CFG_MASK (0x2f << AON_BATMON_BATMONP0_CFG_SHIFT) +# define AON_BATMON_BATMONP0_CFG(n) ((uint32_t)(n) << AON_BATMON_BATMONP0_CFG_SHIFT) + +/* AON_BATMON_BATMONP1 */ + +#define AON_BATMON_BATMONP1_CFG_SHIFT (0) /* Bits 0-5 */ +#define AON_BATMON_BATMONP1_CFG_MASK (0x3f << AON_BATMON_BATMONP1_CFG_SHIFT) +# define AON_BATMON_BATMONP1_CFG(n) ((uint32_t)(n) << AON_BATMON_BATMONP1_CFG_SHIFT) + +/* AON_BATMON_IOSTRP0 */ + +#define AON_BATMON_IOSTRP0_CFG1_SHIFT (0) /* Bits 0-3 */ +#define AON_BATMON_IOSTRP0_CFG1_MASK (15 << AON_BATMON_IOSTRP0_CFG1_SHIFT) +# define AON_BATMON_IOSTRP0_CFG1(n) ((uint32_t)(n) << AON_BATMON_IOSTRP0_CFG1_SHIFT) +#define AON_BATMON_IOSTRP0_CFG2_SHIFT (4) /* Bits 4-6 */ +#define AON_BATMON_IOSTRP0_CFG2_MASK (3 << AON_BATMON_IOSTRP0_CFG2_SHIFT) +# define AON_BATMON_IOSTRP0_CFG2(n) ((uint32_t)(n) << AON_BATMON_IOSTRP0_CFG2_SHIFT) + +/* AON_BATMON_FLASHPUMPP0 */ + +#define AON_BATMON_FLASHPUMPP0_CFG_SHIFT (0) /* Bits 0-3 */ +#define AON_BATMON_FLASHPUMPP0_CFG_MASK (15 << AON_BATMON_FLASHPUMPP0_CFG_SHIFT) +# define AON_BATMON_FLASHPUMPP0_CFG(n) ((uint32_t)(n) << AON_BATMON_FLASHPUMPP0_CFG_SHIFT) +#define AON_BATMON_FLASHPUMPP0_OVR (1 << 4) /* Bit 4 */ +#define AON_BATMON_FLASHPUMPP0_LOWLIM (1 << 5) /* Bit 5 */ +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_SHIFT (6) /* Bits 6-7 */ +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_MASK (3 << AON_BATMON_FLASHPUMPP0_HIGHLIM_SHIFT) +# define AON_BATMON_FLASHPUMPP0_HIGHLIM(n) ((uint32_t)(n) << AON_BATMON_FLASHPUMPP0_HIGHLIM_SHIFT) +#define AON_BATMON_FLASHPUMPP0_FALLB (1 << 8) /* Bit 8 */ + +/* AON_BATMON_BAT */ + +#define AON_BATMON_BAT_FRAC_SHIFT (0) /* Bits 0-7: Fractional part */ +#define AON_BATMON_BAT_FRAC_MASK (0xff << AON_BATMON_BAT_FRAC_SHIFT) +# define AON_BATMON_BAT_FRAC(n) ((uint32_t)(n) << AON_BATMON_BAT_FRAC_SHIFT) +#define AON_BATMON_BAT_INT_SHIFT (8) /* Bits 8-10: Integer part */ +#define AON_BATMON_BAT_INT_MASK (7 << AON_BATMON_BAT_INT_SHIFT) +# define AON_BATMON_BAT_INT(n) ((uint32_t)(n) << AON_BATMON_BAT_INT_SHIFT) + +/* AON_BATMON_BATUPD */ + +#define AON_BATMON_BATUPD_STAT (1 << 0) /* Bit 0: New battery voltage is present */ + +/* AON_BATMON_TEMP */ + +#define AON_BATMON_TEMP_INT_SHIFT (8) /* Bits 8-16: Signed integer part of temperature */ +#define AON_BATMON_TEMP_INT_MASK (0x1ff << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT(n) ((uint32_t)(n) << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT_MIN (0x100 << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT_MAX (0x0ff << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT_ZERO (0x000 << AON_BATMON_TEMP_INT_SHIFT) + +/* AON_BATMON_TEMPUPD */ + +#define AON_BATMON_TEMPUPD_STAT (1 << 0) /* Bit 0: New temperature is present */ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h new file mode 100644 index 00000000000..69c8da34b6a --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h @@ -0,0 +1,265 @@ +/******************************************************************************************************************** + * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H + +/******************************************************************************************************************** + * Included Files + ********************************************************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/******************************************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************************************/ + +/* AON BATMON Register Offsets **************************************************************************************/ + +#define TIVA_AON_BATMON_CTL_OFFSET 0x0000 +#define TIVA_AON_BATMON_MEASCFG_OFFSET 0x0004 +#define TIVA_AON_BATMON_TEMPP0_OFFSET 0x000c +#define TIVA_AON_BATMON_TEMPP1_OFFSET 0x0010 +#define TIVA_AON_BATMON_TEMPP2_OFFSET 0x0014 +#define TIVA_AON_BATMON_BATMONP0_OFFSET 0x0018 +#define TIVA_AON_BATMON_BATMONP1_OFFSET 0x001c +#define TIVA_AON_BATMON_IOSTRP0_OFFSET 0x0020 +#define TIVA_AON_BATMON_FLASHPUMPP0_OFFSET 0x0024 +#define TIVA_AON_BATMON_BAT_OFFSET 0x0028 /* Last Measured Battery Voltage */ +#define TIVA_AON_BATMON_BATUPD_OFFSET 0x002c /* Battery Update */ +#define TIVA_AON_BATMON_TEMP_OFFSET 0x0030 /* Temperature */ +#define TIVA_AON_BATMON_TEMPUPD_OFFSET 0x0034 /* Temperature Update */ +#define TIVA_AON_BATMON_EVENTMASK_OFFSET 0x0048 /* Event Mask */ +#define TIVA_AON_BATMON_EVENT_OFFSET 0x004c /* Event */ +#define TIVA_AON_BATMON_BATUL_OFFSETT 0x0050 /* Battery Upper Limit */ +#define TIVA_AON_BATMON_BATLL_OFFSETT 0x0054 /* Battery Lower Limit */ +#define TIVA_AON_BATMON_TEMPUL_OFFSET 0x0058 /* Temperature Upper Limit */ +#define TIVA_AON_BATMON_TEMPLL_OFFSET 0x005c /* Temperature Lower Limit */ + +/* AON BATMON Register Addresses ************************************************************************************/ + +#define TIVA_AON_BATMON_CTL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_CTL_OFFSET) +#define TIVA_AON_BATMON_MEASCFG (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_MEASCFG_OFFSET) +#define TIVA_AON_BATMON_TEMPP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPP0_OFFSET) +#define TIVA_AON_BATMON_TEMPP1 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPP1_OFFSET) +#define TIVA_AON_BATMON_TEMPP2 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPP2_OFFSET) +#define TIVA_AON_BATMON_BATMONP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATMONP0_OFFSET) +#define TIVA_AON_BATMON_BATMONP1 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATMONP1_OFFSET) +#define TIVA_AON_BATMON_IOSTRP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_IOSTRP0_OFFSET) +#define TIVA_AON_BATMON_FLASHPUMPP0 (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_FLASHPUMPP0_OFFSET) +#define TIVA_AON_BATMON_BAT (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BAT_OFFSET) +#define TIVA_AON_BATMON_BATUPD (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATUPD_OFFSET) +#define TIVA_AON_BATMON_TEMP (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMP_OFFSET) +#define TIVA_AON_BATMON_TEMPUPD (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUPD_OFFSET) +#define TIVA_AON_BATMON_EVENTMASK (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_EVENTMASK_OFFSET) +#define TIVA_AON_BATMON_EVENT (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_EVENT_OFFSET) +#define TIVA_AON_BATMON_BATUL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATUL_OFFSETT) +#define TIVA_AON_BATMON_BATLL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_BATLL_OFFSETT) +#define TIVA_AON_BATMON_TEMPUL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUL_OFFSET) +#define TIVA_AON_BATMON_TEMPLL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPLL_OFFSET) + +/* AON BATMON Register Bitfield Definitions *************************************************************************/ + +/* AON_BATMON_CTL */ + +#define AON_BATMON_CTL_MEAS_EN (1 << 0) /* Bit 0 */ +#define AON_BATMON_CTL_CALC_EN (1 << 1) /* Bit 1 */ + +/* AON_BATMON_MEASCFG */ + +#define AON_BATMON_MEASCFG_PER_SHIFT (0) /* Bits 0-1 */ +#define AON_BATMON_MEASCFG_PER_MASK (3 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER(n) ((uint32_t)(n) << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_CONT (0 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_8CYC (1 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_16CYC (2 << AON_BATMON_MEASCFG_PER_SHIFT) +# define AON_BATMON_MEASCFG_PER_32CYC (3 << AON_BATMON_MEASCFG_PER_SHIFT) + +/* AON_BATMON_TEMPP0 */ + +#define AON_BATMON_TEMPP0_CFG_SHIFT (0) /* Bits 0-7 */ +#define AON_BATMON_TEMPP0_CFG_MASK (0xff << AON_BATMON_TEMPP0_CFG_SHIFT) +# define AON_BATMON_TEMPP0_CFG(n) ((uint32_t)(n) << AON_BATMON_TEMPP0_CFG_SHIFT) + +/* AON_BATMON_TEMPP1 */ + +#define AON_BATMON_TEMPP1_CFG_SHIFT (0) /* Bits 0-5 */ +#define AON_BATMON_TEMPP1_CFG_MASK (0x3f << AON_BATMON_TEMPP1_CFG_SHIFT) +# define AON_BATMON_TEMPP1_CFG(n) ((uint32_t)(n) << AON_BATMON_TEMPP1_CFG_SHIFT) + +/* AON_BATMON_TEMPP2 */ + +#define AON_BATMON_TEMPP2_CFG_SHIFT (0) /* Bits 0-4 */ +#define AON_BATMON_TEMPP2_CFG_MASK (0x2f << AON_BATMON_TEMPP2_CFG_SHIFT) +# define AON_BATMON_TEMPP2_CFG(n) ((uint32_t)(n) << AON_BATMON_TEMPP2_CFG_SHIFT) + +/* AON_BATMON_BATMONP0 */ + +#define AON_BATMON_BATMONP0_CFG_SHIFT (0) /* Bits 0-6 */ +#define AON_BATMON_BATMONP0_CFG_MASK (0x7f << AON_BATMON_BATMONP0_CFG_SHIFT) +# define AON_BATMON_BATMONP0_CFG(n) ((uint32_t)(n) << AON_BATMON_BATMONP0_CFG_SHIFT) + +/* AON_BATMON_BATMONP1 */ + +#define AON_BATMON_BATMONP1_CFG_SHIFT (0) /* Bits 0-5 */ +#define AON_BATMON_BATMONP1_CFG_MASK (0x3f << AON_BATMON_BATMONP1_CFG_SHIFT) +# define AON_BATMON_BATMONP1_CFG(n) ((uint32_t)(n) << AON_BATMON_BATMONP1_CFG_SHIFT) + +/* AON_BATMON_IOSTRP0 */ + +#define AON_BATMON_IOSTRP0_CFG1_SHIFT (0) /* Bits 0-3 */ +#define AON_BATMON_IOSTRP0_CFG1_MASK (15 << AON_BATMON_IOSTRP0_CFG1_SHIFT) +# define AON_BATMON_IOSTRP0_CFG1(n) ((uint32_t)(n) << AON_BATMON_IOSTRP0_CFG1_SHIFT) +#define AON_BATMON_IOSTRP0_CFG2_SHIFT (4) /* Bits 4-6 */ +#define AON_BATMON_IOSTRP0_CFG2_MASK (3 << AON_BATMON_IOSTRP0_CFG2_SHIFT) +# define AON_BATMON_IOSTRP0_CFG2(n) ((uint32_t)(n) << AON_BATMON_IOSTRP0_CFG2_SHIFT) + +/* AON_BATMON_FLASHPUMPP0 */ + +#define AON_BATMON_FLASHPUMPP0_CFG_SHIFT (0) /* Bits 0-3 */ +#define AON_BATMON_FLASHPUMPP0_CFG_MASK (15 << AON_BATMON_FLASHPUMPP0_CFG_SHIFT) +# define AON_BATMON_FLASHPUMPP0_CFG(n) ((uint32_t)(n) << AON_BATMON_FLASHPUMPP0_CFG_SHIFT) +#define AON_BATMON_FLASHPUMPP0_OVR (1 << 4) /* Bit 4 */ +#define AON_BATMON_FLASHPUMPP0_LOWLIM (1 << 5) /* Bit 5 */ +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_SHIFT (6) /* Bits 6-7 */ +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_MASK (3 << AON_BATMON_FLASHPUMPP0_HIGHLIM_SHIFT) +# define AON_BATMON_FLASHPUMPP0_HIGHLIM(n) ((uint32_t)(n) << AON_BATMON_FLASHPUMPP0_HIGHLIM_SHIFT) +#define AON_BATMON_FLASHPUMPP0_FALLB (1 << 8) /* Bit 8 */ +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER (1 << 9) /* Bit 9 */ + +/* AON_BATMON_BAT */ + +#define AON_BATMON_BAT_FRAC_SHIFT (0) /* Bits 0-7: Fractional part */ +#define AON_BATMON_BAT_FRAC_MASK (0xff << AON_BATMON_BAT_FRAC_SHIFT) +# define AON_BATMON_BAT_FRAC(n) ((uint32_t)(n) << AON_BATMON_BAT_FRAC_SHIFT) +#define AON_BATMON_BAT_INT_SHIFT (8) /* Bits 8-10: Integer part */ +#define AON_BATMON_BAT_INT_MASK (7 << AON_BATMON_BAT_INT_SHIFT) +# define AON_BATMON_BAT_INT(n) ((uint32_t)(n) << AON_BATMON_BAT_INT_SHIFT) + +/* AON_BATMON_BATUPD */ + +#define AON_BATMON_BATUPD_STAT (1 << 0) /* Bit 0: New battery voltage is present */ + +/* AON_BATMON_TEMP */ + +#define AON_BATMON_TEMP_INT_SHIFT (8) /* Bits 8-16: Signed integer part of temperature */ +#define AON_BATMON_TEMP_INT_MASK (0x1ff << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT(n) ((uint32_t)(n) << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT_MIN (0x100 << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT_MAX (0x0ff << AON_BATMON_TEMP_INT_SHIFT) +# define AON_BATMON_TEMP_INT_ZERO (0x000 << AON_BATMON_TEMP_INT_SHIFT) + +/* AON_BATMON_TEMPUPD */ + +#define AON_BATMON_TEMPUPD_STAT (1 << 0) /* Bit 0: New temperature is present */ + +/* AON_BATMON_EVENTMASK */ + +#define AON_BATMON_EVENTMASK_BATT_OVER_UL (1 << 0) /* Bit 0: EVENT.BATT_OVER_UL does not + * contribute to combined event from + * BATMON */ +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL (1 << 1) /* Bit 1: EVENT.BATT_BELOW_LL does not + * contribute to combined event from + * BATMON */ +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL (1 << 2) /* Bit 2: EVENT.TEMP_OVER_UL does not + * contribute to combined event from + * BATMON */ +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL (1 << 3) /* Bit 3: EVENT.TEMP_BELOW_LL does not + * contribute to combined event from + * BATMON */ +#define AON_BATMON_EVENTMASK_BATT_UPDATE (1 << 4) /* Bit 4: EVENT.BATT_UPDATE does not + * contribute to combined event from + * BATMON */ +#define AON_BATMON_EVENTMASK_TEMP_UPDATE (1 << 5) /* Bit 5: EVENT.TEMP_UPDATE does not + * contribute to combined event from + * BATMON */ + +/* AON_BATMON_EVENT */ + +#define AON_BATMON_EVENT_BATT_OVER_UL (1 << 0) /* Bit 0: R: Batter level above upper limit + * W: Clears the flag */ +#define AON_BATMON_EVENT_BATT_BELOW_LL (1 << 1) /* Bit 1: Battery level below lower limit + * W: Clears the flag */ +#define AON_BATMON_EVENT_TEMP_OVER_UL (1 << 2) /* Bit 2: R: Temperature level above upper limit + * W: Clears the flag */ +#define AON_BATMON_EVENT_TEMP_BELOW_LL (1 << 3) /* Bit 3: R: Temperature level below lower limit + * W: Clears the flag */ +#define AON_BATMON_EVENT_BATT_UPDATE (1 << 4) /* Bit 4: Alias to BATUPD.STAT */ +#define AON_BATMON_EVENT_TEMP_UPDATE (1 << 5) /* Bit 5: Alias to TEMPUPD.STAT */ + +/* AON_BATMON_BATTUL */ + +#define AON_BATMON_BATTUL_FRAC_SHIFT (0) /* Bits 0-7: Fractional part */ +#define AON_BATMON_BATTUL_FRAC_MASK (0xff << AON_BATMON_BATTUL_FRAC_SHIFT) +# define AON_BATMON_BATTUL_FRAC(n) ((uint32_t)(n) << AON_BATMON_BATTUL_FRAC_SHIFT) +#define AON_BATMON_BATTUL_INT_SHIFT (8) /* Bits: 8-10: Integer part */ +#define AON_BATMON_BATTUL_INT_MASK (7 << AON_BATMON_BATTUL_INT_SHIFT) +# define AON_BATMON_BATTUL_INT(n) ((uint32_t)(n) << AON_BATMON_BATTUL_INT_SHIFT) + +/* AON_BATMON_BATTLL */ + +#define AON_BATMON_BATTLL_INT_SHIFT (8) /* Bits: 8-10: Integer part */ +#define AON_BATMON_BATTLL_INT_MASK (7 << AON_BATMON_BATTLL_INT_SHIFT) +# define AON_BATMON_BATTLL_INT(n) ((uint32_t)(n) << AON_BATMON_BATTLL_INT_SHIFT) + +/* AON_BATMON_TEMPUL */ + +#define AON_BATMON_TEMPUL_FRAC_SHIFT (6) /* Bits 6-7: Fractional part of + * temperature upper limit */ +#define AON_BATMON_TEMPUL_FRAC_MASK (3 << AON_BATMON_TEMPUL_FRAC_SHIFT) +# define AON_BATMON_TEMPUL_FRAC(n) ((uint32_t)(n) << AON_BATMON_TEMPUL_FRAC_SHIFT) +#define AON_BATMON_TEMPUL_INT_SHIFT (8) /* Bits 8-16: Signed integer part + * of tempature upper limit */ +#define AON_BATMON_TEMPUL_INT_MASK (0x1ff << AON_BATMON_TEMPUL_INT_SHIFT) +# define AON_BATMON_TEMPUL_INT(n) ((uint32_t)(n) << AON_BATMON_TEMPUL_INT_SHIFT) + +/* AON_BATMON_TEMPLL */ + +#define AON_BATMON_TEMPLL_FRAC_SHIFT (6) /* Bits 6-7: Fractional part of + * temperature lower limit */ +#define AON_BATMON_TEMPLL_FRAC_MASK (3 << AON_BATMON_TEMPLL_FRAC_SHIFT) +# define AON_BATMON_TEMPLL_FRAC(n) ((uint32_t)(n) << AON_BATMON_TEMPLL_FRAC_SHIFT) +#define AON_BATMON_TEMPLL_INT_SHIFT (8) /* Bits 8-16: Signed integer part + * of tempature lower limit */ +#define AON_BATMON_TEMPLL_INT_MASK (0x1ff << AON_BATMON_TEMPLL_INT_SHIFT) +# define AON_BATMON_TEMPLL_INT(n) ((uint32_t)(n) << AON_BATMON_TEMPLL_INT_SHIFT) + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_batmon.h b/arch/arm/src/tiva/hardware/tiva_aon_batmon.h new file mode 100644 index 00000000000..15368e90d2d --- /dev/null +++ b/arch/arm/src/tiva/hardware/tiva_aon_batmon.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * arch/arm/src/tiva/hardware/tiva_aon_batmon.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_BATMON_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_BATMON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ + +#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the AON BATMON block */ +#elif defined(CONFIG_ARCH_CHIP_CC13X0) +# include "hardware/cc13x0/cc13x0_aon_batmon.h" +#elif defined(CONFIG_ARCH_CHIP_CC13X2) +# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h" +#else +# error "Unsupported Tiva/Stellaris/SimpleLink AON BATMON" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_BATMON_H */ diff --git a/configs/Kconfig b/configs/Kconfig index 2aa562fdc08..c7853afe579 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -335,6 +335,16 @@ config ARCH_BOARD_KWIKSTIK_K40 Kinetis K40 Cortex-M4 MCU. This port uses the NXP/FreeScale KwikStik-K40 development board. +config ARCH_BOARD_LAUNCHXL_CC1310 + bool "TI LaunchXL-CC1310" + depends on ARCH_CHIP_CC1310 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + TI SimpleLink CC1310 LaunchPad Evaluation Kit (LAUNCHXL-CC1310) + featuring the SimpleLinkCC1310 chip. + config ARCH_BOARD_LAUNCHXL_CC1312R1 bool "TI LaunchXL-CC1312R1" depends on ARCH_CHIP_CC1312R1 @@ -1788,6 +1798,7 @@ config ARCH_BOARD default "imxrt1050-evk" if ARCH_BOARD_IMXRT1050_EVK default "imxrt1060-evk" if ARCH_BOARD_IMXRT1060_EVK default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40 + default "launchxl-cc1310" if ARCH_BOARD_LAUNCHXL_CC1310 default "launchxl-cc1312r1" if ARCH_BOARD_LAUNCHXL_CC1312R1 default "launchxl-tms57004" if ARCH_BOARD_LAUNCHXL_TMS57004 default "lc823450-xgevk" if ARCH_BOARD_LC823450_XGEVK @@ -2054,6 +2065,9 @@ endif if ARCH_BOARD_KWIKSTIK_K40 source "configs/kwikstik-k40/Kconfig" endif +if ARCH_BOARD_LAUNCHXL_CC1310 +source "configs/launchxl-cc1310/Kconfig" +endif if ARCH_BOARD_LAUNCHXL_CC1312R1 source "configs/launchxl-cc1312r1/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index 552ec3faebe..7eca2b488d4 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -196,7 +196,15 @@ configs/c5471evm NuttX runs on the ARM core and is built with a GNU arm-nuttx-elf toolchain*. This port is complete and verified. -config/clicker2-stm32 +configs launchxl_cc1310 + Port to the TI SimpleLink CC1310 LaunchPad Evaluation Kit (LAUNCHXL-CC1310) + featuring the SimpleLinkCC1310 chip. + +configs launchxl_cc1312r1 + Port to the TI SimpleLink CC1312R1 LaunchPad Evaluation Kit (LAUNCHXL-CC1312R1) + featuring the SimpleLinkCC1312R1 chip. + +configs/clicker2-stm32 Mikroe Clicker2 STM32 board based on the STMicro STM32F407VGT6 MCU. configs/cloudctrl diff --git a/configs/launchxl-cc1310/Kconfig b/configs/launchxl-cc1310/Kconfig new file mode 100644 index 00000000000..33ed8b534b7 --- /dev/null +++ b/configs/launchxl-cc1310/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_LAUNCH_CC1310 + +endif # ARCH_BOARD_LAUNCH_CC1310 diff --git a/configs/launchxl-cc1310/README.txt b/configs/launchxl-cc1310/README.txt new file mode 100644 index 00000000000..5a2f127bbf0 --- /dev/null +++ b/configs/launchxl-cc1310/README.txt @@ -0,0 +1,35 @@ +README +====== + + This directory holds NuttX board support for the TI LaunchXL-CC1310. + +Contents +======== + + o Status + o Serial Console + o LEDs and Buttons + +Status +====== + + 2019-12-03: Fragmentary board support in place. The initial intent + of this board support is simply to assist in the CC13xx architecture + development. Serious board development will occur later. + +Serial Console +============== + + The on-board XDS110 Debugger provide a USB virtual serial console using + UART0 (PA0/U0RX and PA1/U0TX). + +LEDs and Buttons +================ + +LEDs +---- + + +Buttons +------- + diff --git a/configs/launchxl-cc1310/include/board.h b/configs/launchxl-cc1310/include/board.h new file mode 100644 index 00000000000..48fc74133b5 --- /dev/null +++ b/configs/launchxl-cc1310/include/board.h @@ -0,0 +1,138 @@ +/**************************************************************************** + * configs/launchxl-cc1310/include/board.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIG_LAUNCH_CC1310_INCLUDE_BOARD_H +#define __CONFIG_LAUNCH_CC1310_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Frequency of the ARM core clock */ + +#define SYSCLK_FREQUENCY 48000000 + +/* Peripheral Clock (PCLK) + * + * Same frequency as the SYSCLK + */ + +#define PCLK_FREQUENCY SYSCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The LaunchXL-cc1310 and two LEDs controlled by software: DIO7_GLED (CR1) + * and DIO6_RLED (CR2). A high output value illuminates an LED. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_GLED 0 +#define BOARD_RLED 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_GLED_BIT (1 << BOARD_GLED) +#define BOARD_RLED_BIT (1 << BOARD_RLED) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/cc1310_autoleds.c. The LEDs are used to + * encode OS-related events as follows: + * + * ------------------- ---------------------------- ---- ---- + * SYMBOL Meaning GLED RLED + * ------------------- ---------------------------- ---- ---- */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON */ +#define LED_IRQSENABLED 1 /* Interrupts enabled OFF ON */ +#define LED_STACKCREATED 2 /* Idle stack created ON OFF */ +#define LED_INIRQ 3 /* In an interrupt N/C GLOW */ +#define LED_SIGNAL 3 /* In a signal handler N/C GLOW */ +#define LED_ASSERTION 3 /* An assertion failed N/C GLOW */ +#define LED_PANIC 4 /* The system has crashed OFF BLINK */ +#undef LED_IDLE /* MCU is is sleep mode -Not used- */ + +/* Thus iF GLED is statically on, NuttX has successfully booted and is, + * apparently, running normally. A soft glow of the RLED means that the + * board is taking interrupts. If GLED is off and GLED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions *******************************************************/ + +/* Pin configuration ********************************************************/ + +#ifdef CONFIG_TIVA_UART0 +/* UART0: + * + * The on-board XDS110 Debugger provide a USB virtual serial console using + * UART0 (PA0/U0RX and PA1/U0TX). + */ + +# define GPIO_UART0_RX &g_gpio_uart0_rx +# define GPIO_UART0_TX &g_gpio_uart0_tx +#endif + +/* DMA **********************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Pin configuration ********************************************************/ + +struct cc13xx_pinconfig_s; /* Forward reference */ + +#ifdef CONFIG_TIVA_UART0 +extern const struct cc13xx_pinconfig_s g_gpio_uart0_rx; +extern const struct cc13xx_pinconfig_s g_gpio_uart0_tx; +#endif + +#endif /* __CONFIG_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/configs/launchxl-cc1310/nsh/defconfig b/configs/launchxl-cc1310/nsh/defconfig new file mode 100644 index 00000000000..cc567043df5 --- /dev/null +++ b/configs/launchxl-cc1310/nsh/defconfig @@ -0,0 +1,41 @@ +# CONFIG_NSH_DISABLE_DATE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="launchxl-cc1310" +CONFIG_ARCH_BOARD_LAUNCH_CC1310=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_CC1310=y +CONFIG_ARCH_CHIP_CC13X0=y +CONFIG_ARCH_CHIP_SIMPLELINK=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=8192 +CONFIG_BUILTIN=y +CONFIG_DISABLE_POLL=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=81920 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=12 +CONFIG_SYSTEM_NSH=y +CONFIG_TIVA_UART0=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/configs/launchxl-cc1310/scripts/Make.defs b/configs/launchxl-cc1310/scripts/Make.defs new file mode 100644 index 00000000000..fb77ac6b4e0 --- /dev/null +++ b/configs/launchxl-cc1310/scripts/Make.defs @@ -0,0 +1,125 @@ +############################################################################ +# configs/launchxl-cc1310/scripts/Make.defs +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/launchxl-cc1310/scripts/flash.ld b/configs/launchxl-cc1310/scripts/flash.ld new file mode 100644 index 00000000000..15a20f6843d --- /dev/null +++ b/configs/launchxl-cc1310/scripts/flash.ld @@ -0,0 +1,115 @@ +/**************************************************************************** + * configs/launchxl-cc1310/scripts/flash.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The CC1310 has 128Kb of FLASH beginning at address 0x0000:0000 and + * 20Kb of SRAM beginning at 0x2000:0000 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/launchxl-cc1310/src/Makefile b/configs/launchxl-cc1310/src/Makefile new file mode 100644 index 00000000000..5d872ca91c9 --- /dev/null +++ b/configs/launchxl-cc1310/src/Makefile @@ -0,0 +1,61 @@ +############################################################################ +# configs/launchxl-cc1310/src/Makefile +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = cc1310_boot.c cc1310_pinconfig.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += cc1310_appinit.c cc1310_bringup.c +else ifeq ($(CONFIG_BOARD_INITIALIZE),y) +CSRCS += cc1310_bringup.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += cc1310_autoleds.c +else +CSRCS += cc1310_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += cc1310_buttons.c +endif + +ifeq ($(CONFIG_TIVA_SSI),y) +CSRCS += cc1310_ssi.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/launchxl-cc1310/src/cc1310_appinit.c b/configs/launchxl-cc1310/src/cc1310_appinit.c new file mode 100644 index 00000000000..94cf6ff6a24 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_appinit.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * config/launchxl-cc1310/src/cc1310_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "launchxl-cc1310.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_INITIALIZE + /* Perform board initialization */ + + return cc1310_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/launchxl-cc1310/src/cc1310_autoleds.c b/configs/launchxl-cc1310/src/cc1310_autoleds.c new file mode 100644 index 00000000000..951d866ebf4 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_autoleds.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * configs/launchxl-cc1310/src/cc1310_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "tiva_gpio.h" +#include "launchxl-cc1310.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ +#warning Missing logic +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/launchxl-cc1310/src/cc1310_boot.c b/configs/launchxl-cc1310/src/cc1310_boot.c new file mode 100644 index 00000000000..584e0da3a30 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_boot.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * configs/launchxl-cc1310/src/cc1310_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "tiva_start.h" +#include "launchxl-cc1310.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tiva_boardinitialize + * + * Description: + * All Tiva architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void tiva_boardinitialize(void) +{ +#ifdef CONFIG_TIVA_SSI + /* Configure SSI chip select pins */ + + cc1310_ssidev_initialize(); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + + /* TODO: Initialize antenna switch */ + /* TODO: Shutdown external FLASH */ +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board initialization */ + + (void)cc1310_bringup(); +} +#endif /* CONFIG_BOARD_INITIALIZE */ diff --git a/configs/launchxl-cc1310/src/cc1310_bringup.c b/configs/launchxl-cc1310/src/cc1310_bringup.c new file mode 100644 index 00000000000..d891f3eceda --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_bringup.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * config/launchxl-cc1310/src/cc1310_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "launchxl-cc1310.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cc1310_bringup + * + * Description: + * Bring up board features. + * + * If CONFIG_BOARD_INITIALIZE=y, then this function will be called from + * board_initialize(). + * + * If CONFIG_BOARD_INITIALIZE is not selected, but CONFIG_LIB_BOARDCTL=y + * then this function will *probably* be called from application logic via + * boardctl(). + * + * Otherwise, this function will not be called (which is usually a bad + * thing) + * + ****************************************************************************/ + +int cc1310_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} diff --git a/configs/launchxl-cc1310/src/cc1310_buttons.c b/configs/launchxl-cc1310/src/cc1310_buttons.c new file mode 100644 index 00000000000..ba742491900 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_buttons.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * configs/launchxl-cc1310/src/cc1310_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "tiva_gpio.h" +#include "launchxl-cc1310.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the BUTTON* + * definitions above for the meaning of each bit in the returned value. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ +#warning Missing logic + return 0; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is one + * of the BUTTON* definitions provided above. + * + * Configuration Notes: + * Configuration CONFIG_SAMA5_PIO_IRQ must be selected to enable the + * overall PIO IRQ feature and CONFIG_SAMA5_PIOB_IRQ must be enabled to + * select PIOs to support interrupts on PIOE. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_TIVA_GPIOP_IRQS) +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ +#if 0 + irqstate_t flags; + int ret = -EINVAL; + + /* Interrupts are supported only on ports P and Q and, hence, only on button SW4 */ + + if (id == BUTTON_SW4) + { + /* The following should be atomic */ + + flags = enter_critical_section(); + + /* Detach and disable the button interrupt */ + + up_disable_irq(IRQ_SW4); + irq_detach(IRQ_SW4); + + /* Attach the new handler if so requested */ + + if (irqhandler != NULL) + { + ret = irq_attach(IRQ_SW4, irqhandler, arg); + if (ret == OK) + { + up_enable_irq(IRQ_SW4); + } + } + + leave_critical_section(flags); + } + + return ret; +#else +#warning Missing logic + return -ENOSYS; +#endif +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/launchxl-cc1310/src/cc1310_pinconfig.c b/configs/launchxl-cc1310/src/cc1310_pinconfig.c new file mode 100644 index 00000000000..4264c117f84 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_pinconfig.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * configs/launchxl-cc1310/src/cc1310_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/tiva_ioc.h" +#include "tiva_gpio.h" +#include "launchxl-cc1310.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_TIVA_UART0 +/* UART0: + * + * The on-board XDS110 Debugger provide a USB virtual serial console using + * UART0 (PA0/U0RX and PA1/U0TX). + */ + +const struct cc13xx_pinconfig_s g_gpio_uart0_rx = +{ + .gpio = GPIO_DIO(0), + .ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT +}; + +const struct cc13xx_pinconfig_s g_gpio_uart0_tx = +{ + .gpio = GPIO_DIO(1), + .ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT +}; +#endif \ No newline at end of file diff --git a/configs/launchxl-cc1310/src/cc1310_ssi.c b/configs/launchxl-cc1310/src/cc1310_ssi.c new file mode 100644 index 00000000000..e771b7e9876 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_ssi.c @@ -0,0 +1,117 @@ +/************************************************************************************ + * configs/launchxl-cc1310/src/cc1310_ssi.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "tiva_gpio.h" + +#include "launchxl-cc1310.h" + +#ifdef CONFIG_TIVA_SSI + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Enables debug output from this file */ + +#ifdef CONFIG_DEBUG_SPI +# define ssi_dumpgpio(m) tiva_dumpgpio(SDCCS_GPIO, m) +#else +# define ssi_dumpgpio(m) +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: cc1310_ssidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the DK-TM4C129X. + * + ************************************************************************************/ + +void cc1310_ssidev_initialize(void) +{ +} + +/**************************************************************************** + * The external functions, tiva_ssiselect and tiva_ssistatus must be provided + * by board-specific logic. The are implementations of the select and status + * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All othermethods (including tiva_ssibus_initialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide tiva_ssiselect() and tiva_ssistatus() functions in your + * board-specific logic. This function will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 2. Add a call to tiva_ssibus_initialize() in your low level initialization + * logic + * 3. The handle returned by tiva_ssibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +void tiva_ssiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + ssi_dumpgpio("tiva_ssiselect() Entry"); + ssi_dumpgpio("tiva_ssiselect() Exit"); +} + +uint8_t tiva_ssistatus(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} + +#endif /* CONFIG_TIVA_SSI */ diff --git a/configs/launchxl-cc1310/src/cc1310_userleds.c b/configs/launchxl-cc1310/src/cc1310_userleds.c new file mode 100644 index 00000000000..9b60c2fb426 --- /dev/null +++ b/configs/launchxl-cc1310/src/cc1310_userleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * configs/launchxl-cc1310/src/cc1310_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "tiva_gpio.h" +#include "launchxl-cc1310.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ +#warning Missing logic +} diff --git a/configs/launchxl-cc1310/src/launchxl-cc1310.h b/configs/launchxl-cc1310/src/launchxl-cc1310.h new file mode 100644 index 00000000000..fc10523cc72 --- /dev/null +++ b/configs/launchxl-cc1310/src/launchxl-cc1310.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * configs/launchxl-cc1310/src/launchxl-cc1310.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIG_LAUNCH_CC1310_SRC_LAUNCH_CC1310_H +#define __CONFIG_LAUNCH_CC1310_SRC_LAUNCH_CC1310_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: cc1310_bringup + * + * Description: + * Bring up board features. + * + * If CONFIG_BOARD_INITIALIZE=y, then this function will be called from + * board_initialize(). + * + * If CONFIG_BOARD_INITIALIZE is not selected, but CONFIG_LIB_BOARDCTL=y + * then this function will *probably* be called from application logic via + * boardctl(). + * + * Otherwise, this function will not be called (which is usually a bad + * thing) + * + ****************************************************************************/ + +int cc1310_bringup(void); + +/************************************************************************************ + * Name: cc1310_ssidev_initialize + * + * Description: + * Called to configure SSI chip select GPIO pins for the LAUNCHXL-CC1310 board. + * + ************************************************************************************/ + +#ifdef CONFIG_TIVA_SSI +void cc1310_ssidev_initialize(void); +#endif + +#endif /* __CONFIG_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/configs/launchxl-cc1312r1/include/board.h b/configs/launchxl-cc1312r1/include/board.h index 778bfbe0ed7..8e0bdb643e3 100644 --- a/configs/launchxl-cc1312r1/include/board.h +++ b/configs/launchxl-cc1312r1/include/board.h @@ -128,11 +128,11 @@ /* Pin configuration ********************************************************/ -struct cc134xx_pinconfig_s; /* Forward reference */ +struct cc13xx_pinconfig_s; /* Forward reference */ #ifdef CONFIG_TIVA_UART0 -extern const struct cc134xx_pinconfig_s g_gpio_uart0_rx; -extern const struct cc134xx_pinconfig_s g_gpio_uart0_tx; +extern const struct cc13xx_pinconfig_s g_gpio_uart0_rx; +extern const struct cc13xx_pinconfig_s g_gpio_uart0_tx; #endif #endif /* __CONFIG_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/configs/launchxl-cc1312r1/src/cc1312_pinconfig.c b/configs/launchxl-cc1312r1/src/cc1312_pinconfig.c index 2adde6b5ca5..7d98733d43e 100644 --- a/configs/launchxl-cc1312r1/src/cc1312_pinconfig.c +++ b/configs/launchxl-cc1312r1/src/cc1312_pinconfig.c @@ -54,13 +54,13 @@ * UART0 (PA0/U0RX and PA1/U0TX). */ -const struct cc134xx_pinconfig_s g_gpio_uart0_rx = +const struct cc13xx_pinconfig_s g_gpio_uart0_rx = { .gpio = GPIO_DIO(0), .ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT }; -const struct cc134xx_pinconfig_s g_gpio_uart0_tx = +const struct cc13xx_pinconfig_s g_gpio_uart0_tx = { .gpio = GPIO_DIO(1), .ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT