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SAMV7 USB: Move clock initialization back to sam_clockconfig.c; add seperate UTMI register definition header file; fix a couple of typo bugs
This commit is contained in:
Gregory Nutt
@@ -1,7 +1,7 @@
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/************************************************************************************************************
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* arch/arm/src/samv7/chip/sam_usbhs.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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@@ -126,10 +126,6 @@
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#define SAM_USBHS_SCR_OFFSET 0x0808 /* General Status Clear Register */
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#define SAM_USBHS_SFR_OFFSET 0x080c /* General Status Set Register */
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/* 0x0810-0x082c: Reserved */
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/* UTMI Registers */
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#define SAM_UTMI_OHCIICR_OFFSET 0x0010 /* OHCI Interrupt Configuration Register */
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#define SAM_UTMI_CKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */
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/* Register addresses ***************************************************************************************/
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@@ -195,11 +191,6 @@
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#define SAM_USBHS_SCR (SAM_USBHS_BASE+SAM_USBHS_SCR_OFFSET)
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#define SAM_USBHS_SFR (SAM_USBHS_BASE+SAM_USBHS_SFR_OFFSET)
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/* UTMI Registers */
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#define SAM_UTMI_OHCIICR (SAM_UTMI_BASE+SAM_UTMI_OHCIICR_OFFSET)
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#define SAM_UTMI_CKTRIM (SAM_UTMI_BASE+SAM_UTMI_CKTRIM_OFFSET)
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/* Register bit-field definitions ***************************************************************************/
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/* USBHS Device Controller Register Bit Field Definitions */
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@@ -304,7 +295,7 @@
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/* Device Endpoint Configuration Register */
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#define USBHS_DEVEPTCFG_ALLOC (1 << 0) /* Bit 0: Endpoint Memory Allocate */
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#define USBHS_DEVEPTCFG_ALLOC (1 << 1) /* Bit 1: Endpoint Memory Allocate */
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#define USBHS_DEVEPTCFG_EPBK_SHIFT (2) /* Bits 2-3: Endpoint Banks */
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#define USBHS_DEVEPTCFG_EPBK_MASK (3 << USBHS_DEVEPTCFG_EPBK_SHIFT)
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# define USBHS_DEVEPTCFG_EPBK(n) ((uint32_t)((n)-1) << USBHS_DEVEPTCFG_EPBK_SHIFT)
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@@ -779,22 +770,6 @@
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#define USBHS_SFR_RDERRIS (1 << 4) /* Bit 4: Remote Device Connection Error Interrupt Set */
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/* UTMI Registers */
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/* OHCI Interrupt Configuration Register */
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#define UTMI_OHCIICR_RES0 (1 << 0) /* Bit 0: USB PORT0 Reset */
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#define UTMI_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI Asynchronous Resume Interrupt Enable */
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#define UTMI_OHCIICR_APPSTART (0 << 5) /* Bit 5: Reserved, must be zero */
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#define UTMI_OHCIICR_UDPPUDIS (1 << 23) /* Bit 23: USB Device Pull-up Disable */
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/* UTMI Clock Trimming Register */
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#define UTMI_CKTRIM_FREQ_SHIFT (0) /* Bits 0-1: UTMI Reference Clock Frequency */
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#define UTMI_CKTRIM_FREQ_MASK (3 << UTMI_CKTRIM_FREQ_SHIFT)
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# define UTMI_CKTRIM_FREQ_XTAL12 (0 << UTMI_CKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */
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# define UTMI_CKTRIM_FREQ_XTAL16 (1 << UTMI_CKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */
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/************************************************************************************************************
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* Public Types
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************************************************************************************************************/
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@@ -0,0 +1,92 @@
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/************************************************************************************************************
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* arch/arm/src/samv7/chip/sam_utmi.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* SAMV7D3 Series Data Sheet
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UTMI_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UTMI_H
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/************************************************************************************************************
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* Included Files
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************************************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/samv7/chip.h>
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#include "chip/sam_memorymap.h"
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/************************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************************/
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/* Register offsets *****************************************************************************************/
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#define SAM_UTMI_OHCIICR_OFFSET 0x0010 /* OHCI Interrupt Configuration Register */
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#define SAM_UTMI_CKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */
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/* Register addresses ***************************************************************************************/
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#define SAM_UTMI_OHCIICR (SAM_UTMI_BASE+SAM_UTMI_OHCIICR_OFFSET)
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#define SAM_UTMI_CKTRIM (SAM_UTMI_BASE+SAM_UTMI_CKTRIM_OFFSET)
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/* Register bit-field definitions ***************************************************************************/
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/* OHCI Interrupt Configuration Register */
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#define UTMI_OHCIICR_RES0 (1 << 0) /* Bit 0: USB PORT0 Reset */
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#define UTMI_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI Asynchronous Resume Interrupt Enable */
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#define UTMI_OHCIICR_APPSTART (0 << 5) /* Bit 5: Reserved, must be zero */
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#define UTMI_OHCIICR_UDPPUDIS (1 << 23) /* Bit 23: USB Device Pull-up Disable */
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/* UTMI Clock Trimming Register */
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#define UTMI_CKTRIM_FREQ_SHIFT (0) /* Bits 0-1: UTMI Reference Clock Frequency */
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#define UTMI_CKTRIM_FREQ_MASK (3 << UTMI_CKTRIM_FREQ_SHIFT)
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# define UTMI_CKTRIM_FREQ_XTAL12 (0 << UTMI_CKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */
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# define UTMI_CKTRIM_FREQ_XTAL16 (1 << UTMI_CKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */
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/************************************************************************************************************
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* Public Types
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************************************************************************************************************/
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/************************************************************************************************************
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* Public Data
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************************************************************************************************************/
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/************************************************************************************************************
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* Public Functions
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************************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UTMI_H */
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@@ -54,11 +54,17 @@
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#include "chip/sam_wdt.h"
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#include "chip/sam_supc.h"
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#include "chip/sam_matrix.h"
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#include "chip/sam_utmi.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ***********************************************************/
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/* Not yet supported */
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#undef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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/* Board Settings **********************************************************/
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/* PMC register settings based on the board configuration values defined
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* in board.h
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*/
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@@ -223,6 +229,80 @@ static inline void sam_pmcsetup(void)
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putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
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sam_pmcwait(PMC_INT_LOCKA);
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#ifdef CONFIG_USBDEV
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/* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */
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#if 0 /* REVISIT: Does this apply only to OHCI? */
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putreg32(UTMI_OHCIICR_RES0, SAM_UTMI_OHCIICR);
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#endif
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#if BOARD_MAINOSC_FREQUENCY == 12000000
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putreg32(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM);
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#elif BOARD_MAINOSC_FREQUENCY == 12000000
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putreg32(UTMI_CKTRIM_FREQ_XTAL16, SAM_UTMI_CKTRIM);
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#else
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# error ERROR: Unrecognized MAINSOSC frequency
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#endif
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/* Enable UTMI Clocking. The USBHS can work in two modes:
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*
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* - Normal mode where High speed, Full speed and Low speed are available.
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* - Low-power mode where only Full speed and Low speed are available.
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*
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* Only the normal mode is supported by this logic.
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*/
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#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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/* UTMI Low-power mode, Full/Low Speed mode
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*
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* Enable the 48MHz FS Clock.
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*/
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putreg32(PMC_USBCLK, SAM_PMC_SCER);
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#else
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/* UTMI normal mode, High/Full/Low Speed
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*
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* Disable the 48MHz USB FS Clock. It is not used in this configuration
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*/
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putreg32(PMC_USBCLK, SAM_PMC_SCDR);
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#endif
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/* Select the UTMI PLL as the USB PLL clock input (480MHz) with divider
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* to get to 48MHz. UPLL output frequency is determined only by the
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* 12/16MHz crystal selection above.
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*/
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regval = PMC_USB_USBS_UPLL;
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#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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if ((getreg32(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
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{
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/* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
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regval |= PMC_USB_USBDIV(4);
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}
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else
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{
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/* Divider = 480 Mhz / 1 / 48 Mhz = 10 */
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regval |= PMC_USB_USBDIV(9);
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}
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#endif
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putreg32(regval, SAM_PMC_USB);
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/* Enable the UTMI PLL with the maximum start-up time */
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regval = PMC_CKGR_UCKR_UPLLEN | PMC_CKGR_UCKR_UPLLCOUNT_MAX;
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putreg32(regval, SAM_PMC_CKGR_UCKR);
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/* Wait for LOCKU */
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sam_pmcwait(PMC_INT_LOCKU);
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#endif
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/* Switch to the fast clock and wait for MCKRDY */
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putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR);
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@@ -73,7 +73,6 @@
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#include "cache.h"
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#include "sam_periphclks.h"
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#include "chip/sam_pmc.h"
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#include "chip/sam_usbhs.h"
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#include "sam_usbdev.h"
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@@ -118,7 +117,7 @@
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#define EP0 (0)
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#define SAM_EPSET_ALL (0xffff) /* All endpoints */
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#define SAM_EPSET_NOTEP0 (0xfffe) /* All endpoints except EP0 */
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#define SAM_EPSET_DMA (0x00fe) /* All endpoints that support DMA transfers */
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#define SAM_EPSET_DMA (0x01fe) /* All endpoints that support DMA transfers */
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#define SAM_EP_BIT(ep) (1 << (ep))
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#define SAM_EP0_MAXPACKET (64) /* EP0 Max. packet size */
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@@ -479,6 +478,8 @@ static inline bool
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sam_ep_reserved(struct sam_usbdev_s *priv, int epno);
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static int sam_ep_configure_internal(struct sam_ep_s *privep,
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const struct usb_epdesc_s *desc);
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static inline int
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sam_ep0_configure(struct sam_usbdev_s *priv);
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/* Endpoint operations ******************************************************/
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@@ -815,26 +816,26 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno)
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/* Global Registers */
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lldbg("Global Register:\n");
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lldbg(" CTRL: %04x\n", sam_getreg(SAM_USBHS_DEVCTRL));
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lldbg(" IISR: %04x\n", sam_getreg(SAM_USBHS_DEVISR));
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lldbg(" IMR: %04x\n", sam_getreg(SAM_USBHS_DEVIMR));
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lldbg(" EPT: %04x\n", sam_getreg(SAM_USBHS_DEVEPT));
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lldbg(" FNUM: %04x\n", sam_getreg(SAM_USBHS_DEVFNUM));
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lldbg(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL));
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lldbg(" IISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR));
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lldbg(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR));
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lldbg(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT));
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lldbg(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM));
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/* Endpoint registers */
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lldbg("Endpoint %d Register:\n", epno);
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lldbg(" CFG: %04x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno)));
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lldbg(" ISR: %04x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno)));
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lldbg(" IMR: %04x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno)));
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lldbg(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno)));
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lldbg(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno)));
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lldbg(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno)));
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lldbg("DMA %d Register:\n", epno);
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if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0)
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{
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lldbg(" NXTDSC: %04x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno)));
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lldbg(" ADDRESS: %04x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno)));
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lldbg(" CONTROL: %04x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno)));
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lldbg(" STATUS: %04x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno)));
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lldbg(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno)));
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lldbg(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno)));
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lldbg(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno)));
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lldbg(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno)));
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}
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else
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{
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@@ -3306,7 +3307,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
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sam_putreg(USBHS_DEVEPTIDR_ALLINTS, SAM_USBHS_DEVEPTIDR(epno));
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/* Reset Endpoint FIFOs */
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/* Clear toggle and stall indications */
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sam_putreg(USBHS_DEVEPTISR_DTSEQ_MASK | USBHS_DEVEPTINT_STALLEDI,
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SAM_USBHS_DEVEPTICR(epno));
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@@ -3382,6 +3383,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
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* the FIFO maximum capacity and the maximum number of allowed banks.
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*/
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regaddr = SAM_USBHS_DEVEPTISR(epno);
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if ((sam_getreg(regaddr) & USBHS_DEVEPTISR_CFGOK) == 0)
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{
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usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NCFGOK), epno);
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@@ -3444,6 +3446,19 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
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return OK;
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}
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/****************************************************************************
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* Name: sam_ep0_configure
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*
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* Description:
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* Configure EP0 for normal operation.
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*
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****************************************************************************/
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static inline int sam_ep0_configure(struct sam_usbdev_s *priv)
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{
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return sam_ep_configure_internal(&priv->eplist[EP0], &g_ep0desc);
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}
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/****************************************************************************
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* Endpoint operations
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****************************************************************************/
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@@ -4232,7 +4247,7 @@ static void sam_reset(struct sam_usbdev_s *priv)
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/* Reset and disable all endpoints other. Then re-configure EP0 */
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sam_epset_reset(priv, SAM_EPSET_ALL);
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sam_ep_configure_internal(&priv->eplist[EP0], &g_ep0desc);
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sam_ep0_configure(priv);
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/* Reset endpoint data structures */
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@@ -4306,6 +4321,8 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
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* 2. Enable the USBHS (UIMOD = 1, USBE = 1, FRZCLK = 0).
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* 3. Enable the UPLL 480 MHz.
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* 4. Wait for the UPLL 480 MHz to be considered as locked by the PMC.
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*
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* Steps 1,3, and 4 were performed in sam_clockconfig.c.
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*/
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/* Enable the USBHS peripheral clock (PMC_PCER) */
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@@ -4325,65 +4342,6 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
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regval |= USBHS_CTRL_UIMOD_DEVICE;
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sam_putreg(regval, SAM_USBHS_CTRL);
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/* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */
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#if 0 /* REVISIT: Does this apply only to OHCI? */
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sam_putreg(UTMI_OHCIICR_RES0, SAM_UTMI_OHCIICR);
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#endif
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#if BOARD_MAINOSC_FREQUENCY == 12000000
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sam_putreg(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM);
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#elif BOARD_MAINOSC_FREQUENCY == 12000000
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sam_putreg(UTMI_CKTRIM_FREQ_XTAL16, SAM_UTMI_CKTRIM);
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#else
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# error ERROR: Unrecognized MAINSOSC frequency
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#endif
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#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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/* UTMI Full/Low Speed mode */
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sam_putreg(PMC_USBCLK, SAM_PMC_SCER);
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#else
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/* UTMI parallel mode, High/Full/Low Speed
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*
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* Disable 48MHz USB FS Clock. It is not used in this configuration
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*/
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||||
|
||||
sam_putreg(PMC_USBCLK, SAM_PMC_SCDR);
|
||||
#endif
|
||||
|
||||
/* Select the UTMI PLL as the USB PLL clock input (480MHz) with divider
|
||||
* to get to 48MHz.
|
||||
*/
|
||||
|
||||
regval = PMC_USB_USBS_UPLL;
|
||||
|
||||
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
|
||||
if ((sam_getreg(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
|
||||
{
|
||||
/* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
|
||||
|
||||
regval |= PMC_USB_USBDIV(4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Divider = 480 Mhz / 1 / 48 Mhz = 10 */
|
||||
|
||||
regval |= PMC_USB_USBDIV(9);
|
||||
}
|
||||
#endif
|
||||
|
||||
sam_putreg(regval, SAM_PMC_USB);
|
||||
|
||||
/* Enable the UTMI PLL with the maximum start-up time */
|
||||
|
||||
regval = PMC_CKGR_UCKR_UPLLEN | PMC_CKGR_UCKR_UPLLCOUNT_MAX;
|
||||
sam_putreg(regval, SAM_PMC_CKGR_UCKR);
|
||||
|
||||
/* Wait for LOCKU */
|
||||
|
||||
while ((sam_getreg(SAM_PMC_SR) & PMC_INT_LOCKU) == 0);
|
||||
|
||||
/* Select High Speed */
|
||||
|
||||
regval = sam_getreg(SAM_USBHS_DEVCTRL);
|
||||
|
||||
Reference in New Issue
Block a user