diff --git a/arch/arm/src/samdl/chip/samd_pm.h b/arch/arm/src/samdl/chip/samd_pm.h
index 828b45dd642..7c3e7f08724 100644
--- a/arch/arm/src/samdl/chip/samd_pm.h
+++ b/arch/arm/src/samdl/chip/samd_pm.h
@@ -93,8 +93,10 @@
 
 /* Control register */
 
-#define PM_CTRL_CFDEN             (1 << 2)  /* Bit 2: Clock Failure Detector Enable */
-#define PM_CTRL_BKUPCLK           (1 << 4)  /* Bit 4: Backup Clock Select */
+#ifdef CONFIG_ARCH_FAMILY_SAMD20
+#  define PM_CTRL_CFDEN           (1 << 2)  /* Bit 2: Clock Failure Detector Enable */
+#  define PM_CTRL_BKUPCLK         (1 << 4)  /* Bit 4: Backup Clock Select */
+#endif
 
 /* Sleep mode register */
 
@@ -226,7 +228,7 @@
 #define PM_APBCMASK_PTC           (1 << 19) /* Bit 19: PTC */
 
 #ifdef CONFIG_ARCH_FAMILY_SAMD21
-#  define PM_APBBMASK_I2S         (1 << 10) /* Bit 20: Inter IC Sound */
+#  define PM_APBBMASK_I2S         (1 << 20) /* Bit 20: Inter IC Sound */
 #endif
 
 /* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */
diff --git a/arch/arm/src/samdl/chip/samd_sysctrl.h b/arch/arm/src/samdl/chip/samd_sysctrl.h
index 5fb9f7b516a..a4c6cdd069b 100644
--- a/arch/arm/src/samdl/chip/samd_sysctrl.h
+++ b/arch/arm/src/samdl/chip/samd_sysctrl.h
@@ -81,8 +81,8 @@
 #ifdef CONFIG_ARCH_FAMILY_SAMD21
 #  define SAM_SYSCTRL_DPLLCTRLA_OFFSET  0x0044  /* DPLL Control A */
 #  define SAM_SYSCTRL_DPLLRATIO_OFFSET  0x0048  /* DPLL ratio control */
-#  define SAM_SYSCTRL_DPLLCTRLB_OFFSET  0x0048  /* DPLL Control B */
-#  define SAM_SYSCTRL_DPLLSTATUS_OFFSET 0x0048  /* DPLL status */
+#  define SAM_SYSCTRL_DPLLCTRLB_OFFSET  0x004c  /* DPLL Control B */
+#  define SAM_SYSCTRL_DPLLSTATUS_OFFSET 0x0050  /* DPLL status */
 #endif
 
 /* SYSCTRL register addresses ***************************************************************/