diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c
index fa6151355fc..7b4f6ca258a 100644
--- a/arch/arm/src/stm32/stm32f30xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c
@@ -52,6 +52,15 @@
 #  error "STM32_SYSCLK_FREQUENCY is out of range!"
 #endif
 
+/* Max ADC clock frequency is 72MHz */
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
+    defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
+#  if STM32_PLL_FREQUENCY > 72000000
+#    error ADCxxPRES is hardcoded to 1 - PLL frequency is too high
+#  endif
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -555,6 +564,24 @@ static void stm32_stdclockconfig(void)
 
   stm32_rcc_enablelse();
 #endif
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
+  /* Configure ADC12 clock */
+
+  regval  = getreg32(STM32_RCC_CFGR2);
+  regval &= ~RCC_CFGR2_ADC12PRES_MASK;
+  regval |= RCC_CFGR2_ADC12PRESd1;
+  putreg32(regval, STM32_RCC_CFGR2);
+#endif
+
+#if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
+  /* Configure ADC34 clock */
+
+  regval  = getreg32(STM32_RCC_CFGR2);
+  regval &= ~RCC_CFGR2_ADC34PRES_MASK;
+  regval |= RCC_CFGR2_ADC34PRESd1;
+  putreg32(regval, STM32_RCC_CFGR2);
+#endif
 }
 #endif
 
diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c
index 498fb901ed9..a9245e570d3 100644
--- a/arch/arm/src/stm32/stm32f33xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c
@@ -52,6 +52,14 @@
 #  error "STM32_SYSCLK_FREQUENCY is out of range!"
 #endif
 
+/* Max ADC clock frequency is 72MHz */
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
+#  if STM32_PLL_FREQUENCY > 72000000
+#    error ADCxxPRES is hardcoded to 1 - PLL frequency is too high
+#  endif
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -486,6 +494,15 @@ static void stm32_stdclockconfig(void)
   regval |= RCC_CFGR3_HRTIM1SW;
   putreg32(regval, STM32_RCC_CFGR3);
 #endif
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
+  /* Configure ADC12 clock */
+
+  regval  = getreg32(STM32_RCC_CFGR2);
+  regval &= ~RCC_CFGR2_ADC12PRES_MASK;
+  regval |= RCC_CFGR2_ADC12PRESd1;
+  putreg32(regval, STM32_RCC_CFGR2);
+#endif
 }
 #endif