diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index e7f830ed2ba..80da35c00ca 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -81,36 +81,43 @@ config ARCH_FAMILY_LPC4320 bool default y if ARCH_CHIP_LPC4320FBD144 || ARCH_CHIP_LPC4320FET100 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 config ARCH_FAMILY_LPC4330 bool default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 || ARCH_CHIP_LPC4337JET100 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 config ARCH_FAMILY_LPC4337 bool default y if ARCH_CHIP_LPC4337JBD144 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 config ARCH_FAMILY_LPC4350 bool default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 config ARCH_FAMILY_LPC4353 bool default y if ARCH_CHIP_LPC4353FBD208 || ARCH_CHIP_LPC4353FET180 || ARCH_CHIP_LPC4353FET256 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 config ARCH_FAMILY_LPC4357 bool default y if ARCH_CHIP_LPC4357FET180 || ARCH_CHIP_LPC4357FBD208 || ARCH_CHIP_LPC4357FET256 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 config ARCH_FAMILY_LPC4370 bool default y if ARCH_CHIP_LPC4370FET100 select ARCH_HAVE_TICKLESS + select ARCH_HAVE_AHB_SRAM_BANK1 choice prompt "LPC43XX Boot Configuration" @@ -177,9 +184,15 @@ config LPC43_DAC config LPC43_EMC bool "External Memory Controller (EMC)" default n + select ARCH_HAVE_EXTSDRAM0 + select ARCH_HAVE_EXTSDRAM1 + select ARCH_HAVE_EXTSDRAM2 + select ARCH_HAVE_EXTSDRAM3 config LPC43_ETHERNET bool "Ethernet" + select NETDEVICES + select ARCH_HAVE_PHY default n config LPC43_EVNTMNTR @@ -320,6 +333,158 @@ config LPC43_GPIO_IRQ ---help--- Enable support for GPIO interrupts +menu "Internal Memory Configuration" + +config ARCH_HAVE_AHB_SRAM_BANK1 + bool + +if !LPC43_BOOT_SRAM + +config LPC43_USE_LOCSRAM_BANK1 + bool "Use local SRAM bank 1 memory region" + default n + ---help--- + Add local SRAM bank 1 memory region. + +endif # LPC43_BOOT_SRAM + +config LPC43_USE_AHBSRAM_BANK0 + bool "Use AHB SRAM bank 0 memory region" + default n + ---help--- + Add local AHB SRAM bank 0 memory region. + +config LPC43_USE_AHBSRAM_BANK1 + bool "Use AHB SRAM bank 1 memory region" + default n + depends on ARCH_HAVE_AHB_SRAM_BANK1 + ---help--- + Add local AHB SRAM bank 1 memory region. + +config LPC43_HEAP_AHBSRAM_BANK2 + bool "Use AHB SRAM bank 2 (ETB SRAM) memory region" + default n + ---help--- + Add local AHB SRAM bank 2 (ETB SRAM) memory region. + +endmenu # LPC43xx Internal Memory Configuration + +menu "External Memory Configuration" + +config ARCH_HAVE_EXTSDRAM0 + bool + +config ARCH_HAVE_EXTSDRAM1 + bool + +config ARCH_HAVE_EXTSDRAM2 + bool + +config ARCH_HAVE_EXTSDRAM3 + bool + +config LPC43_EXTSDRAM0 + bool "Configure external SDRAM0 (on DYNCS0)" + default n + depends on ARCH_HAVE_EXTSDRAM0 + select ARCH_HAVE_EXTSDRAM + ---help--- + Configure external SDRAM memory and, if applicable, map then external + SDRAM into the memory map. + +if LPC43_EXTSDRAM0 + +config LPC43_EXTSDRAM0_SIZE + int "External SDRAM0 size" + default 0 + ---help--- + Size of the external SDRAM on DYNCS0 in bytes. + +config LPC43_EXTSDRAM0_HEAP + bool "Add external SDRAM on DYNCS0 to the heap" + default y + ---help--- + Add the external SDRAM on DYNCS0 into the heap. + +endif # LCP43_EXTSDRAM0 + +config LPC43_EXTSDRAM1 + bool "Configure external SDRAM1 (on DYNCS1)" + default n + depends on ARCH_HAVE_EXTSDRAM1 + select ARCH_HAVE_EXTSDRAM + ---help--- + Configure external SDRAM memoryand, if applicable, map then external + SDRAM into the memory map. + +if LPC43_EXTSDRAM1 + +config LPC43_EXTSDRAM1_SIZE + int "External SDRAM1 size" + default 0 + ---help--- + Size of the external SDRAM on DYNCS1 in bytes. + +config LPC43_EXTSDRAM1_HEAP + bool "Add external SDRAM on DYNCS1 to the heap" + default y + ---help--- + Add the external SDRAM on DYNCS1 into the heap. + +endif # LCP43_EXTSDRAM1 + +config LPC43_EXTSDRAM2 + bool "Configure external SDRAM2 (on DYNCS2)" + default n + depends on ARCH_HAVE_EXTSDRAM2 + select ARCH_HAVE_EXTSDRAM + ---help--- + Configure external SDRAM memoryand, if applicable, map then external + SDRAM into the memory map. + +if LPC43_EXTSDRAM2 + +config LPC43_EXTSDRAM2_SIZE + int "External SDRAM2 size" + default 0 + ---help--- + Size of the external SDRAM on DYNCS2 in bytes. + +config LPC43_EXTSDRAM2_HEAP + bool "Add external SDRAM on DYNCS2 to the heap" + default y + ---help--- + Add the external SDRAM on DYNCS2 into the heap. + +endif # LCP43_EXTSDRAM2 + +config LPC43_EXTSDRAM3 + bool "Configure external SDRAM3 (on DYNCS3)" + default n + depends on ARCH_HAVE_EXTSDRAM3 + select ARCH_HAVE_EXTSDRAM + ---help--- + Configure external SDRAM memoryand, if applicable, map then external + SDRAM into the memory map. + +if LPC43_EXTSDRAM3 + +config LPC43_EXTSDRAM3_SIZE + int "External SDRAM3 size" + default 0 + ---help--- + Size of the external SDRAM in bytes. + +config LPC43_EXTSDRAM3_HEAP + bool "Add external SDRAM on DYNCS3 to the heap" + default y + ---help--- + Add the external SDRAM on DYNCS3 into the heap. + +endif # LCP43_EXTSDRAM3 + +endmenu # External Memory Configuration + if LPC43_ETHERNET menu "Ethernet MAC configuration" diff --git a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h index 1b8312c965f..852bd2a862e 100644 --- a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h +++ b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h @@ -90,6 +90,8 @@ /* AHB SRAM */ #define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE) +#define LPC43_AHBSRAM_BANK1_BASE (LPC43_AHBSRAM_BASE + 0x00008000) +#define LPC43_AHBSRAM_BANK2_BASE (LPC43_AHBSRAM_BASE + 0x0000c000) #define LPC43_EEPROM_BASE (LPC43_AHBSRAM_BASE + 0x00004000) #define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x02000000) diff --git a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h index b29722479a3..41a5d939540 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h @@ -190,86 +190,86 @@ #define PINCONF_CTOUT15_2 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_0) #define PINCONF_CTOUT15_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_9) -#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_10) -#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_11) -#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_12) -#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_13) -#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_0) -#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_1) -#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_2) -#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_8) -#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_7) -#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_6) -#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_2) -#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_1) -#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_0) -#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_8) -#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_7) -#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_16) -#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_15) -#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_0) -#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_1) -#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_2) -#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_3) -#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_4) -#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_4) -#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_4) -#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_6) -#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_13) -#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_10) -#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_4) -#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_11) -#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_2) -#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_1) -#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_15) -#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_5) -#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_3) -#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_12) -#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_11) -#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_7) -#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_8) -#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_13) -#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_14) -#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_4) -#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_5) -#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_6) -#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_7) -#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_0) -#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_1) -#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_2) -#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_3) -#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_2) -#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_3) -#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_4) -#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_5) -#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_6) -#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_7) -#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_8) -#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_9) -#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_5) -#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_6) -#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_7) -#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_8) -#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_9) -#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_10) -#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_11) -#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_12) -#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_12) -#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_10) -#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_0) -#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_13) -#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_9) -#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_1) -#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_14) -#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_14) -#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_3) -#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5) -#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_9) +#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_10) +#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_11) +#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_12) +#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_13) +#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_0) +#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_1) +#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_2) +#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_8) +#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_7) +#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_6) +#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_2) +#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_1) +#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_0) +#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_8) +#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_7) +#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_16) +#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_15) +#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_0) +#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_1) +#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_2) +#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_3) +#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_4) +#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSA|PINCONF_PIN_4) +#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_4) +#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_6) +#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_13) +#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_10) +#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_4) +#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_11) +#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_2) +#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_1) +#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_15) +#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_5) +#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_3) +#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_12) +#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_11) +#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_7) +#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_8) +#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) +#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_14) +#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_4) +#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_5) +#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_6) +#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_7) +#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_0) +#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_1) +#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_2) +#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_3) +#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_2) +#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_3) +#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_4) +#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_5) +#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_6) +#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_7) +#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_8) +#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_9) +#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_5) +#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_6) +#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_7) +#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_8) +#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_9) +#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_10) +#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_11) +#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_12) +#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_12) +#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_10) +#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_0) +#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_13) +#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_9) +#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_1) +#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_14) +#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_14) +#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_3) +#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_5) +#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) #define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1) #define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_6) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h index a2cb20ca62f..51cdcdb9fc9 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * arch/arm/src/lpc43xx/chip/lpc43_ccu.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,7 @@ /**************************************************************************************************** * Pre-processor Definitions ****************************************************************************************************/ + /* Register Offsets *********************************************************************************/ #define LPC43_CCU1_PM_OFFSET 0x0000 /* CCU1 power mode register */ @@ -343,6 +344,23 @@ #define CCU_CLK_STAT_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable status */ /* Bits 3-31: Reserved */ +/* CCU1 Branch Clock EMCDIV Configuration Registers */ + +#define CCU_CLK_EMCDIV_CFG_RUN (1 << 0) /* Bit 0: Run enable */ +#define CCU_CLK_EMCDIV_CFG_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable */ +#define CCU_CLK_EMCDIV_CFG_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable */ + /* Bits 3-4: Reserved */ +#define CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT (5) /* Bits 5-7: Clock divider */ +#define CCU_CLK_EMCDIV_CLOCK_DIV_MASK (7 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) +# define CCU_CLK_EMCDIV_CFG_DIV_FUNC(n) ((n) << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) +# define CCU_CLK_EMCDIV_CFG_DIV_NODIV (0 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: No division */ +# define CCU_CLK_EMCDIV_CFG_DIV_BY2 (1 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: Division by 2 */ + /* Bits 8-26: Reserved */ +#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT (27) /* Bits 27-29: Clock divider status */ +#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK (7 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT) +# define CCU_CLK_EMCDIV_CFG_DIVSTAT_NODIV (0 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT) /* Bit 27-29: No division */ +# define CCU_CLK_EMCDIV_CFG_DIVSTAT_BY2 (1 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK) /* Bit 26-29: Divistion by 2 */ + /**************************************************************************************************** * Public Types ****************************************************************************************************/ diff --git a/arch/arm/src/lpc43xx/chip/lpc43_emc.h b/arch/arm/src/lpc43xx/chip/lpc43_emc.h index 4fb3ae38be6..b61cbcbc585 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_emc.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_emc.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * arch/arm/src/lpc43xx/chip/lpc43_emc.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,7 @@ /**************************************************************************************************** * Pre-processor Definitions ****************************************************************************************************/ + /* Register Offsets *********************************************************************************/ #define LPC43_EMC_CONTROL_OFFSET 0x0000 /* EMC Control register */ @@ -213,6 +214,7 @@ #define EMC_CONTROL_LOWPOWER (1 << 2) /* Bit 2: Low-power mode */ /* Bits 3-31: Reserved */ /* EMC Status register */ + #define EMC__ #define EMC_STATUS_BUSY (1 << 0) /* Bit 0: Busy */ #define EMC_STATUS_WB (1 << 1) /* Bit 1: Write buffer status */ @@ -333,13 +335,64 @@ # define EMC_DYNCONFIG_MD_SDRAM (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM (POR reset value) */ /* Bits 5-6: Reserved */ #define EMC_DYNCONFIG_AM0_SHIFT (7) /* Bits 7-12: AM0 Address mapping (see user manual) */ -#define EMC_DYNCONFIG_AM0_MASK (0x3f << EMC_DYNCONFIG_AM0_SHIFT) +#define EMC_DYNCONFIG_AM0_MASK (0x3F << EMC_DYNCONFIG_AM0_SHIFT) /* Bit 13: Reserved */ #define EMC_DYNCONFIG_AM1 (1 << 14) /* Bit 14: AM1 Address mapping (see user manual) */ /* Bits 15-18: Reserved */ -#define EMC_DYNCONFIG_BENA (1 << 10) /* Bit 19: Buffer enable */ +#define EMC_DYNCONFIG_BENA (1 << 19) /* Bit 19: Buffer enable */ #define EMC_DYNCONFIG_WP (1 << 20) /* Bit 20: Write protect. */ /* Bits 21-31: Reserved */ + +/* Dynamic Memory Configuration register Memory Configuration Values */ +/* TODO: complete configuration */ + +/* Data Bus Width Value in LPC43_EMC_DYNCONFIG register (bit 14) */ + +#define EMC_DYNCONFIG_DATA_BUS_16 (0 << 14) /* Data bus width 16 bit */ +#define EMC_DYNCONFIG_DATA_BUS_32 (1 << 14) /* Data bus width 32 bit */ + +/* Low power SDRAM value in LPC43_EMC_DYNCONFIG register (bit 12) */ + +#define EMC_DYNCONFIG_LPSDRAM (1 << 12) /* Low power SDRAM value (Bank, Row, Column)*/ +#define EMC_DYNCONFIG_HPSDRAM (0 << 12) /* High performance SDRAM value (Row, Bank, Column)*/ + +/* Address mapping table for LPC43_EMC_DYNCONFIG register (bits 7-11) */ + +/* Device size bits in LPC43_EMC_DYNCONFIG register (bits 9-11) */ + +#define EMC_DYNCONFIG_DEV_SIZE_SHIFT (9) +#define EMC_DYNCONFIG_DEV_SIZE_MASK (0x7) +# define EMC_DYNCONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYNCONFIG_DEV_SIZE_SHIFT) +# define EMC_DYNCONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYNCONFIG_DEV_SIZE_SHIFT) +# define EMC_DYNCONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYNCONFIG_DEV_SIZE_SHIFT) +# define EMC_DYNCONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYNCONFIG_DEV_SIZE_SHIFT) +# define EMC_DYNCONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYNCONFIG_DEV_SIZE_SHIFT) + +/* Bus width bits in LPC43_EMC_DYNCONFIG register (bits 7-8) */ + +#define EMC_DYNCONFIG_DEV_BUS_SHIFT (7) +#define EMC_DYNCONFIG_DEV_BUS_MASK (0x3) +# define EMC_DYNCONFIG_DEV_BUS_8 (0x00 << EMC_DYNCONFIG_DEV_BUS_SHIFT) +# define EMC_DYNCONFIG_DEV_BUS_16 (0x01 << EMC_DYNCONFIG_DEV_BUS_SHIFT) +# define EMC_DYNCONFIG_DEV_BUS_32 (0x02 << EMC_DYNCONFIG_DEV_BUS_SHIFT) + +#define EMC_DYNCONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /* 16Mb (2Mx8), 2 banks, row length = 11, column length = 9 */ +#define EMC_DYNCONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /* 16Mb (1Mx16), 2 banks, row length = 11, column length = 8 */ +#define EMC_DYNCONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /* 64Mb (8Mx8), 4 banks, row length = 12, column length = 9 */ +#define EMC_DYNCONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /* 64Mb (4Mx16), 4 banks, row length = 12, column length = 8 */ +#define EMC_DYNCONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /* 64Mb (2Mx32), 4 banks, row length = 11, column length = 8, 32 bit bus only */ +#define EMC_DYNCONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /* 128Mb (16Mx8), 4 banks, row length = 12, column length = 10 */ +#define EMC_DYNCONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /* 128Mb (8Mx16), 4 banks, row length = 12, column length = 9 */ +#define EMC_DYNCONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /* 128Mb (4Mx32), 4 banks, row length = 12, column length = 8 */ +#define EMC_DYNCONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /* 256Mb (32Mx8), 4 banks, row length = 13, column length = 10, 32 bit bus only */ +#define EMC_DYNCONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /* 256Mb (16Mx16), 4 banks, row length = 13, column length = 9 */ +#define EMC_DYNCONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /* 256Mb (8Mx32), 4 banks, row length = 13, column length = 8, 32 bit bus only */ +#define EMC_DYNCONFIG_8Mx32_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /* 256Mb (8Mx32), 4 banks, row length = 12, column length = 9, 32 bit bus only */ +#define EMC_DYNCONFIG_64Mx8_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x0 << 7)) /* 512Mb (64Mx8), 4 banks, row length = 13, column length = 11 */ +#define EMC_DYNCONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /* 512Mb (32Mx16), 4 banks, row length = 13, column length = 10 */ +#define EMC_DYNCONFIG_16Mx32_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /* 512Mb (16Mx32), 4 banks, row length = 13, column length = 9, 32 bit bus only */ +#define EMC_DYNCONFIG_32Mx32_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /* 1Gb (32Mx32), 4 banks, row length = 13, column length = 10,32 bit bus only */ + /* Dynamic Memory RAS & CAS Delay registers */ #define EMC_DYNRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency (active to read/write delay) */ @@ -354,6 +407,35 @@ # define EMC_DYNRASCAS_CAS_2CCLK (2 << EMC_DYNRASCAS_CAS_SHIFT) /* Two CCLK cycles */ # define EMC_DYNRASCAS_CAS_3CCLK (3 << EMC_DYNRASCAS_CAS_SHIFT) /* Three CCLK cycles (POR reset value) */ /* Bits 10-31: Reserved */ + +/* Dynamic SDRAM mode register definitions */ + + /* Bits 0-2: Burst length. All other values are reserved. */ +#define EMC_DYNMODE_BURST_LENGTH_SHIFT (0) +#define EMC_DYNMODE_BURST_LENGTH_MASK (0x7) +# define EMC_DYNMODE_BURST_LENGTH_1 (0 << EMC_DYNMODE_BURST_LENGTH_SHIFT) +# define EMC_DYNMODE_BURST_LENGTH_2 (1 << EMC_DYNMODE_BURST_LENGTH_SHIFT) +# define EMC_DYNMODE_BURST_LENGTH_4 (2 << EMC_DYNMODE_BURST_LENGTH_SHIFT) +# define EMC_DYNMODE_BURST_LENGTH_8 (3 << EMC_DYNMODE_BURST_LENGTH_SHIFT) + /* Bit 3: Burst mode type */ +#define EMC_DYNMODE_BURST_TYPE_SHIFT (3) +# define EMC_DYNMODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYNMODE_BURST_TYPE_SHIFT) /* burst type sequential */ +# define EMC_DYNMODE_BURST_TYPE_INTERLEAVED (1 << EMC_DYNMODE_BURST_TYPE_INTERLEAVED) /* burst type interleaved */ + /* Bits 4-6: Latency mode. All other values are reserved. */ +#define EMC_DYNMODE_CAS_SHIFT (4) +#define EMC_DYNMODE_CAS_MASK (0x7) +# define EMC_DYNMODE_CAS_2 (2 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 2 cycles */ +# define EMC_DYNMODE_CAS_3 (3 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 3 cycles */ + /* Bits 7-8: Operating mode. All other values are reserved. */ +#define EMC_DYNMODE_OPMODE_SHIFT (7) +#define EMC_DYNMODE_OPMODE_MASK (0x3) +# define EMC_DYNMODE_OPMODE_STANDARD (0 << EMC_DYNMODE_OPMODE_SHIFT) /* dynamic standard operation mode */ + /* Bit 9: Write burst mode */ +#define EMC_DYNMODE_WBMODE_SHIFT (9) +# define EMC_DYNMODE_WBMODE_PROGRAMMED (0 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode programmed */ +# define EMC_DYNMODE_WBMODE_SINGLE_LOC (1 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode single loc */ + /* Bits 10-11: Reserved */ + /* Static Memory Configuration registers */ #define EMC_STATCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */ diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c index 70a0bbe5873..84b918051fe 100644 --- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c +++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_allocateheap.c * - * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -61,6 +61,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Get customizations for each supported chip. * * SRAM Resources @@ -95,6 +96,25 @@ * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM * banks but are treated as two banks of 48 an 16Kb by the NuttX memory * manager. This gives some symmetry to all of the members of the family. + * + * ---------------------------------------------------------------------- + * EMC SDRAM + * ---------------------------------------------------------------------- + * LPC43xx may have dynamic RAM connected on EMC bus. Up to 4 chips can be + * connected. + * + * DYCS0 (0x2800 0000) up to 128MB + * DYCS1 (0x3000 0000) up to 256MB + * DYCS2 (0x6000 0000) up to 256MB + * DYCS3 (0x7000 0000) up to 256MB + * + * LPC43xx may have static RAM connected on EMC bus. + * + * CS0 (0x1C00 0000) up to 16MB + * CS1 (0x1D00 0000) up to 16MB + * CS2 (0x1E00 0000) up to 16MB + * CS3 (0x1F00 0000) up to 16MB + * */ /* Configuration ************************************************************/ @@ -136,58 +156,88 @@ * * CONFIG_RAM_START = The start of the data RAM region which may be * either local SRAM bank 0 (Configuration A) or 1 (Configuration B). - * CONFIG_RAM_START = The size of the data RAM region. - * CONFIG_RAM_END = The sum of the above + * CONFIG_RAM_SIZE = The size of the data RAM region. + * CONFIG_RAM_END = The sum of the above. + */ + +/* External Memory Configuration + * + * Dynamic memory configuration + * For dynamic memory configuration at least one of LPC43_EXTSDRAMx + * should by defined. + * Also, together with LPC43_EXTSDRAMx should be defined: + * LPC43_EXTSDRAMxSIZE = External RAM size in bytes. + * LPC43_EXTSDRAMxHEAP = Should this RAM be use as heap space? */ /* Check for Configuration A. */ +#undef MM_USE_LOCSRAM_BANK0 +#undef MM_USE_LOCSRAM_BANK1 +#undef MM_USE_AHBSRAM_BANK0 +#undef MM_USE_AHBSRAM_BANK1 +#undef MM_USE_AHBSRAM_BANK2 +#undef MM_USE_EXTSDRAM0 +#undef MM_USE_EXTSDRAM1 +#undef MM_USE_EXTSDRAM2 +#undef MM_USE_EXTSDRAM3 + #ifndef CONFIG_LPC43_BOOT_SRAM /* Configuration A */ -/* CONFIG_RAM_START should be set to the base of AHB SRAM, local 0. */ +/* CONFIG_RAM_START shoudl be set to the base of local SRAM, Bank 0. */ # if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE -# error "CONFIG_RAM_START must be set to the base address of RAM Bank 0" +# error "CONFIG_RAM_START must be set to the base address of RAM bank 0" # endif -/* The configured RAM size should be equal to the size of local SRAM Bank 0 */ +/* The configured RAM size should be equal to the size of local SRAM Bank 0. */ # if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE -# error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 0" +# error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 0" # endif -/* Now we can assign all of the memory regions for configuration A */ +/* Local SRAM Bank 0 will be used as main memory region */ -# define MM_REGION1_BASE LPC43_LOCSRAM_BANK0_BASE -# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK0_SIZE -# define MM_REGION2_BASE LPC43_LOCSRAM_BANK1_BASE -# define MM_REGION2_SIZE LPC43_LOCSRAM_BANK1_SIZE -# define MM_REGION3_BASE LPC43_AHBSRAM_BANK0_BASE -# define MM_REGION3_SIZE LPC43_AHBSRAM_BANK0_SIZE -#else +# define MM_USE_LOCSRAM_BANK0 0 + +/* Use local SRAM Bank 1 if configured */ + +# ifdef CONFIG_LPC43_USE_LOCSRAM_BANK1 +# define MM_USE_LOCSRAM_BANK1 1 +# endif + +#else /* CONFIG_LPC43_BOOT_SRAM */ /* Configuration B */ -/* CONFIG_RAM_START should be set to the base of local SRAM, bank 1. */ +/* CONFIG_RAM_START should be set to the base of local SRAM, Bank 1. */ # if CONFIG_RAM_START != LPC43_LOCSRAM_BANK1_BASE -# error "CONFIG_RAM_START must be set to the base address of SRAM Bank 1" +# error "CONFIG_RAM_START must be set to the base address of RAM bank 1" # endif -/* The configured RAM size should be equal to the size of local SRAM Bank 1 */ +/* The configured RAM size should be equal to the size of local SRAM Bank 1. */ # if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE -# error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 1" +# error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 1" # endif -/* Now we can assign all of the memory regions for configuration B */ +/* Shouldn't use Local SRAM Bank 0 as system use it for code. + * Local SRAM Bank1 is used as main memory region. + */ -# define MM_REGION1_BASE LPC43_LOCSRAM_BANK1_BASE -# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK1_SIZE -# define MM_REGION2_BASE LPC43_AHBSRAM_BANK0_BASE -# define MM_REGION2_SIZE LPC43_AHBSRAM_BANK0_SIZE -# undef MM_REGION3_BASE -# undef MM_REGION3_SIZE +# define MM_USE_LOCSRAM_BANK1 0 + +#endif /* CONFIG_LPC43_BOOT_SRAM */ + +/* Configure other memory banks */ + +#ifdef CONFIG_LPC43_AHBSRAM_BANK0 +# define MM_USE_AHBSRAM_BANK0 1 +#endif + +#ifdef CONFIG_LPC43_AHBSRAM_BANK1 +# define MM_USE_AHBSRAM_BANK1 1 #endif #define MM_DMAREGION_BASE LPC43_AHBSRAM_BANK2_BASE @@ -199,8 +249,61 @@ #warning "Missing Logic" -#define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */ -#define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE +#ifdef CONFIG_LPC43_AHBSRAM_BANK2 +# define MM_USE_AHBSRAM_BANK2 1 +# define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */ +# define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE +#endif + +/* External RAM configuration */ + +/* Check if external SDRAM is supported and, if so, it is intended to be used + * used as heap. + */ + +#if !defined(CONFIG_LPC43_EXTSDRAM0) || !defined(CONFIG_LPC43_EXTSDRAM0_HEAP) +# undef CONFIG_LPC43_EXTSDRAM0_SIZE +# define CONFIG_LPC43_EXTSDRAM0_SIZE 0 +#endif + +#if !defined(CONFIG_LPC43_EXTSDRAM1) || !defined(CONFIG_LPC43_EXTSDRAM1_HEAP) +# undef CONFIG_LPC43_EXTSDRAM1_SIZE +# define CONFIG_LPC43_EXTSDRAM1_SIZE 0 +#endif + +#if !defined(CONFIG_LPC43_EXTSDRAM2) || !defined(CONFIG_LPC43_EXTSDRAM2_HEAP) +# undef CONFIG_LPC43_EXTSDRAM2_SIZE +# define CONFIG_LPC43_EXTSDRAM2_SIZE 0 +#endif + +#if !defined(CONFIG_LPC43_EXTSDRAM3) || !defined(CONFIG_LPC43_EXTSDRAM3_HEAP) +# undef CONFIG_LPC43_EXTSDRAM3_SIZE +# define CONFIG_LPC43_EXTSDRAM3_SIZE 0 +#endif + +#if CONFIG_LPC43_EXTSDRAM0_SIZE > 0 +# define MM_USE_EXTSDRAM0 1 +# define MM_EXTSDRAM0_REGION LPC43_DYCS0_BASE +# define MM_EXTSDRAM0_SIZE CONFIG_LPC43_EXTSDRAM0_SIZE +#endif /* CONFIG_LPC43_EXTSDRAM0_SIZE */ + +#if CONFIG_LPC43_EXTSDRAM1_SIZE > 0 +# define MM_USE_EXTSDRAM1 1 +# define MM_EXTSDRAM1_REGION LPC43_DYCS1_BASE +# define MM_EXTSDRAM1_SIZE CONFIG_LPC43_EXTSDRAM1_SIZE +#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */ + +#if CONFIG_LPC43_EXTSDRAM2_SIZE > 0 +# define MM_USE_EXTSDRAM2 1 +# define MM_EXTSDRAM2_REGION LPC43_DYCS2_BASE +# define MM_EXTSDRAM2_SIZE CONFIG_LPC43_EXTSDRAM2_SIZE +#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */ + +#if CONFIG_LPC43_EXTSDRAM3_SIZE > 0 +# define HAVE_EXTSDRAM3_REGION 1 +# define MM_EXTSDRAM3_REGION LPC43_DYCS3_BASE +# define MM_EXTSDRAM3_SIZE CONFIG_LPC43_EXTSDRAM3_SIZE +#endif /* CONFIG_LPC43_EXTSDRAM3_SIZE */ /**************************************************************************** * Private Data @@ -216,15 +319,26 @@ * thread is the thread that the system boots on and, eventually, becomes the * idle, do nothing task that runs only when there is nothing else to run. * The heap continues from there until the configured end of memory. - * g_idle_topstack is the beginning of this heap region (not necessarily aligned). + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). */ const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; +static uint32_t mem_region_next = 0; /**************************************************************************** * Private Functions ****************************************************************************/ +static void mem_addregion(FAR void *region_start, size_t region_size) +{ + if (mem_region_next <= CONFIG_MM_REGIONS) + { + kmm_addregion(region_start, region_size); + mem_region_next++; + } +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -266,34 +380,43 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) void up_addregion(void) { #if CONFIG_MM_REGIONS > 1 - /* Add the next SRAM region (which should exist) */ - kmm_addregion((FAR void *)MM_REGION2_BASE, MM_REGION2_SIZE); + /* start from second region */ -#ifdef MM_REGION3_BASE - /* Add the third SRAM region (which will not exist in configuration B) */ + mem_region_next = 2; -#if CONFIG_MM_REGIONS > 2 - /* Add the third SRAM region (which may not exist) */ +# ifdef MM_USE_LOCSRAM_BANK1 + mem_addregion((FAR void *)LPC43_LOCSRAM_BANK1_BASE, LPC43_LOCSRAM_BANK1_SIZE); +# endif - kmm_addregion((FAR void *)MM_REGION3_BASE, MM_REGION3_SIZE); +# ifdef MM_USE_AHBSRAM_BANK0 + mem_addregion((FAR void *)LPC43_AHBSRAM_BANK0_BASE, LPC43_AHBSRAM_BANK0_SIZE); +# endif -#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) - /* Add the DMA region (which may not be available) */ +# ifdef MM_USE_AHBSRAM_BANK1 + mem_addregion((FAR void *)LPC43_AHBSRAM_BANK1_BASE, LPC43_AHBSRAM_BANK1_SIZE); +# endif - kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); +# ifdef MM_USE_AHBSRAM_BANK2 + mem_addregion((FAR void *)MM_DMAREGION_BASE, MM_DMAREGION_SIZE); +# endif -#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ -#endif /* CONFIG_MM_REGIONS > 2 */ -#else /* MM_REGION3_BASE */ +# ifdef MM_USE_EXTSDRAM0 + mem_addregion((FAR void *)MM_EXTSDRAM0_REGION, MM_EXTSDRAM0_SIZE); +# endif -#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE) - /* Add the DMA region (which may not be available) */ +# ifdef MM_USE_EXTSDRAM1 + mem_addregion((FAR void *)MM_EXTSDRAM1_REGION, MM_EXTSDRAM1_SIZE); +# endif - kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); +# ifdef MM_USE_EXTSDRAM2 + mem_addregion((FAR void *)MM_EXTSDRAM2_REGION, MM_EXTSDRAM2_SIZE); +# endif + +# ifdef MM_USE_EXTSDRAM3 + mem_addregion((FAR void *)MM_EXTSDRAM3_REGION, MM_EXTSDRAM3_SIZE); +# endif -#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ -#endif /* MM_REGION3_BASE */ #endif /* CONFIG_MM_REGIONS > 1 */ } #endif diff --git a/arch/arm/src/lpc43xx/lpc43_emc.c b/arch/arm/src/lpc43xx/lpc43_emc.c new file mode 100644 index 00000000000..a15ecb5610d --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_emc.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_emc.c + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + + +/* TODO: add #if defined(CONFIG_LPC43_EMC) */ + +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include + +#include "up_internal.h" + +#include "chip.h" +#include "lpc43_pinconfig.h" +#include "lpc43_emc.h" +#include "chip/lpc43_creg.h" +#include "chip/lpc43_cgu.h" +#include "chip/lpc43_ccu.h" +#include "lpc43_rgu.h" +#include "lpc43_gpio.h" +#include "up_arch.h" +#include + + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_emcinit + * + * Description: + * Initialize EMC controller. Start in full power + * mode. + * + ****************************************************************************/ +void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode) +{ + uint32_t regval; + + /* Enable clock for EMC controller. */ + + regval = getreg32(LPC43_CCU1_M4_EMC_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_EMC_CFG); + + /* Configure endian mode and clock ratio. */ + + regval = 0; + if (endian_mode) + regval |= EMC_CONFIG_EM; + if (clock_ratio) + regval |= EMC_CONFIG_CR; + + putreg32(regval, LPC43_EMC_CONFIG); + + /* Enable EMC 001 normal memory map, no low power mode. */ + + putreg32(EMC_CONTROL_ENA, LPC43_EMC_CONTROL); +} + +/**************************************************************************** + * Name: lpc43_lowpowermode + * + * Description: + * Set EMC lowpower mode. + * + ****************************************************************************/ +void lpc43_lowpowermode(uint8_t enable) +{ + uint32_t regval; + + regval = getreg32(LPC43_EMC_CONTROL); + if (enable) + { + regval |= EMC_CONTROL_LOWPOWER; + putreg32(regval, LPC43_EMC_CONTROL); + } + else + { + regval &= ~EMC_CONTROL_LOWPOWER; + putreg32(regval, LPC43_EMC_CONTROL); + } +} + +/**************************************************************************** + * Name: lpc43_emcenable + * + * Description: + * Enable or disable EMC controller. + * + ****************************************************************************/ +void lpc43_emcenable(uint8_t enable) +{ + uint32_t regval; + + regval = getreg32(LPC43_EMC_CONTROL); + if (enable) + { + regval |= EMC_CONTROL_ENA; + putreg32(regval, LPC43_EMC_CONTROL); + } + else + { + regval &= ~EMC_CONTROL_ENA; + putreg32(regval, LPC43_EMC_CONTROL); + } +} diff --git a/arch/arm/src/lpc43xx/lpc43_emc.h b/arch/arm/src/lpc43xx/lpc43_emc.h index 3c2bd2496fe..77b71d86120 100644 --- a/arch/arm/src/lpc43xx/lpc43_emc.h +++ b/arch/arm/src/lpc43xx/lpc43_emc.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc43xx/lpc43_emc.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,16 +48,22 @@ * Pre-processor Definitions ************************************************************************************/ -/************************************************************************************ - * Public Types - ************************************************************************************/ +/* Chip select Definitions **********************************************************/ + +#define EMC_CS0 0 +#define EMC_CS1 1 +#define EMC_CS2 2 +#define EMC_CS3 3 + +#define EMC_DYNCS0 0 +#define EMC_DYNCS1 1 +#define EMC_DYNCS2 2 +#define EMC_DYNCS3 3 /************************************************************************************ - * Public Data + * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode); #endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H */