diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
index 8939f301b3e..f60ab4771bf 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
@@ -247,7 +247,7 @@
 #  define ETH_MACQTXFCR_PLT_M256        (4 << ETH_MACQTXFCR_PLT_SHIFT) /* 100 PT - 256 slot times */
 #  define ETH_MACQTXFCR_PLT_M512        (5 << ETH_MACQTXFCR_PLT_SHIFT) /* 101 PT - 512 slot times */
 #define ETH_MACQTXFCR_DZPQ              (1 << 7)  /* Bit 7: Zero-quanta pause disable */
-#define ETH_MACQTXFCR_PT_SHIFT          (4)       /* Bits 16-31: Pause Time */
+#define ETH_MACQTXFCR_PT_SHIFT          (16)      /* Bits 16-31: Pause Time */
 #define ETH_MACQTXFCR_PT_MASK           (0xFFFF << ETH_MACQTXFCR_PT_SHIFT)
 #define ETH_MACQTXFCR_PT(n)             ((uint32_t)(n) << ETH_MACQTXFCR_PT_SHIFT)
 
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
index 04c4e7d95af..7c1f575a863 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
@@ -130,7 +130,7 @@
 #define DMAMUX1_CRYPT_IN       (76)
 #define DMAMUX1_CRYPT_OUT      (77)
 #define DMAMUX1_HASH_IN        (78)
-#define DMAMUX1_UART7_RX       (70)
+#define DMAMUX1_UART7_RX       (79)
 #define DMAMUX1_UART7_TX       (80)
 #define DMAMUX1_UART8_RX       (81)
 #define DMAMUX1_UART8_TX       (82)
@@ -406,14 +406,14 @@
 #define DMAMAP_DMA12_CRYPTOOUT_1   DMAMAP_MAP(DMA2, DMAMUX1_CRYPTO_OUT)
 #define DMAMAP_DMA12_HASHIN_0      DMAMAP_MAP(DMA1, DMAMUX1_HASH_IN)
 #define DMAMAP_DMA12_HASHIN_1      DMAMAP_MAP(DMA2, DMAMUX1_HASH_IN)
-#define DMAMAP_DMA12_USART7RX_0    DMAMAP_MAP(DMA1, DMAMUX1_USART7_RX)
-#define DMAMAP_DMA12_USART7RX_1    DMAMAP_MAP(DMA2, DMAMUX1_USART7_RX)
-#define DMAMAP_DMA12_USART7TX_0    DMAMAP_MAP(DMA1, DMAMUX1_USART7_TX)
-#define DMAMAP_DMA12_USART7TX_1    DMAMAP_MAP(DMA2, DMAMUX1_USART7_TX)
-#define DMAMAP_DMA12_USART8RX_0    DMAMAP_MAP(DMA1, DMAMUX1_USART8_RX)
-#define DMAMAP_DMA12_USART8RX_1    DMAMAP_MAP(DMA2, DMAMUX1_USART8_RX)
-#define DMAMAP_DMA12_USART8TX_0    DMAMAP_MAP(DMA1, DMAMUX1_USART8_TX)
-#define DMAMAP_DMA12_USART8TX_1    DMAMAP_MAP(DMA2, DMAMUX1_USART8_TX)
+#define DMAMAP_DMA12_UART7RX_0     DMAMAP_MAP(DMA1, DMAMUX1_UART7_RX)
+#define DMAMAP_DMA12_UART7RX_1     DMAMAP_MAP(DMA2, DMAMUX1_UART7_RX)
+#define DMAMAP_DMA12_UART7TX_0     DMAMAP_MAP(DMA1, DMAMUX1_UART7_TX)
+#define DMAMAP_DMA12_UART7TX_1     DMAMAP_MAP(DMA2, DMAMUX1_UART7_TX)
+#define DMAMAP_DMA12_UART8RX_0     DMAMAP_MAP(DMA1, DMAMUX1_UART8_RX)
+#define DMAMAP_DMA12_UART8RX_1     DMAMAP_MAP(DMA2, DMAMUX1_UART8_RX)
+#define DMAMAP_DMA12_UART8TX_0     DMAMAP_MAP(DMA1, DMAMUX1_UART8_TX)
+#define DMAMAP_DMA12_UART8TX_1     DMAMAP_MAP(DMA2, DMAMUX1_UART8_TX)
 #define DMAMAP_DMA12_SPI4RX_0      DMAMAP_MAP(DMA1, DMAMUX1_SPI4_RX)
 #define DMAMAP_DMA12_SPI4RX_1      DMAMAP_MAP(DMA2, DMAMUX1_SPI4_RX)
 #define DMAMAP_DMA12_SPI4TX_0      DMAMAP_MAP(DMA1, DMAMUX1_SPI4_TX)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
index dfb71287ed7..6e16c218200 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
@@ -776,8 +776,8 @@
 #define RCC_APB1LRSTR_HDMICECRST        (1 << 27)   /* RCC APB1LRSTR: HDMICECRST */
                                                     /* Bit 28: Reserved */
 #define RCC_APB1LRSTR_DAC1RST           (1 << 29)   /* RCC APB1LRSTR: DAC1RST */
-#define RCC_APB1LRSTR_USART7RST         (1 << 30)   /* RCC APB1LRSTR: USART7RST */
-#define RCC_APB1LRSTR_USART8RST         (1 << 31)   /* RCC APB1LRSTR: USART8RST */
+#define RCC_APB1LRSTR_UART7RST          (1 << 30)   /* RCC APB1LRSTR: UART7RST */
+#define RCC_APB1LRSTR_UART8RST          (1 << 31)   /* RCC APB1LRSTR: UART8RST */
 
 /* APB1 H peripheral reset register */
 
@@ -913,8 +913,8 @@
 #define RCC_APB1LENR_HDMICECEN          (1 << 27) /* RCC APB1LENR: HDMICECEN */
                                                   /* Bit 28: Reserved */
 #define RCC_APB1LENR_DAC1EN             (1 << 29) /* RCC APB1LENR: DAC1EN */
-#define RCC_APB1LENR_UART7EN            (1 << 30) /* RCC APB1LENR: USART7EN */
-#define RCC_APB1LENR_UART8EN            (1 << 31) /* RCC APB1LENR: USART8EN */
+#define RCC_APB1LENR_UART7EN            (1 << 30) /* RCC APB1LENR: UART7EN */
+#define RCC_APB1LENR_UART8EN            (1 << 31) /* RCC APB1LENR: UART8EN */
 
 /* APB1 H Peripheral Clock enable register */
 
@@ -1061,8 +1061,8 @@
 #define RCC_APB1LLPENR_I2C3LPEN         (1 << 23)      /* RCC APB1LLPENR: I2C3LPEN */
 #define RCC_APB1LLPENR_HDMICECLPEN      (1 << 27)      /* RCC APB1LLPENR: HDMICECLPEN */
 #define RCC_APB1LLPENR_DAC1LPEN         (1 << 29)      /* RCC APB1LLPENR: DAC1LPEN */
-#define RCC_APB1LLPENR_USART7LPEN       (1 << 30)      /* RCC APB1LLPENR: USART7LPEN */
-#define RCC_APB1LLPENR_USART8LPEN       (1 << 31)      /* RCC APB1LLPENR: USART8LPEN */
+#define RCC_APB1LLPENR_UART7LPEN        (1 << 30)      /* RCC APB1LLPENR: UART7LPEN */
+#define RCC_APB1LLPENR_UART8LPEN        (1 << 31)      /* RCC APB1LLPENR: UART8LPEN */
 
 
 /* APB1 H low power mode peripheral clock enable register */