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LPC43 board.h files: Settings needed in lpc43_cpu.c
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@@ -151,6 +151,13 @@
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#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY
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#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY
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/* USB0 ********************************************************************/
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/* Settings needed in lpc43_cpu.c */
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#define BOARD_USB0_CTL 0x0600081d
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#define BOARD_USB0_MDIV 0x06167ffa /* Table 149 datsheet */
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#define BOARD_USB0_NP_DIV 0x00302062 /* Table 149 datsheet */
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/* SPIFI clocking **********************************************************/
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/* SPIFI clocking **********************************************************/
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/* The SPIFI will receive clocking from a divider per the settings provided
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/* The SPIFI will receive clocking from a divider per the settings provided
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* in this file. The NuttX code will configure PLL1 as the input clock
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* in this file. The NuttX code will configure PLL1 as the input clock
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@@ -150,6 +150,13 @@
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#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY
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#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY
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/* USB0 ********************************************************************/
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/* Settings needed in lpc43_cpu.c */
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#define BOARD_USB0_CTL 0x0600081d
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#define BOARD_USB0_MDIV 0x06167ffa /* Table 149 datsheet */
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#define BOARD_USB0_NP_DIV 0x00302062 /* Table 149 datsheet */
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/* SPIFI clocking **********************************************************/
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/* SPIFI clocking **********************************************************/
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/* The SPIFI will receive clocking from a divider per the settings provided
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/* The SPIFI will receive clocking from a divider per the settings provided
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* in this file. The NuttX code will configure PLL1 as the input clock
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* in this file. The NuttX code will configure PLL1 as the input clock
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