diff --git a/arch/sh/src/m16c/m16c_initialstate.c b/arch/sh/src/m16c/m16c_initialstate.c index e4c55678858..1893672790a 100644 --- a/arch/sh/src/m16c/m16c_initialstate.c +++ b/arch/sh/src/m16c/m16c_initialstate.c @@ -40,7 +40,10 @@ #include #include #include + #include +#include + #include "up_internal.h" #include "up_arch.h" @@ -48,8 +51,6 @@ * Preprocessor Definitions ****************************************************************************/ -#define M16C_DEFAULT_IPL 0 /* Default M16C Interrupt priority level */ - /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/sh/src/m16c/m16c_timerisr.c b/arch/sh/src/m16c/m16c_timerisr.c index 962166071be..3cc63271902 100644 --- a/arch/sh/src/m16c/m16c_timerisr.c +++ b/arch/sh/src/m16c/m16c_timerisr.c @@ -41,7 +41,9 @@ #include #include #include + #include +#include #include "clock_internal.h" #include "up_internal.h" diff --git a/arch/sh/src/m16c/m16c_vectors.S b/arch/sh/src/m16c/m16c_vectors.S index 2ffa50154d9..17f47f56039 100644 --- a/arch/sh/src/m16c/m16c_vectors.S +++ b/arch/sh/src/m16c/m16c_vectors.S @@ -346,6 +346,13 @@ _m16c_commonvector: fclr u /* Back to interrupt stack */ push.w r0 /* Save user sp on isp */ +/* Allow nested interrupts */ + +#ifdef M16C_INTERRUPT_IPL + fset i /* Enable interrupts */ + ldipl #M16C_INTERRUPT_IPL /* Set interrupt level */ +#endif + /* Then call _up_doirq with r1=IRQ number, r2=address of context info. At this * point, the interrupt stack holds the address of the last byte of the context * info array @@ -354,6 +361,10 @@ _m16c_commonvector: stc isp, r2 /* R2 = address of base of context info */ jsr.a _up_doirq +#ifdef M16C_INTERRUPT_IPL + fclr i /* Disable interrupts */ +#endif + /* Upon return, r0 will hold address of the base of the new context info structure * use for return. Most of the time this will be the same as the address passed to * to _up_doirg above, but will differ if a context switch occurs during interrupt