Remove the unneeded void cast

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

arch/arm/src/armv6-m/arm_svcall.c

@@ -261,7 +261,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg)
            */
 
           rtcb->flags          &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/arm/src/armv7-a/arm_syscall.c

@@ -239,7 +239,7 @@ uint32_t *arm_syscall(uint32_t *regs)
            */
 
           rtcb->flags          &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/arm/src/armv7-m/arm_svcall.c

@@ -275,7 +275,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg)
            */
 
           rtcb->flags          &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/arm/src/armv7-r/arm_syscall.c

@@ -236,7 +236,7 @@ uint32_t *arm_syscall(uint32_t *regs)
            */
 
           rtcb->flags          &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/arm/src/armv8-m/arm_svcall.c

@@ -274,7 +274,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg)
            */
 
           rtcb->flags          &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/arm/src/cxd56xx/cxd56_pwm.c

@@ -496,8 +496,6 @@ FAR struct pwm_lowerhalf_s *cxd56_pwminitialize(uint32_t channel)
 {
   FAR struct cxd56_pwm_chan_s *pwmch;
 
-  (void)g_pwmops;
-
   switch (channel)
     {
 #ifdef CONFIG_CXD56_PWM0

arch/arm/src/efm32/efm32_start.c

@@ -84,7 +84,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
 
 #ifdef CONFIG_DEBUG_FEATURES
 #  if defined(CONFIG_ARMV7M_ITMSYSLOG)
-#    define showprogress(c) (void)syslog_putc(c)
+#    define showprogress(c) syslog_putc(c)
 #  elif defined(HAVE_UART_CONSOLE) || defined(HAVE_LEUART_CONSOLE)
 #    define showprogress(c) efm32_lowputc(c)
 #  else

arch/arm/src/imxrt/imxrt_flexspi.c

@@ -581,7 +581,7 @@ void imxrt_flexspi_get_default_config(struct flexspi_config_s *config)
 {
   /* Initializes the configure structure to zero */
 
-  (void)memset(config, 0, sizeof(*config));
+  memset(config, 0, sizeof(*config));
 
   config->rx_sample_clock = FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_FROM_DQS_PAD;
   config->enable_sck_free_running     = false;
@@ -606,8 +606,8 @@ void imxrt_flexspi_get_default_config(struct flexspi_config_s *config)
   config->ahb_config.ahb_grant_timeout_cycle  = 0xff;
   config->ahb_config.ahb_bus_timeout_cycle    = 0xffff;
   config->ahb_config.resume_wait_cycle        = 0x20;
-  (void)memset(config->ahb_config.buffer, 0,
-               sizeof(config->ahb_config.buffer));
+  memset(config->ahb_config.buffer, 0,
+         sizeof(config->ahb_config.buffer));
 
   /* Use invalid master ID 0xF and buffer size 0 for the first several
    * buffers.

arch/arm/src/imxrt/imxrt_usdhc.c

@@ -1330,8 +1330,8 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
           mcinfo("Queuing callback to %p(%p)\n",
                  priv->callback, priv->cbarg);
 
-          (void)work_queue(HPWORK, &priv->cbwork, priv->callback,
-                          priv->cbarg, 0);
+          work_queue(HPWORK, &priv->cbwork, priv->callback,
+                     priv->cbarg, 0);
         }
       else
         {

arch/arm/src/phy62xx/uart.c

@@ -756,7 +756,7 @@ static int pplus_uart_interrupt(int irq, void *context, FAR void *arg)
           break;
 
       case BUSY_IRQ:
-         (void)priv->reg->USR;
+         priv->reg->USR;
          break;
 
       default:
@@ -1202,7 +1202,7 @@ static int h4uart_interrupt(int irq, void *context, FAR void *arg)
           break;
       case RLS_IRQ:
       case BUSY_IRQ:
-          (void)preg->USR;
+          preg->USR;
           break;
       default:
           break;

arch/arm/src/rtl8720c/ameba_uart.c

@@ -1051,19 +1051,19 @@ void arm_earlyserialinit(void)
 void arm_serialinit(void)
 {
 #ifdef CONSOLE_DEV
-  (void)uart_register("/dev/console", &CONSOLE_DEV);
+  uart_register("/dev/console", &CONSOLE_DEV);
 #endif
 #ifdef TTYS0_DEV
-  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+  uart_register("/dev/ttyS0", &TTYS0_DEV);
 #endif
 #ifdef TTYS1_DEV
-  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+  uart_register("/dev/ttyS1", &TTYS1_DEV);
 #endif
 #ifdef TTYS2_DEV
-  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+  uart_register("/dev/ttyS2", &TTYS2_DEV);
 #endif
 #ifdef TTYS3_DEV
-  (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+  uart_register("/dev/ttyS3", &TTYS3_DEV);
 #endif
 }
 

arch/arm/src/rtl8720c/ameba_wdt.c

@@ -286,8 +286,8 @@ void ameba_wdt_initialize(void)
   /* Initialize the driver state structure. */
 
   priv->ops = &g_wdgops;
-  (void)watchdog_register(CONFIG_WATCHDOG_DEVPATH,
-                          (FAR struct watchdog_lowerhalf_s *)priv);
+  watchdog_register(CONFIG_WATCHDOG_DEVPATH,
+                    (FAR struct watchdog_lowerhalf_s *)priv);
 }
 
 #endif /* CONFIG_WATCHDOG */

arch/arm/src/rtl8720c/amebaz_coex.c

@@ -86,12 +86,10 @@ static void rtk_notify_info_to_wifi(uint8_t length, uint8_t *report_info)
 }
 
 void bt_coex_handle_cmd_complete_evt(uint16_t opcode, uint16_t cause,
-                                              uint8_t total_len, uint8_t *p)
+                                     uint8_t total_len, uint8_t *p)
 {
-  (void)cause;
   if (opcode == HCI_VENDOR_MAILBOX_CMD)
     {
-      uint8_t status;
       status = *p++; /* jump the double subcmd */
 
       total_len--;
@@ -101,7 +99,6 @@ void bt_coex_handle_cmd_complete_evt(uint16_t opcode, uint16_t cause,
           return ;
         }
 
-      (void)status;
       rltk_coex_mailbox_to_wifi(p, total_len);
 
       /* rtk_parse_vendor_mailbox_cmd_evt(p, total_len, status); */
@@ -149,10 +146,10 @@ static void bt_coex_dump_buf(net_buf_simple *tmp_buf)
 
 static int bt_coex_unpack_xiaomi_vendor_cmd(net_buf_simple *tmp_buf)
 {
-  if (tmp_buf-> data[0] == 0x25 && tmp_buf-> data[1] == 0x00)
+  if (tmp_buf->data[0] == 0x25 && tmp_buf->data[1] == 0x00)
     {
-      tmp_buf -> data += 2;
-      tmp_buf -> len -= 2;
+      tmp_buf->data += 2;
+      tmp_buf->len -= 2;
       return 1;
     }
 

arch/arm/src/sam34/sam_gpioirq.c

@@ -433,7 +433,7 @@ void sam_gpioirqenable(int irq)
     {
       /* Clear (all) pending interrupts and enable this pin interrupt */
 
-      /* (void)getreg32(base + SAM_PIO_ISR_OFFSET); */
+      /* getreg32(base + SAM_PIO_ISR_OFFSET); */
 
       putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
     }

arch/arm/src/sama5/sam_pioirq.c

@@ -479,7 +479,7 @@ void sam_pioirqenable(int irq)
     {
       /* Clear (all) pending interrupts and enable this pin interrupt */
 
-      (void)getreg32(base + SAM_PIO_ISR_OFFSET);
+      getreg32(base + SAM_PIO_ISR_OFFSET);
       putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
     }
 }

arch/arm/src/sama5/sam_sdmmc.c

@@ -1427,8 +1427,8 @@ static int sam_interrupt(int irq, void *context, FAR void *arg)
 
           mcinfo("Queuing callback to %p(%p)\n", priv->callback,
                   priv->cbarg);
-          (void)work_queue(HPWORK, &priv->cbwork, priv->callback,
-                          priv->cbarg, 0);
+          work_queue(HPWORK, &priv->cbwork, priv->callback,
+                     priv->cbarg, 0);
         }
       else
         {

arch/arm/src/samd5e5/sam_oneshot.c

@@ -221,7 +221,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
       /* Yes.. then cancel it */
 
       tmrinfo("Already running... cancelling\n");
-      (void)sam_oneshot_cancel(oneshot, freerun, NULL);
+      sam_oneshot_cancel(oneshot, freerun, NULL);
     }
 
   /* Save the new handler and its argument */

arch/arm/src/samd5e5/sam_progmem.c

@@ -541,7 +541,7 @@ ssize_t up_progmem_eraseblock(size_t cluster)
   /* Erase all pages in the cluster */
 
 #ifdef USE_UNLOCK
-  (void)nvm_unlock(page, SAMD5E5_PAGE_PER_CLUSTER);
+  nvm_unlock(page, SAMD5E5_PAGE_PER_CLUSTER);
 #endif
 
   finfo("INFO: erase block=%d address=0x%x\n",
@@ -549,7 +549,7 @@ ssize_t up_progmem_eraseblock(size_t cluster)
   ret = nvm_command(NVMCTRL_CTRLB_CMD_EB, SAMD5E5_PAGE2BYTE(page));
 
 #ifdef USE_LOCK
-  (void)nvm_lock(page, SAMD5E5_PAGE_PER_CLUSTER);
+  nvm_lock(page, SAMD5E5_PAGE_PER_CLUSTER);
 #endif
 
   if (ret < 0)
@@ -698,7 +698,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen)
 #ifdef USE_UNLOCK /* Make sure that the FLASH is unlocked */
   lock = page;
   locksize = SAMD5E5_BYTE2PAGE(buflen);
-  (void)nvm_unlock(lock, locksize);
+  nvm_unlock(lock, locksize);
 #endif
 
   flags = enter_critical_section();
@@ -860,7 +860,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen)
     }
 
 #ifdef USE_LOCK
-  (void)nvm_lock(lock, locksize);
+  nvm_lock(lock, locksize);
 #endif
 
   leave_critical_section(flags);

arch/arm/src/samd5e5/sam_tc.c

@@ -657,7 +657,7 @@ TC_HANDLE sam_tc_allocate(int tc, int frequency)
       /* Initialize the TC driver structure */
 
       priv->flags = 0;
-      (void)nxsem_init(&priv->exclsem, 0, 1);
+      nxsem_init(&priv->exclsem, 0, 1);
 
       /* Enable clocking to the TC module in PCHCTRL */
 

arch/arm/src/samd5e5/sam_timerisr.c

@@ -113,7 +113,7 @@ void up_timer_initialize(void)
 
   /* Attach the timer interrupt vector */
 
-  (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL);
+  irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL);
 
   /* Enable SysTick interrupts using the processor clock source. */
 

arch/arm/src/samd5e5/sam_wdt.c

@@ -457,7 +457,7 @@ void sam_wdt_initialize(FAR const char *devpath)
   priv->started = false;
   sam_settimeout((FAR struct watchdog_lowerhalf_s *)priv,
                   BOARD_SCLK_FREQUENCY / 2);
-  (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+  watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
 }
 
 #endif /* CONFIG_WATCHDOG && CONFIG__WDT */

arch/arm/src/samv7/sam_gpioirq.c

@@ -389,7 +389,7 @@ void sam_gpioirqenable(int irq)
     {
       /* Clear (all) pending interrupts and enable this pin interrupt */
 
-      /* (void)getreg32(base + SAM_PIO_ISR_OFFSET); */
+      /* getreg32(base + SAM_PIO_ISR_OFFSET); */
 
       putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
     }

arch/arm/src/stm32h7/stm32_qspi.c

@@ -497,10 +497,11 @@ static inline void qspi_putreg(struct stm32h7_qspidev_s *priv,
 #ifdef CONFIG_DEBUG_SPI_INFO
 static void qspi_dumpregs(struct stm32h7_qspidev_s *priv, const char *msg)
 {
-  uint32_t regval;
   spiinfo("%s:\n", msg);
 
 #if 0
+  uint32_t regval;
+
   /* this extra verbose output may be helpful in some cases; you'll need
    * to make sure your syslog is large enough to accommodate extra output.
    */
@@ -575,7 +576,6 @@ static void qspi_dumpregs(struct stm32h7_qspidev_s *priv, const char *msg)
   spiinfo("   PIR:%08x  LPTR:%08x\n",
           getreg32(priv->base + STM32_QUADSPI_PIR_OFFSET),    /* Polling Interval Register */
           getreg32(priv->base + STM32_QUADSPI_LPTR_OFFSET));  /* Low-Power Timeout Register */
-  (void)regval;
 #endif
 }
 #endif

arch/arm/src/stm32h7/stm32_spi_slave.c

@@ -921,7 +921,7 @@ static int spi_lock(FAR struct spi_slave_ctrlr_s *ctrlr, bool lock)
     }
   else
     {
-      (void)nxsem_post(&priv->exclsem);
+      nxsem_post(&priv->exclsem);
       ret = OK;
     }
 
@@ -1156,8 +1156,8 @@ static void spi_bind(struct spi_slave_ctrlr_s *ctrlr,
 
   /* Bind to NSS interrupt */
 
-  (void)stm32_gpiosetevent(priv->nss_pin, false, true, false,
-                           spi_nssinterrupt, priv);
+  stm32_gpiosetevent(priv->nss_pin, false, true, false,
+                     spi_nssinterrupt, priv);
 
 #ifdef CONFIG_PM
   /* Register to receive power management callbacks */
@@ -1196,15 +1196,15 @@ static int spi_nssinterrupt(int irq, void *context, void *arg)
     {
       /* Bind to NSS rising edge interrupt */
 
-      (void)stm32_gpiosetevent(priv->nss_pin, true, false, false,
-                               spi_nssinterrupt, priv);
+      stm32_gpiosetevent(priv->nss_pin, true, false, false,
+                         spi_nssinterrupt, priv);
       return OK;
     }
 
   /* Disable NSS interrupt */
 
-  (void)stm32_gpiosetevent(priv->nss_pin, false, false, false,
-                           NULL, priv);
+  stm32_gpiosetevent(priv->nss_pin, false, false, false,
+                     NULL, priv);
 
   /* Re-configure nss pin */
 

arch/arm/src/stm32l5/stm32l5_irq.c

@@ -141,7 +141,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq)
 #ifdef CONFIG_DEBUG_FEATURES
 static int stm32l5_nmi(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! NMI received\n");
   PANIC();
   return 0;
@@ -149,7 +149,7 @@ static int stm32l5_nmi(int irq, FAR void *context, FAR void *arg)
 
 static int stm32l5_busfault(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
   PANIC();
   return 0;
@@ -157,7 +157,7 @@ static int stm32l5_busfault(int irq, FAR void *context, FAR void *arg)
 
 static int stm32l5_usagefault(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
   PANIC();
   return 0;
@@ -165,7 +165,7 @@ static int stm32l5_usagefault(int irq, FAR void *context, FAR void *arg)
 
 static int stm32l5_pendsv(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! PendSV received\n");
   PANIC();
   return 0;
@@ -173,7 +173,7 @@ static int stm32l5_pendsv(int irq, FAR void *context, FAR void *arg)
 
 static int stm32l5_dbgmonitor(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
   PANIC();
   return 0;
@@ -181,7 +181,7 @@ static int stm32l5_dbgmonitor(int irq, FAR void *context, FAR void *arg)
 
 static int stm32l5_reserved(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Reserved interrupt\n");
   PANIC();
   return 0;

arch/arm/src/stm32l5/stm32l5_lse.c

@@ -181,6 +181,6 @@ void stm32l5_rcc_enablelse(void)
 
       /* Disable backup domain access if it was disabled on entry */
 
-      (void)stm32l5_pwr_enablebkp(writable);
+      stm32l5_pwr_enablebkp(writable);
     }
 }

arch/arm/src/stm32l5/stm32l5_rcc.c

@@ -102,7 +102,7 @@ static inline void rcc_resetbkp(void)
        * backup data registers and backup SRAM).
        */
 
-      (void)stm32l5_pwr_enablebkp(true);
+      stm32l5_pwr_enablebkp(true);
 
       /* We might be changing RTCSEL - to ensure such changes work, we must
        * reset the backup domain (having backed up the RTC_MAGIC token)
@@ -123,7 +123,7 @@ static inline void rcc_resetbkp(void)
           putreg32(bkregs[i], STM32L5_RTC_BKR(i));
         }
 
-      (void)stm32l5_pwr_enablebkp(false);
+      stm32l5_pwr_enablebkp(false);
     }
 }
 #else

arch/arm/src/stm32l5/stm32l5_serial.c

@@ -1209,7 +1209,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend)
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
           if (priv->iflow)
             {
-              (void)stm32l5serial_dmaiflowrestart(priv);
+              stm32l5serial_dmaiflowrestart(priv);
             }
           else
 #endif
@@ -2644,7 +2644,7 @@ static void stm32l5serial_dmarxint(FAR struct uart_dev_s *dev, bool enable)
     {
       /* Re-enable RX DMA. */
 
-      (void)stm32l5serial_dmaiflowrestart(priv);
+      stm32l5serial_dmaiflowrestart(priv);
     }
 #endif
 }
@@ -2805,7 +2805,7 @@ static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status,
         {
           /* Re-enable RX DMA. */
 
-          (void)stm32l5serial_dmaiflowrestart(priv);
+          stm32l5serial_dmaiflowrestart(priv);
         }
 #endif
     }
@@ -3076,14 +3076,14 @@ void arm_serialinit(void)
   /* Register the console */
 
 #if CONSOLE_UART > 0
-  (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
+  uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
 
 #ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING
   /* If not disabled, register the console UART to ttyS0 and exclude
    * it from initializing it further down
    */
 
-  (void)uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev);
+  uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev);
   minor = 1;
 #endif
 
@@ -3119,7 +3119,7 @@ void arm_serialinit(void)
       /* Register USARTs as devices in increasing order */
 
       devname[9] = '0' + minor++;
-      (void)uart_register(devname, &g_uart_devs[i]->dev);
+      uart_register(devname, &g_uart_devs[i]->dev);
     }
 #endif /* HAVE UART */
 }

arch/arm/src/stm32l5/stm32l5_spi.c

@@ -689,7 +689,7 @@ static void spi_dmatxwait(FAR struct stm32l5_spidev_s *priv)
 #ifdef CONFIG_STM32L5_SPI_DMA
 static inline void spi_dmarxwakeup(FAR struct stm32l5_spidev_s *priv)
 {
-  (void)nxsem_post(&priv->rxsem);
+  nxsem_post(&priv->rxsem);
 }
 #endif
 
@@ -704,7 +704,7 @@ static inline void spi_dmarxwakeup(FAR struct stm32l5_spidev_s *priv)
 #ifdef CONFIG_STM32L5_SPI_DMA
 static inline void spi_dmatxwakeup(FAR struct stm32l5_spidev_s *priv)
 {
-  (void)nxsem_post(&priv->txsem);
+  nxsem_post(&priv->txsem);
 }
 #endif
 
@@ -953,7 +953,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
     }
   else
     {
-      (void)nxsem_post(&priv->exclsem);
+      nxsem_post(&priv->exclsem);
       ret = OK;
     }
 

arch/arm/src/stm32l5/stm32l5_timerisr.c

@@ -134,7 +134,7 @@ void up_timer_initialize(void)
 
   /* Attach the timer interrupt vector */
 
-  (void)irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL);
+  irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL);
 
   /* Enable SysTick interrupts */
 

arch/arm/src/stm32u5/stm32_irq.c

@@ -141,7 +141,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
 #ifdef CONFIG_DEBUG_FEATURES
 static int stm32_nmi(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! NMI received\n");
   PANIC();
   return 0;
@@ -149,7 +149,7 @@ static int stm32_nmi(int irq, FAR void *context, FAR void *arg)
 
 static int stm32_busfault(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
   PANIC();
   return 0;
@@ -157,7 +157,7 @@ static int stm32_busfault(int irq, FAR void *context, FAR void *arg)
 
 static int stm32_usagefault(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
   PANIC();
   return 0;
@@ -165,7 +165,7 @@ static int stm32_usagefault(int irq, FAR void *context, FAR void *arg)
 
 static int stm32_pendsv(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! PendSV received\n");
   PANIC();
   return 0;
@@ -173,7 +173,7 @@ static int stm32_pendsv(int irq, FAR void *context, FAR void *arg)
 
 static int stm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
   PANIC();
   return 0;
@@ -181,7 +181,7 @@ static int stm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
 
 static int stm32_reserved(int irq, FAR void *context, FAR void *arg)
 {
-  (void)up_irq_save();
+  up_irq_save();
   _err("PANIC!!! Reserved interrupt\n");
   PANIC();
   return 0;

arch/arm/src/stm32u5/stm32_lse.c

@@ -181,6 +181,6 @@ void stm32_rcc_enablelse(void)
 
       /* Disable backup domain access if it was disabled on entry */
 
-      (void)stm32_pwr_enablebkp(writable);
+      stm32_pwr_enablebkp(writable);
     }
 }

arch/arm/src/stm32u5/stm32_rcc.c

@@ -102,7 +102,7 @@ static inline void rcc_resetbkp(void)
        * backup data registers and backup SRAM).
        */
 
-      (void)stm32_pwr_enablebkp(true);
+      stm32_pwr_enablebkp(true);
 
       /* We might be changing RTCSEL - to ensure such changes work, we must
        * reset the backup domain (having backed up the RTC_MAGIC token)
@@ -123,7 +123,7 @@ static inline void rcc_resetbkp(void)
           putreg32(bkregs[i], STM32U5_RTC_BKR(i));
         }
 
-      (void)stm32_pwr_enablebkp(false);
+      stm32_pwr_enablebkp(false);
     }
 }
 #else

arch/arm/src/stm32u5/stm32_serial.c

@@ -1209,7 +1209,7 @@ static void stm32serial_setsuspend(struct uart_dev_s *dev, bool suspend)
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
           if (priv->iflow)
             {
-              (void)stm32serial_dmaiflowrestart(priv);
+              stm32serial_dmaiflowrestart(priv);
             }
           else
 #endif
@@ -2644,7 +2644,7 @@ static void stm32serial_dmarxint(FAR struct uart_dev_s *dev, bool enable)
     {
       /* Re-enable RX DMA. */
 
-      (void)stm32serial_dmaiflowrestart(priv);
+      stm32serial_dmaiflowrestart(priv);
     }
 #endif
 }
@@ -2804,7 +2804,7 @@ static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status,
         {
           /* Re-enable RX DMA. */
 
-          (void)stm32serial_dmaiflowrestart(priv);
+          stm32serial_dmaiflowrestart(priv);
         }
 #endif
     }
@@ -3075,14 +3075,14 @@ void arm_serialinit(void)
   /* Register the console */
 
 #if CONSOLE_UART > 0
-  (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
+  uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
 
 #ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING
   /* If not disabled, register the console UART to ttyS0 and exclude
    * it from initializing it further down
    */
 
-  (void)uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev);
+  uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev);
   minor = 1;
 #endif
 
@@ -3118,7 +3118,7 @@ void arm_serialinit(void)
       /* Register USARTs as devices in increasing order */
 
       devname[9] = '0' + minor++;
-      (void)uart_register(devname, &g_uart_devs[i]->dev);
+      uart_register(devname, &g_uart_devs[i]->dev);
     }
 #endif /* HAVE UART */
 }

arch/arm/src/stm32u5/stm32_timerisr.c

@@ -134,7 +134,7 @@ void up_timer_initialize(void)
 
   /* Attach the timer interrupt vector */
 
-  (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
+  irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
 
   /* Enable SysTick interrupts */
 

arch/avr/src/at90usb/at90usb_serial.c

@@ -232,7 +232,7 @@ static int usart1_attach(struct uart_dev_s *dev)
   irq_attach(AT90USB_IRQ_U1RX, usart1_rxinterrupt, NULL);
   irq_attach(AT90USB_IRQ_U1DRE, usart1_txinterrupt, NULL);
 
-  /* (void)irq_attach(AT90USB_IRQ_U1TX, usart1_txinterrupt, NULL); */
+  /* irq_attach(AT90USB_IRQ_U1TX, usart1_txinterrupt, NULL); */
 
   return OK;
 }
@@ -258,7 +258,7 @@ static void usart1_detach(struct uart_dev_s *dev)
   irq_detach(AT90USB_IRQ_U1RX);
   irq_detach(AT90USB_IRQ_U1DRE);
 
-  /* (void)irq_detach(AT90USB_IRQ_U1TX); */
+  /* irq_detach(AT90USB_IRQ_U1TX); */
 }
 
 /****************************************************************************

arch/avr/src/atmega/atmega_serial.c

@@ -371,7 +371,7 @@ static int usart0_attach(struct uart_dev_s *dev)
   irq_attach(ATMEGA_IRQ_U0RX, usart0_rxinterrupt, NULL);
   irq_attach(ATMEGA_IRQ_U0DRE, usart0_txinterrupt, NULL);
 
-  /* (void)irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt, NULL); */
+  /* irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt, NULL); */
 
   return OK;
 }
@@ -395,7 +395,7 @@ static int usart1_attach(struct uart_dev_s *dev)
   irq_attach(ATMEGA_IRQ_U1RX, usart1_rxinterrupt, NULL);
   irq_attach(ATMEGA_IRQ_U1DRE, usart1_txinterrupt, NULL);
 
-  /* (void)irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt, NULL); */
+  /* irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt, NULL); */
 
   return OK;
 }
@@ -423,7 +423,7 @@ static void usart0_detach(struct uart_dev_s *dev)
   irq_detach(ATMEGA_IRQ_U0RX);
   irq_detach(ATMEGA_IRQ_U0DRE);
 
-  /* (void)irq_detach(ATMEGA_IRQ_U0TX); */
+  /* irq_detach(ATMEGA_IRQ_U0TX); */
 }
 #endif
 
@@ -439,7 +439,7 @@ static void usart1_detach(struct uart_dev_s *dev)
   irq_detach(ATMEGA_IRQ_U1RX);
   irq_detach(ATMEGA_IRQ_U1DRE);
 
-  /* (void)irq_detach(ATMEGA_IRQ_U1TX); */
+  /* irq_detach(ATMEGA_IRQ_U1TX); */
 }
 #endif
 

arch/mips/include/syscall.h

@@ -163,7 +163,7 @@
  */
 
 #define SYS_syscall_return (3)
-#define up_syscall_return() (void)sys_call0(SYS_syscall_return)
+#define up_syscall_return() sys_call0(SYS_syscall_return)
 
 #endif
 #endif /* __ASSEMBLY__ */

arch/mips/src/mips32/mips_swint0.c

@@ -230,7 +230,7 @@ int up_swint0(int irq, void *context, void *arg)
            */
 
           rtcb->flags            &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/misoc/include/syscall.h

@@ -90,7 +90,7 @@
  */
 
 #define SYS_syscall_return (3)
-#define up_syscall_return() (void)sys_call0(SYS_syscall_return)
+#define up_syscall_return() sys_call0(SYS_syscall_return)
 
 #endif
 

arch/renesas/src/rx65n/rx65n_riic.c

@@ -2008,7 +2008,7 @@ static void rx65n_riic_pre_end_set(FAR struct rx65n_i2c_priv_s *priv)
       RIIC0.ICMR3.BIT.ACKBT = 1;
       RIIC0.ICMR3.BIT.ACKWP = 0;
 
-      (void)rx65n_getreg(RX65N_RIIC0_ICMR3);
+      rx65n_getreg(RX65N_RIIC0_ICMR3);
     }
 
   else if (1 == priv->bus)
@@ -2020,7 +2020,7 @@ static void rx65n_riic_pre_end_set(FAR struct rx65n_i2c_priv_s *priv)
       RIIC1.ICMR3.BIT.ACKBT = 1;
       RIIC1.ICMR3.BIT.ACKWP = 0;
 
-      (void)rx65n_getreg(RX65N_RIIC1_ICMR3);
+      rx65n_getreg(RX65N_RIIC1_ICMR3);
     }
 
   else
@@ -2032,7 +2032,7 @@ static void rx65n_riic_pre_end_set(FAR struct rx65n_i2c_priv_s *priv)
       RIIC2.ICMR3.BIT.ACKBT = 1;
       RIIC2.ICMR3.BIT.ACKWP = 0;
 
-      (void)rx65n_getreg(RX65N_RIIC2_ICMR3);
+      rx65n_getreg(RX65N_RIIC2_ICMR3);
     }
 }
 

arch/renesas/src/rx65n/rx65n_rtc.c

@@ -553,7 +553,7 @@ int rx65n_rtc_setdatetime(FAR const struct tm *tp)
    * seconds)
    */
 
-  /* (void)gmtime_r(&tp->tv_sec, &tp); */
+  /* gmtime_r(&tp->tv_sec, &tp); */
 
   rtc_dumptime(&tp, "Setting time");
 
@@ -706,7 +706,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
    * seconds)
    */
 
-  (void)gmtime_r(&tp->tv_sec, &newtime);
+  gmtime_r(&tp->tv_sec, &newtime);
   rtc_dumptime(&newtime, "Setting time");
 
   /* Then write the broken out values to the RTC */

arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c

@@ -467,7 +467,7 @@ static int rx65n_setrelative(FAR struct rtc_lowerhalf_s *lower,
 
           /* And convert the time back to broken out format */
 
-          (void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
+          gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
 
           /* The set the alarm using this absolute time */
 

arch/renesas/src/rx65n/rx65n_sbram.c

@@ -278,7 +278,7 @@ static int rx65n_sbram_open(FAR struct file *filep)
 static int rx65n_sbram_internal_close(FAR struct sbramfh_s *bbf)
 {
   bbf->dirty = 0;
-  (void)clock_gettime(CLOCK_REALTIME, &bbf->lastwrite);
+  clock_gettime(CLOCK_REALTIME, &bbf->lastwrite);
   bbf->crc = rx65n_sbram_crc(bbf);
 
   SBRAM_DUMP(bbf, "close done");

arch/renesas/src/rx65n/rx65n_usbhost.c

@@ -3925,7 +3925,7 @@ static uint16_t usb_cstd_is_set_frdy (uint16_t pipe, uint16_t fifosel,
 
       buffer = hw_usb_read_syscfg();
       buffer = hw_usb_read_syssts();
-      (void)nxsig_usleep(1);
+      nxsig_usleep(1);
     }
 
   return (RX65N_USB_FIFO_ERROR);
@@ -6322,7 +6322,7 @@ static void rx65n_usbhost_bottomhalf (void *arg)
 
   else
     {
-      (void)nxsig_usleep(100);
+      nxsig_usleep(100);
       uwarn("WARNING: un known bottomhalf. Value is %d\n",
          bottom_half_processing);
       syslog (LOG_INFO, "WARNING: un known bottomhalf. Value is %d\n",
@@ -6480,13 +6480,13 @@ static int rx65n_usbhost_rh_enumerate(struct usbhost_connection_s *conn,
 
   /* USB 2.0 spec says at least 50ms delay before port reset */
 
-  (void)nxsig_usleep(100 * 1000);
+  nxsig_usleep(100 * 1000);
 
   /* Put RH port 1 in reset.
    * Currently supporting only single downstream port)
    */
 
-  (void)nxsig_usleep(200 * 1000);
+  nxsig_usleep(200 * 1000);
   return OK;
 }
 

arch/risc-v/src/bl602/bl602_serial.c

@@ -888,9 +888,6 @@ void riscv_serialinit(void)
 int up_putc(int ch)
 {
 #ifdef HAVE_SERIAL_CONSOLE
-  struct bl602_uart_s *priv = (struct bl602_uart_s *)CONSOLE_DEV.priv;
-  (void)priv;
-
   irqstate_t flags = enter_critical_section();
 
   /* Check for LF */

arch/risc-v/src/common/riscv_sigdeliver.c

@@ -120,7 +120,7 @@ void riscv_sigdeliver(void)
   DEBUGASSERT(rtcb->irqcount == 0);
   while (rtcb->irqcount < saved_irqcount)
     {
-      (void)enter_critical_section();
+      enter_critical_section();
     }
 #endif
 

arch/risc-v/src/common/riscv_swint.c

@@ -297,7 +297,7 @@ int riscv_swint(int irq, void *context, void *arg)
            */
 
           rtcb->flags          &= ~TCB_FLAG_SYSCALL;
-          (void)nxsig_unmask_pendingsignal();
+          nxsig_unmask_pendingsignal();
         }
         break;
 #endif

arch/risc-v/src/rv32m1/rv32m1_irq.c

@@ -214,7 +214,7 @@ void up_enable_irq(int irq)
 
       /* Read INTPTEN back to make it sure */
 
-      (void)getreg32(RV32M1_EU_INTPTEN);
+      getreg32(RV32M1_EU_INTPTEN);
     }
 }
 

arch/sim/src/sim/up_macho_init.c

@@ -67,7 +67,7 @@ allow_write(const void *start, const void *end)
    * the OS version.
    */
 
-  (void)mprotect(p, sz, PROT_READ | PROT_WRITE);
+  mprotect(p, sz, PROT_READ | PROT_WRITE);
 }
 
 __attribute__((constructor))