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arch/arm/src/tiva/hardware: Review and update for compatibility with CC13xx.

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This commit is contained in:
Gregory Nutt
2019-02-14 17:27:37 -06:00
parent b8c7e5fcc0
commit ee8b0a076c
1 changed files with 164 additions and 139 deletions
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arch/arm/src/tiva/hardware/tiva_ssi.h
+40 -15
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@@ -1,4 +1,4 @@
/************************************************************************************ /********************************************************************************************
* arch/arm/src/tiva/hardware/tiva_ssi.h * arch/arm/src/tiva/hardware/tiva_ssi.h
* *
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -31,25 +31,25 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ********************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H
/************************************************************************************ /********************************************************************************************
* Included Files * Included Files
************************************************************************************/ ********************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h> #include <sys/types.h>
#if TIVA_NSSI > 0 #if TIVA_NSSI > 0
/************************************************************************************ /********************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ********************************************************************************************/
/* SSI register offsets *************************************************************/ /* SSI register offsets *********************************************************************/
#define TIVA_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ #define TIVA_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
#define TIVA_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ #define TIVA_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
@@ -60,6 +60,9 @@
#define TIVA_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ #define TIVA_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
#define TIVA_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ #define TIVA_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
#define TIVA_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ #define TIVA_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# define TIVA_SSI_DMACR_OFFSET 0x024 /* SSI DMA Control */
#else /* if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TIVA) */
# define TIVA_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ # define TIVA_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
# define TIVA_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ # define TIVA_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
# define TIVA_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ # define TIVA_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
@@ -72,8 +75,9 @@
# define TIVA_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ # define TIVA_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
# define TIVA_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ # define TIVA_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
# define TIVA_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ # define TIVA_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
#endif
/* SSI register addresses ***********************************************************/ /* SSI register addresses *******************************************************************/
#define TIVA_SSI0_CR0 (TIVA_SSI0_BASE + TIVA_SSI_CR0_OFFSET) #define TIVA_SSI0_CR0 (TIVA_SSI0_BASE + TIVA_SSI_CR0_OFFSET)
#define TIVA_SSI0_CR1 (TIVA_SSI0_BASE + TIVA_SSI_CR1_OFFSET) #define TIVA_SSI0_CR1 (TIVA_SSI0_BASE + TIVA_SSI_CR1_OFFSET)
@@ -84,6 +88,9 @@
#define TIVA_SSI0_RIS (TIVA_SSI0_BASE + TIVA_SSI_RIS_OFFSET) #define TIVA_SSI0_RIS (TIVA_SSI0_BASE + TIVA_SSI_RIS_OFFSET)
#define TIVA_SSI0_MIS (TIVA_SSI0_BASE + TIVA_SSI_MIS_OFFSET) #define TIVA_SSI0_MIS (TIVA_SSI0_BASE + TIVA_SSI_MIS_OFFSET)
#define TIVA_SSI0_ICR (TIVA_SSI0_BASE + TIVA_SSI_ICR_OFFSET) #define TIVA_SSI0_ICR (TIVA_SSI0_BASE + TIVA_SSI_ICR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# define TIVA_SSI0_DMACR (TIVA_SSI0_BASE + TIVA_SSI_DMACR_OFFSET)
#else /* if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TIVA) */
# define TIVA_SSI0_PERIPHID4 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID4_OFFSET) # define TIVA_SSI0_PERIPHID4 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID4_OFFSET)
# define TIVA_SSI0_PERIPHID5 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID5_OFFSET) # define TIVA_SSI0_PERIPHID5 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID5_OFFSET)
# define TIVA_SSI0_PERIPHID6 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID6_OFFSET) # define TIVA_SSI0_PERIPHID6 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID6_OFFSET)
@@ -96,6 +103,7 @@
# define TIVA_SSI0_PCELLID1 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID1_OFFSET) # define TIVA_SSI0_PCELLID1 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID1_OFFSET)
# define TIVA_SSI0_PCELLID2 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID2_OFFSET) # define TIVA_SSI0_PCELLID2 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID2_OFFSET)
# define TIVA_SSI0_PCELLID3 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID3_OFFSET) # define TIVA_SSI0_PCELLID3 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID3_OFFSET)
#endif
#if TIVA_NSSI > 1 #if TIVA_NSSI > 1
#define TIVA_SSI1_CR0 (TIVA_SSI1_BASE + TIVA_SSI_CR0_OFFSET) #define TIVA_SSI1_CR0 (TIVA_SSI1_BASE + TIVA_SSI_CR0_OFFSET)
@@ -107,6 +115,9 @@
#define TIVA_SSI1_RIS (TIVA_SSI1_BASE + TIVA_SSI_RIS_OFFSET) #define TIVA_SSI1_RIS (TIVA_SSI1_BASE + TIVA_SSI_RIS_OFFSET)
#define TIVA_SSI1_MIS (TIVA_SSI1_BASE + TIVA_SSI_MIS_OFFSET) #define TIVA_SSI1_MIS (TIVA_SSI1_BASE + TIVA_SSI_MIS_OFFSET)
#define TIVA_SSI1_ICR (TIVA_SSI1_BASE + TIVA_SSI_ICR_OFFSET) #define TIVA_SSI1_ICR (TIVA_SSI1_BASE + TIVA_SSI_ICR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# define TIVA_SSI1_DMACR (TIVA_SSI1_BASE + TIVA_SSI_DMACR_OFFSET)
#else /* if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TIVA) */
# define TIVA_SSI1_PERIPHID4 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID4_OFFSET) # define TIVA_SSI1_PERIPHID4 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID4_OFFSET)
# define TIVA_SSI1_PERIPHID5 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID5_OFFSET) # define TIVA_SSI1_PERIPHID5 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID5_OFFSET)
# define TIVA_SSI1_PERIPHID6 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID6_OFFSET) # define TIVA_SSI1_PERIPHID6 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID6_OFFSET)
@@ -119,6 +130,7 @@
# define TIVA_SSI1_PCELLID1 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID1_OFFSET) # define TIVA_SSI1_PCELLID1 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID1_OFFSET)
# define TIVA_SSI1_PCELLID2 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID2_OFFSET) # define TIVA_SSI1_PCELLID2 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID2_OFFSET)
# define TIVA_SSI1_PCELLID3 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID3_OFFSET) # define TIVA_SSI1_PCELLID3 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID3_OFFSET)
#endif
#define TIVA_SSI_BASE(n) (TIVA_SSI0_BASE + (n)*0x01000) #define TIVA_SSI_BASE(n) (TIVA_SSI0_BASE + (n)*0x01000)
@@ -131,6 +143,9 @@
#define TIVA_SSI_RIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_RIS_OFFSET) #define TIVA_SSI_RIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_RIS_OFFSET)
#define TIVA_SSI_MIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_MIS_OFFSET) #define TIVA_SSI_MIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_MIS_OFFSET)
#define TIVA_SSI_ICR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_ICR_OFFSET) #define TIVA_SSI_ICR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_ICR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# define TIVA_SSI_DMACR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_DMACR_OFFSET)
#else /* if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TIVA) */
# define TIVA_SSI_PERIPHID4(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID4_OFFSET) # define TIVA_SSI_PERIPHID4(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID4_OFFSET)
# define TIVA_SSI_PERIPHID5(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID5_OFFSET) # define TIVA_SSI_PERIPHID5(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID5_OFFSET)
# define TIVA_SSI_PERIPHID6(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID6_OFFSET) # define TIVA_SSI_PERIPHID6(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID6_OFFSET)
@@ -143,9 +158,10 @@
# define TIVA_SSI_PCELLID1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID1_OFFSET) # define TIVA_SSI_PCELLID1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID1_OFFSET)
# define TIVA_SSI_PCELLID2(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID2_OFFSET) # define TIVA_SSI_PCELLID2(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID2_OFFSET)
# define TIVA_SSI_PCELLID3(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID3_OFFSET) # define TIVA_SSI_PCELLID3(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID3_OFFSET)
#endif
#endif /* TIVA_NSSI > 1 */ #endif /* TIVA_NSSI > 1 */
/* SSI register bit defitiions ******************************************************/ /* SSI register bit defitiions **************************************************************/
/* SSI Control 0 (SSICR0), offset 0x000 */ /* SSI Control 0 (SSICR0), offset 0x000 */
@@ -211,6 +227,14 @@
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ #define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ #define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
/* SSI DMA Control */
# define SSI_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA enable */
# define SSI_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA enable */
#endif
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TIVA) */
/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ /* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
# define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ # define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
@@ -218,18 +242,19 @@
/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ /* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
# define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ # define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
#endif
/************************************************************************************ /********************************************************************************************
* Public Types * Public Types
************************************************************************************/ ********************************************************************************************/
/************************************************************************************ /********************************************************************************************
* Public Data * Public Data
************************************************************************************/ ********************************************************************************************/
/************************************************************************************ /********************************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ********************************************************************************************/
#endif /* TIVA_NSSI > 0 */ #endif /* TIVA_NSSI > 0 */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H */ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H */