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include/nuttx/i2c/i2c_master.h: Add a definition to distinguish a new START of messages from a repeated start. No lower-half I2C drivers actually implement this new flag bit, however. drivers/i2c/i2c_writeread.c: Use new repeated START definition where appopriated. Other: Some cosmetic changes, updates to README files, etc.

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This commit is contained in:
Gregory Nutt
2018-08-03 07:43:57 -06:00
parent ac5b2ea049
commit ee28cd9aeb
5 changed files with 39 additions and 37 deletions
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arch/arm/src/samd5e5/sam_clockconfig.c
+17 -23
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@@ -416,7 +416,7 @@ static void sam_xosc32k_configure(const struct sam_xosc32_config_s *config)
/* Wait for XOSC32 to become ready if it was enabled */ /* Wait for XOSC32 to become ready if it was enabled */
if (config->enable && ! config->ondemand) if (config->enable && !config->ondemand)
{ {
while ((getreg32(SAM_OSC32KCTRL_STATUS) & while ((getreg32(SAM_OSC32KCTRL_STATUS) &
OSC32KCTRL_INT_XOSC32KRDY) == 0) OSC32KCTRL_INT_XOSC32KRDY) == 0)
@@ -542,23 +542,21 @@ static void sam_xosc0_configure(const struct sam_clockconfig_s *config)
regval = sam_xoscctrl(config); regval = sam_xoscctrl(config);
putreg32(regval, SAM_OSCCTRL_XOSCCTRL0); putreg32(regval, SAM_OSCCTRL_XOSCCTRL0);
/* If the XOSC was enabled, then wait for it to become ready */ /* Wait for XOSC32 to become ready if it was enabled */
/* Wait for XOSC32 to become ready if it was enabled */ if (config->enable)
{
if (config->enable) while (getreg32(SAM_OSCCTRL_STATUS) & OSCCTRL_INT_XOSCRDY0) == 0)
{ {
while (getreg32(SAM_OSCCTRL_STATUS) & OSCCTRL_INT_XOSCRDY0) == 0) }
{ }
}
}
/* Re-select OnDemand */ /* Re-select OnDemand */
if (config->ondemand) if (config->ondemand)
{ {
regval = getre32(SAM_OSCCTRL_XOSCCTRL0) regval = getre32(SAM_OSCCTRL_XOSCCTRL0)
regval |=OSCCTRL_XOSCCTRL_ONDEMAND; regval |= OSCCTRL_XOSCCTRL_ONDEMAND;
putreg32(regval, SAM_OSCCTRL_XOSCCTRL0); putreg32(regval, SAM_OSCCTRL_XOSCCTRL0);
} }
} }
@@ -574,23 +572,21 @@ void sam_xosc1_configure(const struct sam_xosc_config_s *config)
regval = sam_xoscctrl(config); regval = sam_xoscctrl(config);
putreg32(regval, SAM_OSCCTRL_XOSCCTRL1); putreg32(regval, SAM_OSCCTRL_XOSCCTRL1);
/* If the XOSC was enabled, then wait for it to become ready */ /* Wait for XOSC32 to become ready if it was enabled */
/* Wait for XOSC32 to become ready if it was enabled */ if (config->enable)
{
if (config->enable) while (getreg32(SAM_OSCCTRL_STATUS) & OSCCTRL_INT_XOSCRDY1) == 0)
{ {
while (getreg32(SAM_OSCCTRL_STATUS) & OSCCTRL_INT_XOSCRDY1) == 0) }
{ }
}
}
/* Re-select OnDemand */ /* Re-select OnDemand */
if (config->ondemand) if (config->ondemand)
{ {
regval = getre32(SAM_OSCCTRL_XOSCCTRL1) regval = getre32(SAM_OSCCTRL_XOSCCTRL1)
regval |=OSCCTRL_XOSCCTRL_ONDEMAND; regval |= OSCCTRL_XOSCCTRL_ONDEMAND;
putreg32(regval, SAM_OSCCTRL_XOSCCTRL1); putreg32(regval, SAM_OSCCTRL_XOSCCTRL1);
} }
} }
@@ -631,7 +627,6 @@ static void sam_gclk_configure(uintptr_t regaddr,
regval = GCLK_GENCTRL_SRC(config->source) | GCLK_GENCTRL_GENEN | regval = GCLK_GENCTRL_SRC(config->source) | GCLK_GENCTRL_GENEN |
GCLK_GENCTRL1_DIV(config->div); GCLK_GENCTRL1_DIV(config->div);
if (config->idc) if (config->idc)
{ {
regval |= GCLK_GENCTRL_IDC; regval |= GCLK_GENCTRL_IDC;
@@ -872,7 +867,6 @@ static void sam_dfll_ready(const struct sam_dfll_config_s *config)
if ((regval8 & OSCCTRL_DFLLCTRLB_MODE) != 0) if ((regval8 & OSCCTRL_DFLLCTRLB_MODE) != 0)
{ {
ready = OSCCTRL_INT_DFLLRDY | OSCCTRL_INT_DFLLLCKC; ready = OSCCTRL_INT_DFLLRDY | OSCCTRL_INT_DFLLLCKC;
} }
/* In open-loop mode, wait only for DFLL ready */ /* In open-loop mode, wait only for DFLL ready */
configs/metro-m4/README.txt
+6
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@@ -45,6 +45,12 @@ STATUS
hardware. The primary JTAG problem seems to be that it is now unable hardware. The primary JTAG problem seems to be that it is now unable
to halt the CPU. to halt the CPU.
This is most likely a consequence of something happening in the NuttX
boot-up sequence that interferes with JTAG operation. When I continue
debugging in the future, I will put an infinitel loop, branch-on-self
at the code startup up (__start) so that I can attached the debugger
and step through the initial configuration.
Unlocking FLASH Unlocking FLASH
=============== ===============
drivers/eeprom/i2c_xx24xx.c
+1 -1
View File
@@ -103,7 +103,7 @@
****************************************************************************/ ****************************************************************************/
#ifndef CONFIG_EE24XX_FREQUENCY #ifndef CONFIG_EE24XX_FREQUENCY
#define CONFIG_EE24XX_FREQUENCY 100000 # define CONFIG_EE24XX_FREQUENCY 100000
#endif #endif
/**************************************************************************** /****************************************************************************
drivers/i2c/i2c_writeread.c
+13 -12
View File
@@ -83,19 +83,20 @@ int i2c_writeread(FAR struct i2c_master_s *dev,
/* Format two messages: The first is a write */ /* Format two messages: The first is a write */
msg[0].frequency = config->frequency, msg[0].frequency = config->frequency,
msg[0].addr = config->address; msg[0].addr = config->address;
msg[0].flags = flags; msg[0].flags = flags;
msg[0].buffer = (FAR uint8_t *)wbuffer; /* Override const */ msg[0].buffer = (FAR uint8_t *)wbuffer; /* Override const */
msg[0].length = wbuflen; msg[0].length = wbuflen;
/* The second is either a read (rbuflen > 0) or a write (rbuflen < 0) with /* The second is either a read (rbuflen > 0) with a repeated start or a
* no restart. * write (rbuflen < 0) with no restart.
*/ */
if (rbuflen > 0) if (rbuflen > 0)
{ {
msg[1].flags = (flags | I2C_M_READ); msg[0].flags |= I2C_M_NOSTOP;
msg[1].flags = (flags | I2C_M_READ);
} }
else else
{ {
@@ -103,10 +104,10 @@ int i2c_writeread(FAR struct i2c_master_s *dev,
rbuflen = -rbuflen; rbuflen = -rbuflen;
} }
msg[1].frequency = config->frequency, msg[1].frequency = config->frequency,
msg[1].addr = config->address; msg[1].addr = config->address;
msg[1].buffer = rbuffer; msg[1].buffer = rbuffer;
msg[1].length = rbuflen; msg[1].length = rbuflen;
/* Then perform the transfer. */ /* Then perform the transfer. */
include/nuttx/i2c/i2c_master.h
+2 -1
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@@ -77,8 +77,9 @@
#define I2C_M_READ 0x0001 /* Read data, from slave to master */ #define I2C_M_READ 0x0001 /* Read data, from slave to master */
#define I2C_M_TEN 0x0002 /* Ten bit address */ #define I2C_M_TEN 0x0002 /* Ten bit address */
#define I2C_M_NOSTOP 0x0040 /* Message should not end with a STOP */
#define I2C_M_NORESTART 0x0080 /* Message should not begin with #define I2C_M_NORESTART 0x0080 /* Message should not begin with
* (re-)start of transfer */ * (re-)START of transfer */
/* I2C Character Driver IOCTL Commands **************************************/ /* I2C Character Driver IOCTL Commands **************************************/
/* The I2C driver is intended to support application testing of the I2C bus. /* The I2C driver is intended to support application testing of the I2C bus.