mirror of
https://github.com/apache/nuttx.git
synced 2026-05-30 21:36:28 +08:00
arch/arm/xmc4 : various fixes and clean
- Fix EtherCAT signals drive strengh (from errata PORTS_CM.H002), caused bus faults. - Changed xmc4_ecat.c for compile time pin definition. - Fixed xmc4_ecat.c register not written (reset value already used). - Removed EXTCLK for xmc4800 as pin is used for ECAT. - Clean xmc4 familly board.h and clocks config. Signed-off-by: adriendesp <adrien.desproges@gmail.com>
This commit is contained in:
@@ -101,13 +101,13 @@
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/* 120 MHz
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*
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* fVCO = 12MHz * 40 / 2 = 480MHz
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* fPLL = 480MHz / 2 = 240MHz
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* fSYS = fPLL / 2 = 120MHz
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* fCCU = fSYS / 2 = 60MHz
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* fCPU = fSYS / 1 = 120MHz
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* fPB = fCPU / 2 = 60MHz
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* fETH = fSYS / 2 = 60MHz
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* fVCO = 12MHz * 40 / 1 = 480MHz
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* fPLL = 480MHz / 4 = 120MHz
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* fSYS = fPLL / 1 = 120MHz
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* fCCU = fSYS / 2 = 60MHz
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* fCPU = fSYS / 1 = 120MHz
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* fPERIPH = fCPU / 2 = 60MHz
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* fETH = fSYS / 2 = 60MHz
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*/
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# define BOARD_PLL_NDIV 40
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@@ -160,9 +160,6 @@
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# define BOARD_WDTDIV 1
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# define BOARD_WDT_FREQUENCY 24000000
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# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
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# define BOARD_PLL_ECKDIV 480 /* [1,512] */
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# define kHz_1 1000
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# define MHz_1 (kHz_1 * kHz_1)
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# define MHz_50 ( 50 * MHz_1)
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@@ -206,12 +203,10 @@
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# define EXTCLK_PIN_P1_15 15
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# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8
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# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
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# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */
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# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY)
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# define BOARD_PLL_ECKDIV 480 /* [1,512] */
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/* range check EXTDIV */
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# if BOARD_EXTDIV > 512
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# if BOARD_PLL_ECKDIV > 512
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# error "EXTCLK Divisor out of range!"
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# endif
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#endif
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@@ -235,8 +230,8 @@
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*/
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#undef BOARD_ENABLE_USBPLL
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#define BOARD_USB_PDIV 2
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#define BOARD_USB_NDIV 64
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#define BOARD_USBPLL_PDIV 2
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#define BOARD_USBPLL_NDIV 64
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/* FLASH wait states */
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@@ -97,13 +97,13 @@
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/* 120 MHz
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*
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* fVCO = 12MHz * 40 / 2 = 480MHz
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* fPLL = 480MHz / 2 = 240MHz
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* fSYS = fPLL / 2 = 120MHz
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* fCCU = fSYS / 2 = 60MHz
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* fCPU = fSYS / 1 = 120MHz
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* fPB = fCPU / 2 = 60MHz
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* fETH = fSYS / 2 = 60MHz
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* fVCO = 12MHz * 40 / 1 = 480MHz
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* fPLL = 480MHz / 4 = 120MHz
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* fSYS = fPLL / 1 = 120MHz
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* fCCU = fSYS / 2 = 60MHz
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* fCPU = fSYS / 1 = 120MHz
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* fPERIPH = fCPU / 2 = 60MHz
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* fETH = fSYS / 2 = 60MHz
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*/
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# define BOARD_PLL_NDIV 40
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@@ -156,9 +156,6 @@
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# define BOARD_WDTDIV 1
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# define BOARD_WDT_FREQUENCY 24000000
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# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
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# define BOARD_PLL_ECKDIV 480 /* [1,512] */
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# define kHz_1 1000
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# define MHz_1 (kHz_1 * kHz_1)
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# define MHz_50 ( 50 * MHz_1)
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@@ -202,12 +199,10 @@
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# define EXTCLK_PIN_P1_15 15
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# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8
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# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
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# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */
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# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY)
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# define BOARD_PLL_ECKDIV 480 /* [1,512] */
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/* range check EXTDIV */
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# if BOARD_EXTDIV > 512
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# if BOARD_PLL_ECKDIV > 512
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# error "EXTCLK Divisor out of range!"
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# endif
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#endif
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@@ -224,15 +219,16 @@
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/* USB PLL settings.
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*
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* fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz
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* fUSBPLL = fXTAL * N / 2P = 192MHz
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* fUSB = fUSBPLL / USBDIV = 192MHz / 4 = 48 MHz
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*
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* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and
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* fUSBPLLVCO <= 520 MHz
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*/
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#undef BOARD_ENABLE_USBPLL
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#define BOARD_USB_PDIV 2
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#define BOARD_USB_NDIV 64
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#define BOARD_USBPLL_PDIV 2
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#define BOARD_USBPLL_NDIV 64
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/* FLASH wait states */
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@@ -301,7 +297,7 @@
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#define BUTTON_0_BIT (1 << BUTTON_0)
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#define BUTTON_1_BIT (1 << BUTTON_1)
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/* USIC0 ********************************************************************/
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/* USIC *********************************************************************/
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/* USIC0 CH0 is used as UART0
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*
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@@ -91,19 +91,17 @@
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#define BOARD_ENABLE_PLL 1 /* enable the PLL */
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#define CPU_FREQ 120 /* MHz */
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/* TODO: Automate PLL calculations */
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#if CPU_FREQ == 120
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/* 120 MHz
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*
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* fVCO = 12MHz * 40 / 2 = 480MHz
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* fPLL = 480MHz / 2 = 240MHz
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* fSYS = fPLL / 2 = 120MHz
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* fCCU = fSYS / 2 = 60MHz
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* fCPU = fSYS / 1 = 120MHz
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* fPB = fCPU / 2 = 60MHz
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* fETH = fSYS / 2 = 60MHz
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* fVCO = 12MHz * 40 / 1 = 480MHz
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* fPLL = 480MHz / 4 = 120MHz
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* fSYS = fPLL / 1 = 120MHz
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* fCCU = fSYS / 2 = 60MHz
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* fCPU = fSYS / 1 = 120MHz
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* fPERIPH = fCPU / 2 = 60MHz
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* fETH = fSYS / 2 = 60MHz
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*/
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# define BOARD_PLL_NDIV 40
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@@ -156,9 +154,6 @@
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# define BOARD_WDTDIV 1
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# define BOARD_WDT_FREQUENCY 24000000
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# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
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# define BOARD_PLL_ECKDIV 480 /* [1,512] */
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# define kHz_1 1000
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# define MHz_1 (kHz_1 * kHz_1)
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# define MHz_50 ( 50 * MHz_1)
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@@ -195,19 +190,17 @@
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/* EXT clock settings */
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#define BOARD_EXTCKL_ENABLE 1 /* 0 disables output */
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#define BOARD_EXTCKL_ENABLE 0 /* 0 disables output, P0.12 taken by ECAT */
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#if BOARD_EXTCKL_ENABLE
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# define EXTCLK_PIN_P0_8 8
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# define EXTCLK_PIN_P1_15 15
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# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8
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# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
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# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */
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# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY)
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# define BOARD_PLL_ECKDIV 480 /* [1,512] */
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/* range check EXTDIV */
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# if BOARD_EXTDIV > 512
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# if BOARD_PLL_ECKDIV > 512
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# error "EXTCLK Divisor out of range!"
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# endif
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#endif
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@@ -224,15 +217,27 @@
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/* USB PLL settings.
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*
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* fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz
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* fUSBPLLVCO = fXTAL * N / P = 12M * 100 / 3 = 400MHz
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* fUSBPLL = fUSBPLLVCO / 2 = 200MHz
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*
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* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and
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* fUSBPLLVCO <= 520 MHz
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*/
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#define BOARD_ENABLE_USBPLL
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#define BOARD_USB_PDIV 3
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#define BOARD_USB_NDIV 100
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#define BOARD_ENABLE_USBPLL
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#define BOARD_USBPLL_PDIV 3
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#define BOARD_USBPLL_NDIV 100
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/* ECAT clock
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*
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* fECAT = fUSBPLL / (ECATDIV + 1) = 200M / 2 = 100MHz
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*/
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#define BOARD_ECAT_DIV 1
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# if BOARD_ECAT_DIV > 3
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# error "ECADIV out of range! [0-3]"
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# endif
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/* FLASH wait states */
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@@ -301,7 +306,7 @@
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#define BUTTON_0_BIT (1 << BUTTON_0)
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#define BUTTON_1_BIT (1 << BUTTON_1)
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/* USIC0 ********************************************************************/
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/* Peripherals definitions **************************************************/
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/* USIC0 CH0 is used as UART0
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*
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@@ -325,7 +330,9 @@
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#define GPIO_SPI4_MISO (GPIO_U2C0_DX0C)
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#define GPIO_SPI4_SCLK (GPIO_U2C0_SCLKOUT_1 | GPIO_PADA2_STRONGMEDIUM)
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/* ECAT0 configuration */
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/* ECAT0 configuration
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* See XMC4800 Relax Board user manual for associated pinout.
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*/
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#define ECAT_CLK_25 GPIO_ECAT_CLK_25_1
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#define ECAT_LED_ERR GPIO_ECAT_LED_ERR
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