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nRF52 SPI: use PPI API instead of direct register access

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This commit is contained in:
Matias N
2021-01-30 17:28:17 -03:00
committed by Brennan Ashton
parent 22437698f1
commit e9a45ea183
2 changed files with 13 additions and 12 deletions
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arch/arm/src/nrf52/Kconfig
+1
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@@ -621,6 +621,7 @@ menu "SPI Configuration"
config NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER config NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
bool "Master 1 Byte transfer anomaly workaround" bool "Master 1 Byte transfer anomaly workaround"
depends on NRF52_SPI_MASTER && ARCH_CHIP_NRF52832 depends on NRF52_SPI_MASTER && ARCH_CHIP_NRF52832
select NRF52_PPI
default y default y
---help--- ---help---
Enable the workaround to fix SPI Master 1 byte transfer bug Enable the workaround to fix SPI Master 1 byte transfer bug
arch/arm/src/nrf52/nrf52_spi.c
+12 -12
View File
@@ -44,7 +44,7 @@
#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER #ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
# include "hardware/nrf52_gpiote.h" # include "hardware/nrf52_gpiote.h"
# include "hardware/nrf52_ppi.h" # include "nrf52_ppi.h"
#endif #endif
/**************************************************************************** /****************************************************************************
@@ -63,7 +63,7 @@
/* Reserve PPI channel and GPIOTE channel for 1 byte transfer workaround */ /* Reserve PPI channel and GPIOTE channel for 1 byte transfer workaround */
#ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER #ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER
# define SPI_1B_WORKAROUND_PPI_CHAN (18) # define SPI_1B_WORKAROUND_PPI_CHAN (NRF52_PPI_NUM_CONFIGURABLE_CHANNELS - 1)
# define SPI_1B_WORKAROUND_GPIOTE_CHAN (7) # define SPI_1B_WORKAROUND_GPIOTE_CHAN (7)
#endif #endif
@@ -1016,29 +1016,29 @@ static void nrf52_spi_1b_workaround(FAR struct spi_dev_s *dev, bool enable)
/* Stop the SPIM instance when SCK toggles */ /* Stop the SPIM instance when SCK toggles */
putreg32(NRF52_GPIOTE_EVENTS_IN(SPI_1B_WORKAROUND_GPIOTE_CHAN), nrf52_ppi_set_event_ep(SPI_1B_WORKAROUND_PPI_CHAN,
NRF52_PPI_CHEEP(SPI_1B_WORKAROUND_PPI_CHAN)); NRF52_GPIOTE_EVENTS_IN(
SPI_1B_WORKAROUND_GPIOTE_CHAN));
putreg32((priv->base + NRF52_SPIM_TASK_STOP_OFFSET), nrf52_ppi_set_task_ep(SPI_1B_WORKAROUND_PPI_CHAN,
NRF52_PPI_CHTEP(SPI_1B_WORKAROUND_PPI_CHAN)); priv->base + NRF52_SPIM_TASK_STOP_OFFSET);
/* Enable PPI channel */ /* Enable PPI channel */
modifyreg32(NRF52_PPI_CHEN, 0, nrf52_ppi_channel_enable(SPI_1B_WORKAROUND_PPI_CHAN, true);
PPI_CHEN_CH(SPI_1B_WORKAROUND_PPI_CHAN));
} }
else else
{ {
/* Disable event */ /* Disable event */
putreg32(0, NRF52_GPIOTE_CONFIG(SPI_1B_WORKAROUND_GPIOTE_CHAN)); putreg32(0, NRF52_GPIOTE_CONFIG(SPI_1B_WORKAROUND_GPIOTE_CHAN));
putreg32(0, NRF52_PPI_CHEEP(SPI_1B_WORKAROUND_PPI_CHAN));
putreg32(0, NRF52_PPI_CHTEP(SPI_1B_WORKAROUND_PPI_CHAN)); nrf52_ppi_set_event_ep(SPI_1B_WORKAROUND_PPI_CHAN, 0);
nrf52_ppi_set_task_ep(SPI_1B_WORKAROUND_PPI_CHAN, 0);
/* Disable PPI channel */ /* Disable PPI channel */
modifyreg32(NRF52_PPI_CHEN, nrf52_ppi_channel_enable(SPI_1B_WORKAROUND_PPI_CHAN, false);
PPI_CHEN_CH(SPI_1B_WORKAROUND_PPI_CHAN), 0);
} }
} }
#endif #endif