Remove the arch/ subdirectory; replace it with a submodule

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "configs"]
 	path = configs
 	url = https://bitbucket.org/nuttx/boards.git
+[submodule "arch"]
+	path = arch
+	url = https://bitbucket.org/nuttx/arch.git

arch/README.txt

@@ -1,332 +0,0 @@
-Architecture-Specific Code
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-Table of Contents
-^^^^^^^^^^^^^^^^^
-
-  o Architecture-Specific Code
-  o Summary of Files
-  o Supported Architectures
-  o Configuring NuttX
-
-Architecture-Specific Code
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The NuttX configuration consists of:
-
-o Processor architecture specific files.  These are the files contained
-  in the arch/<arch-name>/ directory discussed in this README.
-
-o Chip/SoC specific files.  Each processor processor architecture
-  is embedded in chip or System-on-a-Chip (SoC) architecture.  The
-  full chip architecture includes the processor architecture plus
-  chip-specific interrupt logic, general purpose I/O (GIO) logic, and
-  specialized, internal peripherals (such as UARTs, USB, etc.).
-
-  These chip-specific files are contained within chip-specific
-  sub-directories in the arch/<arch-name>/ directory and are selected
-  via the CONFIG_ARCH_name selection
-
-o Board specific files.  In order to be usable, the chip must be
-  contained in a board environment.  The board configuration defines
-  additional properties of the board including such things as
-  peripheral LEDs, external peripherals (such as network, USB, etc.).
-
-  These board-specific configuration files can be found in the
-  configs/<board-name>/ sub-directories.
-
-This README will address the processor architecture specific files
-that are contained in the arch/<arch-name>/ directory. The file
-include/nuttx/arch.h identifies all of the APIs that must
-be provided by this architecture specific logic.  (It also includes
-arch/<arch-name>/arch.h as described below).
-
-Directory Structure
-^^^^^^^^^^^^^^^^^^^
-
-The arch directory contains architecture specific logic.  The complete
-board port in is defined by the architecture-specific code in this
-directory (plus the board-specific configurations in the config/
-subdirectory).  Each architecture must provide a subdirectory <arch-name>
-under arch/ with the following characteristics:
-
-
-        <arch-name>/
-        |-- include/
-        |   |--<chip-name>/
-        |   |  `-- (chip-specific header files)
-        |   |--<other-chips>/
-        |   |-- arch.h
-        |   |-- irq.h
-        |   `-- types.h
-        `-- src/
-            |--<chip-name>/
-            |  `-- (chip-specific source files)
-            |--<other-chips>/
-            |-- Makefile
-            `-- (architecture-specific source files)
-
-Summary of Files
-^^^^^^^^^^^^^^^^
-
-include/<chip-name>/
-  This sub-directory contains chip-specific header files.
-
-include/arch.h
-  This is a hook for any architecture specific definitions that may
-  be needed by the system.  It is included by include/nuttx/arch.h
-
-include/types.h
-  This provides architecture/toolchain-specific definitions for
-  standard types.  This file should typedef:
-
-    _int8_t, _uint8_t, _int16_t, _uint16_t, _int32_t, _uint32_t
-
-  and if the architecture supports 64-bit integers.
-
-    _int24_t, _uint24_t, int64_t, uint64_t
-
-  NOTE that these type names have a leading underscore character.  This
-  file will be included(indirectly) by include/stdint.h and typedef'ed to
-  the final name without the underscore character.  This roundabout way of
-  doings things allows the stdint.h to be removed from the include/
-  directory in the event that the user prefers to use the definitions
-  provided by their toolchain header files
-
-    irqstate_t
-
-  Must be defined to the be the size required to hold the interrupt
-  enable/disable state.
-
-  This file will be included by include/sys/types.h and be made
-  available to all files.
-
-include/irq.h
-  This file needs to define some architecture specific functions (usually
-  inline if the compiler supports inlining) and structure.  These include:
-
-  - struct xcptcontext.  This structures represents the saved context
-    of a thread.
-
-  - irqstate_t irqsave(void) -- Used to disable all interrupts.
-
-  - void irqrestore(irqstate_t flags) -- Used to restore interrupt
-    enables to the same state as before irqsave was called.
-
-  This file must also define NR_IRQS, the total number of IRQs supported
-  by the board.
-
-src/<chip-name>/
-  This sub-directory contains chip-specific source files.
-
-src/Makefile
-  This makefile will be executed to build the targets src/libup.a and
-  src/up_head.o.  The up_head.o file holds the entry point into the system
-  (power-on reset entry point, for example).  It will be used in
-  the final link with libup.a and other system archives to generate the
-  final executable.
-
-Supported Architectures
-^^^^^^^^^^^^^^^^^^^^^^^
-
-arch/sim - Linux/Cygwin simulation
-    A user-mode port of NuttX to the x86 Linux platform is available.
-    The purpose of this port is primarily to support OS feature development.
-    This port does not support interrupts or a real timer (and hence no
-    round robin scheduler)  Otherwise, it is complete.
-
-arch/arm - ARM-based micro-controllers
-    This directory holds common ARM architectures.  At present, this includes
-    the following subdirectories:
-
-    arch/arm/include and arch/arm/src/common
-        Common ARM/Cortex-M3 logic.
-
-    arch/arm/src/arm and arch/arm/include/arm
-        Common ARM-specific logic
-
-    arch/arm/src/armv7-m and arch/arm/include/armv7-m
-        Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
-
-    arch/arm/include/c5471 and arch/arm/src/c5471
-        TI TMS320C5471 (also called TMS320DM180 or just C5471).
-        NuttX operates on the ARM7 of this dual core processor. This port
-        complete, verified, and included in the NuttX release 0.1.1.
-
-    arch/arm/include/calypso and arch/arm/src/calypso
-        TI "Calypso" MCU used in various cell phones (and, in particular,
-        by the Osmocom-bb project).  Like the c5471, NuttX operates on the
-        ARM7 of this dual core processor. This port was contributed by
-        Denis Carilki and includes the work of Denis, Alan Carvalho de Assis,
-        and Stefan Richter.  Calypso support first appeared in NuttX-6.17.
-
-    arch/arm/include/dm320 and arch/arm/src/dm320
-        TI TMS320DM320 (also called just DM320).
-        NuttX operates on the ARM9EJS of this dual core processor.  This port
-        complete, verified, and included in the NuttX release 0.2.1.
-
-    arch/arm/include/imx and arch/arm/src/imx
-        Freescale MC9328MX1 or i.MX1. This port uses the Freescale MX1ADS
-        development board with a GNU arm-elf toolchain* under either Linux or Cygwin.
-        STATUS: This port has stalled because of development tool issues. Coding
-        is complete on the basic port (timer, serial console, SPI).
-
-    arch/arm/include/lm and arch/arm/src/lm
-        These directories contain support for the Luminary LM3S/4F family. The
-        initial, release of this port was included in NuttX version 0.4.6.  The
-        current port includes timer, serial console, Ethernet, SSI, and microSD
-        support. There are working configurations the NuttX OS test, to run the
-        NuttShell (NSH), the NuttX networking test, and the uIP web server.
-
-    arch/arm/include/lpc214x and arch/arm/src/lpc214x
-        These directories provide support for NXP LPC214x family of
-        ARM7TDMI processors.  This port boots and passes the OS test (examples/ostest).
-        The port is complete and verifed.  As of NuttX 0.3.17, the port includes:
-        timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
-        support.  A verifed NuttShell (NSH) configuration is also available.
-
-    arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
-        NXP LPC2378. Support is provided for the NXP LPC2378 MCU. This port was
-        contributed by Rommel Marcelo is was first released in NuttX-5.3.
-        STATUS: This port boots and passes the OS test (examples/ostest) and
-        includes a working implementation of the NuttShell (NSH). The port is
-        complete and verified. As of NuttX 5.3, the port includes only basic
-        timer interrupts and serial console support.
-
-    arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
-        These directories provide support for NXP LPC31xx family of
-        ARM926EJ-S processors.  The port for the NXP LPC3131 was first
-        released in NuttX-5.1 (but was not functional until NuttX-5.2).
-        STATUS: The basic EA3131 port is complete and verified in NuttX-5.2
-        This basic port includes basic boot-up, serial console, and timer
-        interrupts. This port was extended in NuttX 5.3 with a USB high
-        speed driver contributed by David Hewson. This port has been
-        verified using the NuttX OS test, USB serial and mass storage tests
-        and includes a working implementation of the NuttShell ((NSH)).
-
-        This port was later extended to support additional members of the
-        LPC31xx family including, specifically, the LPC3152.
-
-    arch/arm/include/sam3u and arch/arm/src/sam3u
-        Atmel AT91SAM3U. This port is for Atmel AT91SAM3U4E MCU.
-        STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
-        The basic port includes boot-up logic, interrupt driven serial
-        console, and system timer interrupts. That release passes the
-        NuttX OS test and is proven to have a valid OS implementation. A
-        onfiguration to support the NuttShell is also included.
-
-    arch/arm/include/stm32 and arch/arm/src/stm32
-        These directories contain support for the STMicro STM32 F1, F2, and
-        F4 families.
-
-        STATUS: The basic STM32 F1 port was released in NuttX version 0.4.12.
-        and has continued to develop consistently over time.  It now includes
-        support for the F2 and F4 families and a rich offering of peripheral
-        drivers.
-
-    arch/arm/include/str71x and arch/arm/src/str71x
-        These directories provide support for the STMicro STR71x processors.
-        Coding is complete on the basic port (boot logic, system time, serial console),
-        but no testing has been performed due to some problems I am having with my
-        JTAG wiggler and OpenOCD on Linux.
-
-arch/avr
-    This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
-    MCU families.  STATUS:  Under development.
-
-    arch/avr/include/avr and arch/avr/src/avr
-      Common support for all 8-bit AVR MCUs
-
-    arch/avr/include/atmega and arch/avr/src/atmega
-      Support specifically for the AVR ATMega family (specifically only for
-      the ATMega128 at the moment).
-
-    arch/avr/include/at90usb and arch/avr/src/at90usb
-      Support specifically for the AVR AT90USB646, 647, 1286, and 1287 family.
-
-    arch/avr/include/avr32 and arch/avr/src/avr32
-      Common support for all AVR32 MCUs
-
-    arch/avr/include/at32uc3 and arch/avr/src/at32uc3
-      Support specifically for the AT32UC3Bxxx family (specifically only for
-      the AT32UC3B0256 at the moment).
-
-arch/hc
-    This directory is dedicated to ports to the Freescale HC family.
-
-    arch/arm/include/m9s12 and arch/arm/src/m9s12
-      These directories provide support for the Freescale mc9s12x family.
-      STATUS:  Fragments of this port were first released in nuttx-5.0 and
-      the port was "code-complete" as nuttx-5.18.  However, the final
-      verification effort has been stalled because of higher priority tasks.
-
-arch/mips
-    This directory is dedicated to ports to the MIPS family.
-
-    arch/mips/include/mips32 and arch/mips/src/mips32
-      Common support for all MIPS32 architectures
-
-    arch/mips/include/pic32mx and arch/mips/src/pic32mx
-      Support for all MicroChip PIC32MX architectures
-
-arch/rgmp
-
-    RGMP stands for RTOS and GPOS on Multi-Processor.  RGMP is a project
-    for running GPOS and RTOS simultaneously on multi-processor platforms.
-    You can port your favorite RTOS to RGMP together with an unmodified
-    Linux to form a hybrid operating system. This makes your application
-    able to use both RTOS and GPOS features.
-
-    See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
-    information about RGMP.
-
-arch/sh - SuperH and related Hitachi/Renesas microcontrollers
-
-    arch/sh/include and arch/sh/src/common
-        Common SuperH logic.
-
-    arch/sh/include/shs and arch/sh/src/sh1
-        Support for the SH-1 processor.
-
-arch/x86 - Intel x86 architectures
-    This directory holds related, 32- and 64-bit architectures from Intel.
-    At present, this includes the following subdirectories:
-
-    arch/x86/include and arch/x86/src/common
-        Common x86 logic.
-
-    arch/x86/include/i486 and arch/x86/src/i486
-        These directories hold definitions and logic appropriate for any
-        instantiation of the 32-bit i486 architecture.
-
-    arch/x86/include/qemu and arch/x86/src/qemu
-        This is the implementation of NuttX on the QEMU x86 simulation.
-
-arch/z16 - ZiLOG 16-bit processors
-    This directory holds related, 16-bit architectures from ZiLOG.  At
-    present, this includes the following subdirectories:
-
-    arch/z16/include and arch/z16/src/common
-        Common microcontroller logic.
-
-    arch/z16/include/z16f and arch/z16/src/z16f
-        ZiLOG z16f Microcontroller.
-        STATUS: Released in nuttx-0.3.7.  Fully functional other than issues
-        addressed in ${TOPDIR}/TODO.
-
-arch/z80 - ZiLOG 8-bit microcontrollers
-    This directory holds related, 8-bit architectures from ZiLOG.  At
-    present, this includes the following subdirectories:
-
-    arch/z80/include and arch/z80/src/common
-        Common microcontroller logic.
-
-    arch/z80/include/z80 and arch/z80/src/z80
-        Classic ZiLOG z80 Microcontroller.
-        STATUS: Functional with no known defects.  There are still several
-         OS features that have not yet been tested (e.g., networking).
-
-    arch/z80/include/z8 and arch/z80/src/z8
-        ZiLOG Z8Encore! Microcontroller
-
-    arch/z80/include/ez80 and arch/z80/src/ez80
-        ZiLOG ez80 Acclaim! Microcontroller

arch/arm/include/.gitignore

@@ -1,3 +0,0 @@
-/board
-/chip
-

arch/arm/include/a1x/a10_irq.h

@@ -1,223 +0,0 @@
-/****************************************************************************************
- * arch/arm/include/a1x/a10_irq.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H
-#define __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* External interrupts numbers */
-
-#define A1X_IRQ_NMI         0 /* External Non-Mask Interrupt */
-#  define A1X_IRQ_POWER     0 /* Power module */
-#  define A1X_IRQ_BATTERY   0 /* Brownout detect */
-#  define A1X_IRQ_BROWNOUT  0 /* Brownout */
-#define A1X_IRQ_UART0       1 /* UART 0 interrupt */
-#define A1X_IRQ_UART1       2 /* UART 1 interrupt */
-#define A1X_IRQ_UART2       3 /* UART 2 interrupt */
-#define A1X_IRQ_UART3       4 /* UART 3 interrupt */
-#define A1X_IRQ_IR0         5 /* IR 0 interrupt */
-#define A1X_IRQ_IR1         6 /* IR 1 interrupt */
-#define A1X_IRQ_TWI0        7 /* TWI 0 interrupt */
-#define A1X_IRQ_TWI1        8 /* TWI 1 interrupt */
-#define A1X_IRQ_TWI2        9 /* TWI 2 interrupt */
-#define A1X_IRQ_SPI0       10 /* SPI 0 interrupt */
-#define A1X_IRQ_SPI1       11 /* SPI 1 interrupt */
-#define A1X_IRQ_SPI2       12 /* SPI 2 interrupt */
-#define A1X_IRQ_NC         13 /* NC */
-#define A1X_IRQ_AC97       14 /* AC97 interrupt */
-#define A1X_IRQ_TS         15 /* TS interrupt */
-#define A1X_IRQ_IIS        16 /* Digital Audio Controller interrupt */
-#define A1X_IRQ_UART4      17 /* UART 4 interrupt */
-#define A1X_IRQ_UART5      18 /* UART 5 interrupt */
-#define A1X_IRQ_UART6      19 /* UART 6 interrupt */
-#define A1X_IRQ_UART7      20 /* UART 7 interrupt */
-#define A1X_IRQ_KEYPAD     21 /* Keypad interrupt */
-#define A1X_IRQ_TIMER0     22 /* Timer port 0 */
-#define A1X_IRQ_TIMER1     23 /* Timer port 1 */
-#define A1X_IRQ_TIMER2     24 /* Timer 2 */
-#  define A1X_IRQ_ALARM    24 /* Alarm */
-#  define A1X_IRQ_WD       24 /* Watchdog */
-#define A1X_IRQ_TIMER3     25 /* Timer 3 interrupt */
-#define A1X_IRQ_CAN        26 /* CAN Bus controller interrupt */
-#define A1X_IRQ_DMA        27 /* DMA channel interrupt */
-#define A1X_IRQ_PIO        28 /* PIO interrupt */
-#define A1X_IRQ_TOUCH      29 /* Touch Panel interrupt */
-#define A1X_IRQ_AUDIO      30 /* Analog Audio Codec interrupt */
-#define A1X_IRQ_LRADC      31 /* LRADC interrupt */
-#define A1X_IRQ_SDMMC0     32 /* SD/MMC Host Controller 0 interrupt */
-#define A1X_IRQ_SDMMC1     33 /* SD/MMC Host Controller 1 interrupt */
-#define A1X_IRQ_SDMMC2     34 /* SD/MMC Host Controller 2 interrupt */
-#define A1X_IRQ_SDMMC3     35 /* SD/MMC Host Controller 3 interrupt */
-#define A1X_IRQ_RESERVED36 36
-#define A1X_IRQ_NAND       37 /* NAND Flash Controller (NFC) interrupt */
-#define A1X_IRQ_USB0       38 /* USB 0 wakeup, connect, disconnect interrupt */
-#define A1X_IRQ_USB1       39 /* USB 1 wakeup, connect, disconnect interrupt */
-#define A1X_IRQ_USB2       40 /* USB 2 wakeup, connect, disconnect interrupt */
-#define A1X_IRQ_SCR        41 /* SCR interrupt */
-#define A1X_IRQ_CSI0       42 /* CSI 0 interrupt */
-#define A1X_IRQ_CSI1       43 /* CSI 1 interrupt */
-#define A1X_IRQ_LCDC0      44 /* LCD Controller 0 interrupt */
-#define A1X_IRQ_LCDC1      45 /* LCD Controller 1 interrupt */
-#define A1X_IRQ_MP         46 /* MP interrupt */
-#define A1X_IRQ_DEFE0      47 /* DE-FE0 interrupt */
-#  define A1X_IRQ_DEBE0    47 /* DE-BE0 interrupt */
-#define A1X_IRQ_DEFE1      48 /* DE-FE1 interrupt */
-#  define A1X_IRQ_DEBE1    48 /* DE-BE1 interrupt */
-#define A1X_IRQ_PMU        49 /* PMU interrupt */
-#define A1X_IRQ_SPI3       50 /* SPI3 interrupt */
-#define A1X_IRQ_TZASC      51 /* TZASC interrupt */
-#define A1X_IRQ_PATA       52 /* PATA interrupt */
-#define A1X_IRQ_VE         53 /* VE interrupt */
-#define A1X_IRQ_SS         54 /* Security System interrupt */
-#define A1X_IRQ_EMAC       55 /* EMAC interrupt */
-#define A1X_IRQ_RESERVED56 56
-#define A1X_IRQ_RESERVED57 57
-#define A1X_IRQ_HDMI       58 /* HDMI interrupt */
-#define A1X_IRQ_TVE        59 /* TV encoder 0/1 interrupt */
-#define A1X_IRQ_ACE        60 /* ACE interrupt */
-#define A1X_IRQ_TVD        61 /* TV decoder interrupt */
-#define A1X_IRQ_PS20       62 /* PS2-0 interrupt */
-#define A1X_IRQ_PS21       63 /* PS2-1 interrupt */
-#define A1X_IRQ_USB3       64 /* USB 3 wakeup, connect, disconnect interrupt */
-#define A1X_IRQ_USB4       65 /* USB 4 wakeup, connect, disconnect interrupt */
-#define A1X_IRQ_PLE        66 /* PLE interrupts */
-#  define A1X_IRQ_PERFMU   66 /* Performance monitor interrupt */
-#define A1X_IRQ_TIMER4     67 /* Timer 4 interrupt */
-#define A1X_IRQ_TIMER5     68 /* Timer 5 interrupt */
-#define A1X_IRQ_GPU_GP     69
-#define A1X_IRQ_GPU_GPMMU  70
-#define A1X_IRQ_GPU_PP0    71
-#define A1X_IRQ_GPU_PPMMU0 72
-#define A1X_IRQ_GPU_PMU    73
-#define A1X_IRQ_GPU_RSV0   74
-#define A1X_IRQ_GPU_RSV1   75
-#define A1X_IRQ_GPU_RSV2   76
-#define A1X_IRQ_GPU_RSV3   77
-#define A1X_IRQ_GPU_RSV4   78
-#define A1X_IRQ_GPU_RSV5   79
-#define A1X_IRQ_GPU_RSV6   80
-
-/* Total number of interrupts */
-
-#define A1X_IRQ_NINT       81
-
-/* Up to 32 external PIO interrupts */
-
-#ifdef CONFIG_A1X_PIO_IRQ
-#  define A1X_PIO_EINT0    (A1X_IRQ_NINT+0)
-#  define A1X_PIO_EINT1    (A1X_IRQ_NINT+1)
-#  define A1X_PIO_EINT2    (A1X_IRQ_NINT+2)
-#  define A1X_PIO_EINT3    (A1X_IRQ_NINT+3)
-#  define A1X_PIO_EINT4    (A1X_IRQ_NINT+4)
-#  define A1X_PIO_EINT5    (A1X_IRQ_NINT+5)
-#  define A1X_PIO_EINT6    (A1X_IRQ_NINT+6)
-#  define A1X_PIO_EINT7    (A1X_IRQ_NINT+7)
-#  define A1X_PIO_EINT8    (A1X_IRQ_NINT+8)
-#  define A1X_PIO_EINT9    (A1X_IRQ_NINT+9)
-#  define A1X_PIO_EINT10   (A1X_IRQ_NINT+10)
-#  define A1X_PIO_EINT11   (A1X_IRQ_NINT+11)
-#  define A1X_PIO_EINT12   (A1X_IRQ_NINT+12)
-#  define A1X_PIO_EINT13   (A1X_IRQ_NINT+13)
-#  define A1X_PIO_EINT14   (A1X_IRQ_NINT+14)
-#  define A1X_PIO_EINT15   (A1X_IRQ_NINT+15)
-#  define A1X_PIO_EINT16   (A1X_IRQ_NINT+16)
-#  define A1X_PIO_EINT17   (A1X_IRQ_NINT+17)
-#  define A1X_PIO_EINT18   (A1X_IRQ_NINT+18)
-#  define A1X_PIO_EINT19   (A1X_IRQ_NINT+19)
-#  define A1X_PIO_EINT20   (A1X_IRQ_NINT+20)
-#  define A1X_PIO_EINT21   (A1X_IRQ_NINT+21)
-#  define A1X_PIO_EINT22   (A1X_IRQ_NINT+22)
-#  define A1X_PIO_EINT23   (A1X_IRQ_NINT+23)
-#  define A1X_PIO_EINT24   (A1X_IRQ_NINT+24)
-#  define A1X_PIO_EINT25   (A1X_IRQ_NINT+25)
-#  define A1X_PIO_EINT26   (A1X_IRQ_NINT+26)
-#  define A1X_PIO_EINT27   (A1X_IRQ_NINT+27)
-#  define A1X_PIO_EINT28   (A1X_IRQ_NINT+28)
-#  define A1X_PIO_EINT29   (A1X_IRQ_NINT+29)
-#  define A1X_PIO_EINT30   (A1X_IRQ_NINT+30)
-#  define A1X_PIO_EINT31   (A1X_IRQ_NINT+31)
-#  define A1X_PIO_NINT     32
-#else
-#  define A1X_PIO_NINT     0
-#endif
-
-/* Total number of IRQ numbers */
-
-#define NR_IRQS            (A1X_IRQ_NINT + A1X_PIO_NINT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Inline functions
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Variables
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Function Prototypes
- ****************************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H */
-

arch/arm/include/a1x/chip.h

@@ -1,68 +0,0 @@
-/************************************************************************************
- * arch/arm/include/a1x/chip.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_A1X_CHIP_H
-#define __ARCH_ARM_INCLUDE_A1X_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-/* A1X Family */
-
-#if defined(CONFIG_ARCH_CHIP_A10)
-#  define ALLWINNER_A1X    1         /* A1X family */
-#else
-#  error Unrecognized A1X chip
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_A1X_CHIP_H */

arch/arm/include/a1x/irq.h

@@ -1,91 +0,0 @@
-/****************************************************************************************
- * arch/arm/include/a1x/irq.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_A1X_IRQ_H
-#define __ARCH_ARM_INCLUDE_A1X_IRQ_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/a1x/chip.h>
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* Chip-Specific External interrupts */
-
-#if defined(CONFIG_ARCH_CHIP_A10)
-#  include <arch/a1x/a10_irq.h>
-#else
-#  error Unrecognized A1X chip
-#endif
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************************
- * Public Function Prototypes
- ****************************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_A1X_IRQ_H */
-

arch/arm/include/arch.h

@@ -1,210 +0,0 @@
-/****************************************************************************
- * arch/arm/include/arch.h
- *
- *   Copyright (C) 2007-2009, 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/arch.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARCH_H
-#define __ARCH_ARM_INCLUDE_ARCH_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#  include <nuttx/pgalloc.h>
-#  include <nuttx/addrenv.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifdef CONFIG_PIC
-
-/* This identifies the register the is used by the processor as the PIC base
- * register.  It is usually r9 or r10
- */
-
-#define PIC_REG         r10
-#define PIC_REG_STRING "r10"
-
-/* Macros to get and set the PIC base register.  picbase is assumed to be
- * of type (void*) and that it will fit into a uint32_t.  These must be
- * inline so that they will be compatible with the ABIs rules for
- * preserving the PIC register
- */
-
-#define up_getpicbase(ppicbase) \
-do { \
-  uint32_t picbase; \
-  __asm__ \
-  ( \
-    "\tmov %0, " PIC_REG_STRING "\n\t" \
-    : "=r"(picbase) \
-  ); \
-  *ppicbase = (FAR void*)picbase; \
-} while (0)
-
-#define up_setpicbase(picbase) \
-do { \
-  uint32_t _picbase = (uint32_t)picbase; \
-  __asm__ \
-  ( \
-    "\tmov " PIC_REG_STRING ", %0\n\t" \
-    : : "r"(_picbase) : PIC_REG_STRING \
-  ); \
-} while (0)
-
-#endif /* CONFIG_PIC */
-
-#ifdef CONFIG_ARCH_ADDRENV
-#if CONFIG_MM_PGSIZE != 4096
-#  error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
-#endif
-
-/* Convert 4KiB pages to 1MiB sections */
-
-#  define __PG2SECT_SHIFT     (20 - MM_PGSHIFT)
-#  define __PG2SECT_MASK      ((1 << __PG2SECT_SHIFT) - 1)
-
-#  define ARCH_PG2SECT(p)     (((p) + __PG2SECT_MASK) >> __PG2SECT_SHIFT)
-#  define ARCH_SECT2PG(s)     ((s) << __PG2SECT_SHIFT)
-
-#  define ARCH_TEXT_NSECTS    ARCH_PG2SECT(CONFIG_ARCH_TEXT_NPAGES)
-#  define ARCH_DATA_NSECTS    ARCH_PG2SECT(CONFIG_ARCH_DATA_NPAGES)
-#  define ARCH_HEAP_NSECTS    ARCH_PG2SECT(CONFIG_ARCH_HEAP_NPAGES)
-
-#  ifdef CONFIG_MM_SHM
-#    define ARCH_SHM_NSECTS   ARCH_PG2SECT(ARCH_SHM_MAXPAGES)
-#  endif
-
-#  ifdef CONFIG_ARCH_STACK_DYNAMIC
-#    define ARCH_STACK_NSECTS ARCH_PG2SECT(CONFIG_ARCH_STACK_NPAGES)
-#  endif
-#endif /* CONFIG_ARCH_ADDRENV */
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_ADDRENV
-/* The task group resources are retained in a single structure, task_group_s
- * that is defined in the header file nuttx/include/nuttx/sched.h. The type
- * group_addrenv_t must be defined by platform specific logic in
- * nuttx/arch/<architecture>/include/arch.h.
- *
- * These tables would hold the physical address of the level 2 page tables.
- * All would be initially NULL and would not be backed up with physical memory
- * until mappings in the level 2 page table are required.
- */
-
-struct group_addrenv_s
-{
-  /* Level 1 page table entries for each group section */
-
-  FAR uintptr_t *text[ARCH_TEXT_NSECTS];
-  FAR uintptr_t *data[ARCH_DATA_NSECTS];
-#ifdef CONFIG_BUILD_KERNEL
-  FAR uintptr_t *heap[ARCH_HEAP_NSECTS];
-#ifdef CONFIG_MM_SHM
-  FAR uintptr_t *shm[ARCH_SHM_NSECTS];
-#endif
-
-  /* Initial heap allocation (in bytes).  This exists only provide an
-   * indirect path for passing the size of the initial heap to the heap
-   * initialization logic.  These operations are separated in time and
-   * architecture.  REVISIT:  I would like a better way to do this.
-   */
-
-  size_t heapsize;
-#endif
-};
-
-typedef struct group_addrenv_s group_addrenv_t;
-
-/* This type is used when the OS needs to temporarily instantiate a
- * different address environment.  Used in the implementation of
- *
- *   int up_addrenv_select(group_addrenv_t addrenv, save_addrenv_t *oldenv);
- *   int up_addrenv_restore(save_addrenv_t oldenv);
- *
- * In this case, the saved valued in the L1 page table are returned
- */
-
-struct save_addrenv_s
-{
-  FAR uint32_t text[ARCH_TEXT_NSECTS];
-  FAR uint32_t data[ARCH_DATA_NSECTS];
-#ifdef CONFIG_BUILD_KERNEL
-  FAR uint32_t heap[ARCH_HEAP_NSECTS];
-#ifdef CONFIG_MM_SHM
-  FAR uint32_t shm[ARCH_SHM_NSECTS];
-#endif
-#endif
-};
-
-typedef struct save_addrenv_s save_addrenv_t;
-#endif
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_ARCH_H */

arch/arm/include/arm/irq.h

@@ -1,231 +0,0 @@
-/****************************************************************************
- * arch/arm/include/arm/irq.h
- *
- *   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARM_IRQ_H
-#define __ARCH_ARM_INCLUDE_ARM_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/irq.h>
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* IRQ Stack Frame Format:
- *
- * Context is always saved/restored in the same way:
- *
- *   (1) stmia rx, {r0-r14}
- *   (2) then the PC and CPSR
- *
- * This results in the following set of indices that
- * can be used to access individual registers in the
- * xcp.regs array:
- */
-
-#define REG_R0              (0)
-#define REG_R1              (1)
-#define REG_R2              (2)
-#define REG_R3              (3)
-#define REG_R4              (4)
-#define REG_R5              (5)
-#define REG_R6              (6)
-#define REG_R7              (7)
-#define REG_R8              (8)
-#define REG_R9              (9)
-#define REG_R10             (10)
-#define REG_R11             (11)
-#define REG_R12             (12)
-#define REG_R13             (13)
-#define REG_R14             (14)
-#define REG_R15             (15)
-#define REG_CPSR            (16)
-
-#define XCPTCONTEXT_REGS    (17)
-#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
-
-#define REG_A1              REG_R0
-#define REG_A2              REG_R1
-#define REG_A3              REG_R2
-#define REG_A4              REG_R3
-#define REG_V1              REG_R4
-#define REG_V2              REG_R5
-#define REG_V3              REG_R6
-#define REG_V4              REG_R7
-#define REG_V5              REG_R8
-#define REG_V6              REG_R9
-#define REG_V7              REG_R10
-#define REG_SB              REG_R9
-#define REG_SL              REG_R10
-#define REG_FP              REG_R11
-#define REG_IP              REG_R12
-#define REG_SP              REG_R13
-#define REG_LR              REG_R14
-#define REG_PC              REG_R15
-
-/* The PIC register is usually R10. It can be R9 is stack checking is enabled
- * or if the user changes it with -mpic-register on the GCC command line.
- */
-
-#define REG_PIC             REG_R10
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/* This struct defines the way the registers are stored.  We
- * need to save:
- *
- *  1	CPSR
- *  7	Static registers, v1-v7 (aka r4-r10)
- *  1	Frame pointer, fp (aka r11)
- *  1	Stack pointer, sp (aka r13)
- *  1	Return address, lr (aka r14)
- * ---
- * 11	(XCPTCONTEXT_USER_REG)
- *
- * On interrupts, we also need to save:
- *  4	Volatile registers, a1-a4 (aka r0-r3)
- *  1	Scratch Register, ip (aka r12)
- *---
- *  5	(XCPTCONTEXT_IRQ_REGS)
- *
- * For a total of 17 (XCPTCONTEXT_REGS)
- */
-
-#ifndef __ASSEMBLY__
-struct xcptcontext
-{
-  /* The following function pointer is non-zero if there
-   * are pending signals to be processed.
-   */
-
-#ifndef CONFIG_DISABLE_SIGNALS
-  void *sigdeliver; /* Actual type is sig_deliver_t */
-
-  /* These are saved copies of LR and CPSR used during
-   * signal processing.
-   */
-
-  uint32_t saved_pc;
-  uint32_t saved_cpsr;
-#endif
-
-  /* Register save area */
-
-  uint32_t regs[XCPTCONTEXT_REGS];
-
-  /* Extra fault address register saved for common paging logic.  In the
-   * case of the prefetch abort, this value is the same as regs[REG_R15];
-   * For the case of the data abort, this value is the value of the fault
-   * address register (FAR) at the time of data abort exception.
-   */
-
-#ifdef CONFIG_PAGING
-  uintptr_t far;
-#endif
-};
-#endif
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* Save the current interrupt enable state & disable IRQs */
-
-static inline irqstate_t irqsave(void)
-{
-  unsigned int flags;
-  unsigned int temp;
-  __asm__ __volatile__
-    (
-     "\tmrs    %0, cpsr\n"
-     "\torr    %1, %0, #128\n"
-     "\tmsr    cpsr_c, %1"
-     : "=r" (flags), "=r" (temp)
-     :
-     : "memory");
-  return flags;
-}
-
-/* Restore saved IRQ & FIQ state */
-
-static inline void irqrestore(irqstate_t flags)
-{
-  __asm__ __volatile__
-    (
-     "msr    cpsr_c, %0"
-     :
-     : "r" (flags)
-     : "memory");
-}
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_ARM_IRQ_H */

arch/arm/include/arm/syscall.h

@@ -1,244 +0,0 @@
-/****************************************************************************
- * arch/arm/include/arm/syscall.h
- *
- *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through include/syscall.h or include/sys/sycall.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARM_SYSCALL_H
-#define __ARCH_ARM_INCLUDE_ARM_SYSCALL_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define SYS_syscall 0x900001
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* SWI with SYS_ call number and no parameters */
-
-static inline uintptr_t sys_call0(unsigned int nbr)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SWI with SYS_ call number and one parameter */
-
-static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SWI with SYS_ call number and two parameters */
-
-static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SWI with SYS_ call number and three parameters */
-
-static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SWI with SYS_ call number and four parameters */
-
-static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SWI with SYS_ call number and five parameters */
-
-static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SWI with SYS_ call number and six parameters */
-
-static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5,
-                                  uintptr_t parm6)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg6 __asm__("r6") = (long)(parm6);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "swi %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_INCLUDE_ARM_SYSCALL_H */
-

arch/arm/include/armv6-m/irq.h

@@ -1,378 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv6-m/irq.h
- *
- *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
-#define __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/irq.h>
-#ifndef __ASSEMBLY__
-#  include <nuttx/compiler.h>
-#  include <stdint.h>
-#endif
-
-#include <arch/chip/chip.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-/* If this is a kernel build, how many nested system calls should we support? */
-
-#ifndef CONFIG_SYS_NNEST
-#  define CONFIG_SYS_NNEST 2
-#endif
-
-/* IRQ Stack Frame Format ***************************************************
- *
- * The following additional registers are stored by the interrupt handling
- * logic.
- */
-
-#define REG_R13             (0)  /* R13 = SP at time of interrupt */
-#define REG_PRIMASK         (1)  /* PRIMASK */
-#define REG_R4              (2)  /* R4 */
-#define REG_R5              (3)  /* R5 */
-#define REG_R6              (4)  /* R6 */
-#define REG_R7              (5)  /* R7 */
-#define REG_R8              (6)  /* R8 */
-#define REG_R9              (7)  /* R9 */
-#define REG_R10             (8)  /* R10 */
-#define REG_R11             (9)  /* R11 */
-
-/* In the kernel build, we may return to either privileged or unprivileged
- * modes.
- */
-
-#ifdef CONFIG_BUILD_PROTECTED
-#  define REG_EXC_RETURN    (10) /* EXC_RETURN */
-#  define SW_XCPT_REGS      (11)
-#else
-#  define SW_XCPT_REGS      (10)
-#endif
-
-/* The total number of registers saved by software */
-
-#define SW_XCPT_SIZE        (4 * SW_XCPT_REGS)
-
-/* On entry into an IRQ, the hardware automatically saves the following
- * registers on the stack in this (address) order:
- */
-
-#define REG_R0              (SW_XCPT_REGS+0) /* R0 */
-#define REG_R1              (SW_XCPT_REGS+1) /* R1 */
-#define REG_R2              (SW_XCPT_REGS+2) /* R2 */
-#define REG_R3              (SW_XCPT_REGS+3) /* R3 */
-#define REG_R12             (SW_XCPT_REGS+4) /* R12 */
-#define REG_R14             (SW_XCPT_REGS+5) /* R14 = LR */
-#define REG_R15             (SW_XCPT_REGS+6) /* R15 = PC */
-#define REG_XPSR            (SW_XCPT_REGS+7) /* xPSR */
-
-#define HW_XCPT_REGS        (8)
-#define HW_XCPT_SIZE        (4 * HW_XCPT_REGS)
-
-#define XCPTCONTEXT_REGS    (HW_XCPT_REGS + SW_XCPT_REGS)
-#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
-
-/* Alternate register names */
-
-#define REG_A1              REG_R0
-#define REG_A2              REG_R1
-#define REG_A3              REG_R2
-#define REG_A4              REG_R3
-#define REG_V1              REG_R4
-#define REG_V2              REG_R5
-#define REG_V3              REG_R6
-#define REG_V4              REG_R7
-#define REG_V5              REG_R8
-#define REG_V6              REG_R9
-#define REG_V7              REG_R10
-#define REG_SB              REG_R9
-#define REG_SL              REG_R10
-#define REG_FP              REG_R11
-#define REG_IP              REG_R12
-#define REG_SP              REG_R13
-#define REG_LR              REG_R14
-#define REG_PC              REG_R15
-
-/* The PIC register is usually R10. It can be R9 is stack checking is enabled
- * or if the user changes it with -mpic-register on the GCC command line.
- */
-
-#define REG_PIC             REG_R10
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* This structure represents the return state from a system call */
-
-#ifdef CONFIG_LIB_SYSCALL
-struct xcpt_syscall_s
-{
-  uint32_t excreturn;   /* The EXC_RETURN value */
-  uint32_t sysreturn;   /* The return PC */
-};
-#endif
-
-/* The following structure is included in the TCB and defines the complete
- * state of the thread.
- */
-
-struct xcptcontext
-{
-#ifndef CONFIG_DISABLE_SIGNALS
-  /* The following function pointer is non-zero if there
-   * are pending signals to be processed.
-   */
-
-  void *sigdeliver; /* Actual type is sig_deliver_t */
-
-  /* These are saved copies of LR, PRIMASK, and xPSR used during
-   * signal processing.
-   */
-
-  uint32_t saved_pc;
-  uint32_t saved_primask;
-  uint32_t saved_xpsr;
-#ifdef CONFIG_BUILD_PROTECTED
-  uint32_t saved_lr;
-#endif
-
-# ifdef CONFIG_BUILD_PROTECTED
-  /* This is the saved address to use when returning from a user-space
-   * signal handler.
-   */
-
-  uint32_t sigreturn;
-
-# endif
-#endif
-
-#ifdef CONFIG_LIB_SYSCALL
-  /* The following array holds the return address and the exc_return value
-   * needed to return from each nested system call.
-   */
-
-  uint8_t nsyscalls;
-  struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
-#endif
-
-  /* Register save area */
-
-  uint32_t regs[XCPTCONTEXT_REGS];
-};
-#endif
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* Get/set the PRIMASK register */
-
-static inline uint8_t getprimask(void) inline_function;
-static inline uint8_t getprimask(void)
-{
-  uint32_t primask;
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, primask\n"
-     : "=r" (primask)
-     :
-     : "memory");
-
-  return (uint8_t)primask;
-}
-
-static inline void setprimask(uint32_t primask) inline_function;
-static inline void setprimask(uint32_t primask)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr primask, %0\n"
-      :
-      : "r" (primask)
-      : "memory");
-}
-
-/* Disable IRQs */
-
-static inline void irqdisable(void) inline_function;
-static inline void irqdisable(void)
-{
-  __asm__ __volatile__ ("\tcpsid  i\n");
-}
-
-/* Save the current primask state & disable IRQs */
-
-static inline irqstate_t irqsave(void) inline_function;
-static inline irqstate_t irqsave(void)
-{
-  unsigned short primask;
-
-  /* Return the current value of primask register and set
-   * bit 0 of the primask register to disable interrupts
-   */
-
-  __asm__ __volatile__
-    (
-     "\tmrs    %0, primask\n"
-     "\tcpsid  i\n"
-     : "=r" (primask)
-     :
-     : "memory");
-
-  return primask;
-}
-
-/* Enable IRQs */
-
-static inline void irqenable(void) inline_function;
-static inline void irqenable(void)
-{
-  __asm__ __volatile__ ("\tcpsie  i\n");
-}
-
-/* Restore saved primask state */
-
-static inline void irqrestore(irqstate_t flags) inline_function;
-static inline void irqrestore(irqstate_t flags)
-{
-  /* If bit 0 of the primask is 0, then we need to restore
-   * interrupts.
-   */
-
-  __asm__ __volatile__
-    (
-      "\tmsr primask, %0\n"
-      :
-      : "r" (flags)
-      : "memory");
-}
-
-/* Get/set IPSR */
-
-static inline uint32_t getipsr(void) inline_function;
-static inline uint32_t getipsr(void)
-{
-  uint32_t ipsr;
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, ipsr\n"
-     : "=r" (ipsr)
-     :
-     : "memory");
-
-  return ipsr;
-}
-
-static inline void setipsr(uint32_t ipsr) inline_function;
-static inline void setipsr(uint32_t ipsr)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr ipsr, %0\n"
-      :
-      : "r" (ipsr)
-      : "memory");
-}
-
-/* Get/set CONTROL */
-
-static inline uint32_t getcontrol(void) inline_function;
-static inline uint32_t getcontrol(void)
-{
-  uint32_t control;
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, control\n"
-     : "=r" (control)
-     :
-     : "memory");
-
-  return control;
-}
-
-static inline void setcontrol(uint32_t control) inline_function;
-static inline void setcontrol(uint32_t control)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr control, %0\n"
-      :
-      : "r" (control)
-      : "memory");
-}
-
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H */
-

arch/arm/include/armv6-m/syscall.h

@@ -1,267 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv6-m/syscall.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through include/syscall.h or include/sys/sycall.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H
-#define __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* This is the value used as the argument to the SVC instruction.  It is not
- * used.
- */
-
-#define SYS_syscall 0x00
-
-/* The SYS_signal_handler_return is executed here... its value is not always
- * available in this context and so is assumed to be 7.
- */
-
-#ifndef SYS_signal_handler_return
-#  define SYS_signal_handler_return (7)
-#elif SYS_signal_handler_return != 7
-#  error "SYS_signal_handler_return was assumed to be 7"
-#endif
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* SVC call with SYS_ call number and no parameters */
-
-static inline uintptr_t sys_call0(unsigned int nbr)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and one parameter */
-
-static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and two parameters */
-
-static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and three parameters */
-
-static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and four parameters.
- *
- * NOTE the nonstandard parameter passing:  parm4 is in R4
- */
-
-static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and five parameters.
- *
- * NOTE the nonstandard parameter passing:  parm4 and parm5 are in R4 and R5
- */
-
-static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and six parameters.
- *
- * NOTE the nonstandard parameter passing:  parm4-parm6 are in R4-R6
- */
-
-static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5,
-                                  uintptr_t parm6)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg6 __asm__("r6") = (long)(parm6);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H */
-

arch/arm/include/armv7-a/irq.h

@@ -1,412 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv7-a/irq.h
- *
- *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_IRQ_H
-#define __ARCH_ARM_INCLUDE_ARMV7_A_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/irq.h>
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#  include <arch/arch.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* IRQ Stack Frame Format:
- *
- * Context is always saved/restored in the same way:
- *
- *   (1) stmia rx, {r0-r14}
- *   (2) then the PC and CPSR
- *
- * This results in the following set of indices that can be used to access
- * individual registers in the xcp.regs array:
- */
-
-#define REG_R0              (0)
-#define REG_R1              (1)
-#define REG_R2              (2)
-#define REG_R3              (3)
-#define REG_R4              (4)
-#define REG_R5              (5)
-#define REG_R6              (6)
-#define REG_R7              (7)
-#define REG_R8              (8)
-#define REG_R9              (9)
-#define REG_R10             (10)
-#define REG_R11             (11)
-#define REG_R12             (12)
-#define REG_R13             (13)
-#define REG_R14             (14)
-#define REG_R15             (15)
-#define REG_CPSR            (16)
-
-#define ARM_CONTEXT_REGS    (17)
-
-/* If the MCU supports a floating point unit, then it will be necessary
- * to save the state of the FPU status register and data registers on
- * each context switch.  These registers are not saved during interrupt
- * level processing, however. So, as a consequence, floating point
- * operations may NOT be performed in interrupt handlers.
- *
- * The FPU provides an extension register file containing 32 single-
- * precision registers. These can be viewed as:
- *
- * - Sixteen 64-bit double word registers, D0-D15
- * - Thirty-two 32-bit single-word registers, S0-S31
- *   S<2n> maps to the least significant half of D<n>
- *   S<2n+1> maps to the most significant half of D<n>.
- */
-
-#ifdef CONFIG_ARCH_FPU
-#  define REG_D0            (ARM_CONTEXT_REGS+0)  /* D0 */
-#  define REG_S0            (ARM_CONTEXT_REGS+0)  /* S0 */
-#  define REG_S1            (ARM_CONTEXT_REGS+1)  /* S1 */
-#  define REG_D1            (ARM_CONTEXT_REGS+2)  /* D1 */
-#  define REG_S2            (ARM_CONTEXT_REGS+2)  /* S2 */
-#  define REG_S3            (ARM_CONTEXT_REGS+3)  /* S3 */
-#  define REG_D2            (ARM_CONTEXT_REGS+4)  /* D2 */
-#  define REG_S4            (ARM_CONTEXT_REGS+4)  /* S4 */
-#  define REG_S5            (ARM_CONTEXT_REGS+5)  /* S5 */
-#  define REG_D3            (ARM_CONTEXT_REGS+6)  /* D3 */
-#  define REG_S6            (ARM_CONTEXT_REGS+6)  /* S6 */
-#  define REG_S7            (ARM_CONTEXT_REGS+7)  /* S7 */
-#  define REG_D4            (ARM_CONTEXT_REGS+8)  /* D4 */
-#  define REG_S8            (ARM_CONTEXT_REGS+8)  /* S8 */
-#  define REG_S9            (ARM_CONTEXT_REGS+9)  /* S9 */
-#  define REG_D5            (ARM_CONTEXT_REGS+10) /* D5 */
-#  define REG_S10           (ARM_CONTEXT_REGS+10) /* S10 */
-#  define REG_S11           (ARM_CONTEXT_REGS+11) /* S11 */
-#  define REG_D6            (ARM_CONTEXT_REGS+12) /* D6 */
-#  define REG_S12           (ARM_CONTEXT_REGS+12) /* S12 */
-#  define REG_S13           (ARM_CONTEXT_REGS+13) /* S13 */
-#  define REG_D7            (ARM_CONTEXT_REGS+14) /* D7 */
-#  define REG_S14           (ARM_CONTEXT_REGS+14) /* S14 */
-#  define REG_S15           (ARM_CONTEXT_REGS+15) /* S15 */
-#  define REG_D8            (ARM_CONTEXT_REGS+16) /* D8 */
-#  define REG_S16           (ARM_CONTEXT_REGS+16) /* S16 */
-#  define REG_S17           (ARM_CONTEXT_REGS+17) /* S17 */
-#  define REG_D9            (ARM_CONTEXT_REGS+18) /* D9 */
-#  define REG_S18           (ARM_CONTEXT_REGS+18) /* S18 */
-#  define REG_S19           (ARM_CONTEXT_REGS+19) /* S19 */
-#  define REG_D10           (ARM_CONTEXT_REGS+20) /* D10 */
-#  define REG_S20           (ARM_CONTEXT_REGS+20) /* S20 */
-#  define REG_S21           (ARM_CONTEXT_REGS+21) /* S21 */
-#  define REG_D11           (ARM_CONTEXT_REGS+22) /* D11 */
-#  define REG_S22           (ARM_CONTEXT_REGS+22) /* S22 */
-#  define REG_S23           (ARM_CONTEXT_REGS+23) /* S23 */
-#  define REG_D12           (ARM_CONTEXT_REGS+24) /* D12 */
-#  define REG_S24           (ARM_CONTEXT_REGS+24) /* S24 */
-#  define REG_S25           (ARM_CONTEXT_REGS+25) /* S25 */
-#  define REG_D13           (ARM_CONTEXT_REGS+26) /* D13 */
-#  define REG_S26           (ARM_CONTEXT_REGS+26) /* S26 */
-#  define REG_S27           (ARM_CONTEXT_REGS+27) /* S27 */
-#  define REG_D14           (ARM_CONTEXT_REGS+28) /* D14 */
-#  define REG_S28           (ARM_CONTEXT_REGS+28) /* S28 */
-#  define REG_S29           (ARM_CONTEXT_REGS+29) /* S29 */
-#  define REG_D15           (ARM_CONTEXT_REGS+30) /* D15 */
-#  define REG_S30           (ARM_CONTEXT_REGS+30) /* S30 */
-#  define REG_S31           (ARM_CONTEXT_REGS+31) /* S31 */
-#  define REG_FPSCR         (ARM_CONTEXT_REGS+32) /* Floating point status and control */
-#  define FPU_CONTEXT_REGS  (33)
-#else
-#  define FPU_CONTEXT_REGS  (0)
-#endif
-
-/* The total number of registers saved by software */
-
-#define XCPTCONTEXT_REGS    (ARM_CONTEXT_REGS + FPU_CONTEXT_REGS)
-#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
-
-/* Friendly register names */
-
-#define REG_A1              REG_R0
-#define REG_A2              REG_R1
-#define REG_A3              REG_R2
-#define REG_A4              REG_R3
-#define REG_V1              REG_R4
-#define REG_V2              REG_R5
-#define REG_V3              REG_R6
-#define REG_V4              REG_R7
-#define REG_V5              REG_R8
-#define REG_V6              REG_R9
-#define REG_V7              REG_R10
-#define REG_SB              REG_R9
-#define REG_SL              REG_R10
-#define REG_FP              REG_R11
-#define REG_IP              REG_R12
-#define REG_SP              REG_R13
-#define REG_LR              REG_R14
-#define REG_PC              REG_R15
-
-/* The PIC register is usually R10. It can be R9 is stack checking is enabled
- * or if the user changes it with -mpic-register on the GCC command line.
- */
-
-#define REG_PIC             REG_R10
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* This structure represents the return state from a system call */
-
-#ifdef CONFIG_LIB_SYSCALL
-struct xcpt_syscall_s
-{
-#ifdef CONFIG_BUILD_KERNEL
-  uint32_t cpsr;        /* The CPSR value */
-#endif
-  uint32_t sysreturn;   /* The return PC */
-};
-#endif
-
-/* This struct defines the way the registers are stored.  We need to save:
- *
- *  1  CPSR
- *  7  Static registers, v1-v7 (aka r4-r10)
- *  1  Frame pointer, fp (aka r11)
- *  1  Stack pointer, sp (aka r13)
- *  1  Return address, lr (aka r14)
- * ---
- * 11  (XCPTCONTEXT_USER_REG)
- *
- * On interrupts, we also need to save:
- *  4  Volatile registers, a1-a4 (aka r0-r3)
- *  1  Scratch Register, ip (aka r12)
- *---
- *  5  (XCPTCONTEXT_IRQ_REGS)
- *
- * For a total of 17 (XCPTCONTEXT_REGS)
- */
-
-#ifndef __ASSEMBLY__
-struct xcptcontext
-{
-  /* The following function pointer is non-zero if there are pending signals
-   * to be processed.
-   */
-
-#ifndef CONFIG_DISABLE_SIGNALS
-  void *sigdeliver; /* Actual type is sig_deliver_t */
-
-  /* These are saved copies of LR and CPSR used during signal processing. */
-
-  uint32_t saved_pc;
-  uint32_t saved_cpsr;
-
-# ifdef CONFIG_BUILD_KERNEL
-  /* This is the saved address to use when returning from a user-space
-   * signal handler.
-   */
-
-  uint32_t sigreturn;
-
-# endif
-#endif
-
-  /* Register save area */
-
-  uint32_t regs[XCPTCONTEXT_REGS];
-
-  /* Extra fault address register saved for common paging logic.  In the
-   * case of the pre-fetch abort, this value is the same as regs[REG_R15];
-   * For the case of the data abort, this value is the value of the fault
-   * address register (FAR) at the time of data abort exception.
-   */
-
-#ifdef CONFIG_PAGING
-  uintptr_t far;
-#endif
-
-#ifdef CONFIG_LIB_SYSCALL
-  /* The following array holds the return address and the exc_return value
-   * needed to return from each nested system call.
-   */
-
-  uint8_t nsyscalls;
-  struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
-#endif
-
-#ifdef CONFIG_ARCH_ADDRENV
-#ifdef CONFIG_ARCH_STACK_DYNAMIC
-  /* This array holds the physical address of the level 2 page table used
-   * to map the thread's stack memory.  This array will be initially of
-   * zeroed and would be back-up up with pages during page fault exception
-   * handling to support dynamically sized stacks for each thread.
-   */
-
-  FAR uintptr_t *ustack[ARCH_STACK_NSECTS];
-#endif
-
-#ifdef CONFIG_ARCH_KERNEL_STACK
-  /* In this configuration, all syscalls execute from an internal kernel
-   * stack.  Why?  Because when we instantiate and initialize the address
-   * environment of the new user process, we will temporarily lose the
-   * address environment of the old user process, including its stack
-   * contents.  The kernel C logic will crash immediately with no valid
-   * stack in place.
-   */
-
-  FAR uint32_t *ustkptr;  /* Saved user stack pointer */
-  FAR uint32_t *kstack;   /* Allocate base of the (aligned) kernel stack */
-#ifndef CONFIG_DISABLE_SIGNALS
-  FAR uint32_t *kstkptr;  /* Saved kernel stack pointer */
-#endif
-#endif
-#endif
-};
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* Return the current IRQ state */
-
-static inline irqstate_t irqstate(void)
-{
-  unsigned int cpsr;
-
-  __asm__ __volatile__
-    (
-      "\tmrs    %0, cpsr\n"
-      : "=r" (cpsr)
-      :
-      : "memory"
-    );
-
-  return cpsr;
-}
-
-/* Disable IRQs and return the previous IRQ state */
-
-static inline irqstate_t irqsave(void)
-{
-  unsigned int cpsr;
-
-  __asm__ __volatile__
-    (
-      "\tmrs    %0, cpsr\n"
-      "\tcpsid  i\n"
-#if defined(CONFIG_ARMV7A_DECODEFIQ)
-      "\tcpsid  f\n"
-#endif
-      : "=r" (cpsr)
-      :
-      : "memory"
-    );
-
-  return cpsr;
-}
-
-/* Enable IRQs and return the previous IRQ state */
-
-static inline irqstate_t irqenable(void)
-{
-  unsigned int cpsr;
-
-  __asm__ __volatile__
-    (
-      "\tmrs    %0, cpsr\n"
-      "\tcpsie  i\n"
-#if defined(CONFIG_ARMV7A_DECODEFIQ)
-      "\tcpsie  f\n"
-#endif
-      : "=r" (cpsr)
-      :
-      : "memory"
-    );
-
-  return cpsr;
-}
-
-/* Restore saved IRQ & FIQ state */
-
-static inline void irqrestore(irqstate_t flags)
-{
-  __asm__ __volatile__
-    (
-      "msr    cpsr_c, %0"
-      :
-      : "r" (flags)
-      : "memory"
-    );
-}
-
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_IRQ_H */

arch/arm/include/armv7-a/syscall.h

@@ -1,243 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv-7a/syscall.h
- *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through include/syscall.h or include/sys/sycall.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H
-#define __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define SYS_syscall 0x900001
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* SVC with SYS_ call number and no parameters */
-
-static inline uintptr_t sys_call0(unsigned int nbr)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SVC with SYS_ call number and one parameter */
-
-static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SVC with SYS_ call number and two parameters */
-
-static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SVC with SYS_ call number and three parameters */
-
-static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SVC with SYS_ call number and four parameters */
-
-static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SVC with SYS_ call number and five parameters */
-
-static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/* SVC with SYS_ call number and six parameters */
-
-static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5,
-                                  uintptr_t parm6)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg6 __asm__("r6") = (long)(parm6);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
-    : "memory", "r14"
-  );
-
-  return reg0;
-}
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H */

arch/arm/include/armv7-m/irq.h

@@ -1,394 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv7-m/irq.h
- *
- *   Copyright (C) 2009, 2011-2012, 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
-#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/irq.h>
-#ifndef __ASSEMBLY__
-#  include <nuttx/compiler.h>
-#  include <stdint.h>
-#endif
-
-/* Included implementation-dependent register save structure layouts */
-
-#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)
-#  include <arch/armv7-m/irq_cmnvector.h>
-#else
-#  include <arch/armv7-m/irq_lazyfpu.h>
-#endif
-
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-#  include <arch/chip/chip.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-/* If this is a kernel build, how many nested system calls should we support? */
-
-#ifndef CONFIG_SYS_NNEST
-#  define CONFIG_SYS_NNEST 2
-#endif
-
-/* Alternate register names *************************************************/
-
-#define REG_A1              REG_R0
-#define REG_A2              REG_R1
-#define REG_A3              REG_R2
-#define REG_A4              REG_R3
-#define REG_V1              REG_R4
-#define REG_V2              REG_R5
-#define REG_V3              REG_R6
-#define REG_V4              REG_R7
-#define REG_V5              REG_R8
-#define REG_V6              REG_R9
-#define REG_V7              REG_R10
-#define REG_SB              REG_R9
-#define REG_SL              REG_R10
-#define REG_FP              REG_R11
-#define REG_IP              REG_R12
-#define REG_SP              REG_R13
-#define REG_LR              REG_R14
-#define REG_PC              REG_R15
-
-/* The PIC register is usually R10. It can be R9 is stack checking is enabled
- * or if the user changes it with -mpic-register on the GCC command line.
- */
-
-#define REG_PIC             REG_R10
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-#ifndef __ASSEMBLY__
-
-/* This structure represents the return state from a system call */
-
-#ifdef CONFIG_LIB_SYSCALL
-struct xcpt_syscall_s
-{
-  uint32_t excreturn;   /* The EXC_RETURN value */
-  uint32_t sysreturn;   /* The return PC */
-};
-#endif
-
-/* The following structure is included in the TCB and defines the complete
- * state of the thread.
- */
-
-struct xcptcontext
-{
-#ifndef CONFIG_DISABLE_SIGNALS
-  /* The following function pointer is non-zero if there
-   * are pending signals to be processed.
-   */
-
-  void *sigdeliver; /* Actual type is sig_deliver_t */
-
-  /* These are saved copies of LR, PRIMASK, and xPSR used during
-   * signal processing.
-   */
-
-  uint32_t saved_pc;
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-  uint32_t saved_basepri;
-#else
-  uint32_t saved_primask;
-#endif
-  uint32_t saved_xpsr;
-#ifdef CONFIG_BUILD_PROTECTED
-  uint32_t saved_lr;
-#endif
-
-# ifdef CONFIG_BUILD_PROTECTED
-  /* This is the saved address to use when returning from a user-space
-   * signal handler.
-   */
-
-  uint32_t sigreturn;
-
-# endif
-#endif
-
-#ifdef CONFIG_LIB_SYSCALL
-  /* The following array holds the return address and the exc_return value
-   * needed to return from each nested system call.
-   */
-
-  uint8_t nsyscalls;
-  struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
-
-#endif
-
-  /* Register save area */
-
-  uint32_t regs[XCPTCONTEXT_REGS];
-};
-#endif
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* Get/set the PRIMASK register */
-
-static inline uint8_t getprimask(void) inline_function;
-static inline uint8_t getprimask(void)
-{
-  uint32_t primask;
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, primask\n"
-     : "=r" (primask)
-     :
-     : "memory");
-
-  return (uint8_t)primask;
-}
-
-static inline void setprimask(uint32_t primask) inline_function;
-static inline void setprimask(uint32_t primask)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr primask, %0\n"
-      :
-      : "r" (primask)
-      : "memory");
-}
-
-/* Get/set the BASEPRI register.  The BASEPRI register defines the minimum
- * priority for exception processing. When BASEPRI is set to a nonzero
- * value, it prevents the activation of all exceptions with the same or
- * lower priority level as the BASEPRI value.
- */
-
-static inline uint8_t getbasepri(void) inline_function;
-static inline uint8_t getbasepri(void)
-{
-  uint32_t basepri;
-
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, basepri\n"
-     : "=r" (basepri)
-     :
-     : "memory");
-
-  return (uint8_t)basepri;
-}
-
-static inline void setbasepri(uint32_t basepri) inline_function;
-static inline void setbasepri(uint32_t basepri)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr basepri, %0\n"
-      :
-      : "r" (basepri)
-      : "memory");
-}
-
-/* Disable IRQs */
-
-static inline void irqdisable(void) inline_function;
-static inline void irqdisable(void)
-{
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-  setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
-#else
-  __asm__ __volatile__ ("\tcpsid  i\n");
-#endif
-}
-
-/* Save the current primask state & disable IRQs */
-
-static inline irqstate_t irqsave(void) inline_function;
-static inline irqstate_t irqsave(void)
-{
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-
-  uint8_t basepri = getbasepri();
-  setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
-  return (irqstate_t)basepri;
-
-#else
-
-  unsigned short primask;
-
-  /* Return the current value of primask register and set
-   * bit 0 of the primask register to disable interrupts
-   */
-
-  __asm__ __volatile__
-    (
-     "\tmrs    %0, primask\n"
-     "\tcpsid  i\n"
-     : "=r" (primask)
-     :
-     : "memory");
-
-  return primask;
-#endif
-}
-
-/* Enable IRQs */
-
-static inline void irqenable(void) inline_function;
-static inline void irqenable(void)
-{
-  setbasepri(0);
-  __asm__ __volatile__ ("\tcpsie  i\n");
-}
-
-/* Restore saved primask state */
-
-static inline void irqrestore(irqstate_t flags) inline_function;
-static inline void irqrestore(irqstate_t flags)
-{
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-  setbasepri((uint32_t)flags);
-#else
-  /* If bit 0 of the primask is 0, then we need to restore
-   * interrupts.
-   */
-
-  __asm__ __volatile__
-    (
-      "\ttst    %0, #1\n"
-      "\tbne.n  1f\n"
-      "\tcpsie  i\n"
-      "1:\n"
-      :
-      : "r" (flags)
-      : "memory");
-#endif
-}
-
-/* Get/set IPSR */
-
-static inline uint32_t getipsr(void) inline_function;
-static inline uint32_t getipsr(void)
-{
-  uint32_t ipsr;
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, ipsr\n"
-     : "=r" (ipsr)
-     :
-     : "memory");
-
-  return ipsr;
-}
-
-static inline void setipsr(uint32_t ipsr) inline_function;
-static inline void setipsr(uint32_t ipsr)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr ipsr, %0\n"
-      :
-      : "r" (ipsr)
-      : "memory");
-}
-
-/* Get/set CONTROL */
-
-static inline uint32_t getcontrol(void) inline_function;
-static inline uint32_t getcontrol(void)
-{
-  uint32_t control;
-  __asm__ __volatile__
-    (
-     "\tmrs  %0, control\n"
-     : "=r" (control)
-     :
-     : "memory");
-
-  return control;
-}
-
-static inline void setcontrol(uint32_t control) inline_function;
-static inline void setcontrol(uint32_t control)
-{
-  __asm__ __volatile__
-    (
-      "\tmsr control, %0\n"
-      :
-      : "r" (control)
-      : "memory");
-}
-
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H */
-

arch/arm/include/armv7-m/irq_cmnvector.h

@@ -1,168 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv7-m/irq_cmnvector.h
- *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H
-#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* IRQ Stack Frame Format: */
-
-/* The following additional registers are stored by the interrupt handling
- * logic.
- */
-
-#define REG_R13             (0)  /* R13 = SP at time of interrupt */
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-#  define REG_BASEPRI       (1)  /* BASEPRI */
-#else
-#  define REG_PRIMASK       (1)  /* PRIMASK */
-#endif
-#define REG_R4              (2)  /* R4 */
-#define REG_R5              (3)  /* R5 */
-#define REG_R6              (4)  /* R6 */
-#define REG_R7              (5)  /* R7 */
-#define REG_R8              (6)  /* R8 */
-#define REG_R9              (7)  /* R9 */
-#define REG_R10             (8)  /* R10 */
-#define REG_R11             (9)  /* R11 */
-#define REG_EXC_RETURN      (10) /* EXC_RETURN */
-#define SW_INT_REGS         (11)
-
-#ifdef CONFIG_ARCH_FPU
-
-/* If the MCU supports a floating point unit, then it will be necessary
- * to save the state of the non-volatile registers before calling code
- * that may save and overwrite them.
- */
-
-#  define REG_S16           (SW_INT_REGS+0) /* S16 */
-#  define REG_S17           (SW_INT_REGS+1) /* S17 */
-#  define REG_S18           (SW_INT_REGS+2) /* S18 */
-#  define REG_S19           (SW_INT_REGS+3) /* S19 */
-#  define REG_S20           (SW_INT_REGS+4) /* S20 */
-#  define REG_S21           (SW_INT_REGS+5) /* S21 */
-#  define REG_S22           (SW_INT_REGS+6) /* S22 */
-#  define REG_S23           (SW_INT_REGS+7) /* S23 */
-#  define REG_S24           (SW_INT_REGS+8) /* S24 */
-#  define REG_S25           (SW_INT_REGS+9) /* S25 */
-#  define REG_S26           (SW_INT_REGS+10) /* S26 */
-#  define REG_S27           (SW_INT_REGS+11) /* S27 */
-#  define REG_S28           (SW_INT_REGS+12) /* S28 */
-#  define REG_S29           (SW_INT_REGS+13) /* S29 */
-#  define REG_S30           (SW_INT_REGS+14) /* S30 */
-#  define REG_S31           (SW_INT_REGS+15) /* S31 */
-#  define SW_FPU_REGS       (16)
-#else
-#  define SW_FPU_REGS       (0)
-#endif
-
-/* The total number of registers saved by software */
-
-#define SW_XCPT_REGS        (SW_INT_REGS + SW_FPU_REGS)
-#define SW_XCPT_SIZE        (4 * SW_XCPT_REGS)
-
-/* On entry into an IRQ, the hardware automatically saves the following
- * registers on the stack in this (address) order:
- */
-
-#define REG_R0              (SW_XCPT_REGS+0) /* R0 */
-#define REG_R1              (SW_XCPT_REGS+1) /* R1 */
-#define REG_R2              (SW_XCPT_REGS+2) /* R2 */
-#define REG_R3              (SW_XCPT_REGS+3) /* R3 */
-#define REG_R12             (SW_XCPT_REGS+4) /* R12 */
-#define REG_R14             (SW_XCPT_REGS+5) /* R14 = LR */
-#define REG_R15             (SW_XCPT_REGS+6) /* R15 = PC */
-#define REG_XPSR            (SW_XCPT_REGS+7) /* xPSR */
-#define HW_INT_REGS         (8)
-
-#ifdef CONFIG_ARCH_FPU
-
-/* If the FPU is enabled, the hardware also saves the volatile FP registers.
- */
-
-#  define REG_S0            (SW_XCPT_REGS+8)  /* S0 */
-#  define REG_S1            (SW_XCPT_REGS+9)  /* S1 */
-#  define REG_S2            (SW_XCPT_REGS+10) /* S2 */
-#  define REG_S3            (SW_XCPT_REGS+11) /* S3 */
-#  define REG_S4            (SW_XCPT_REGS+12) /* S4 */
-#  define REG_S5            (SW_XCPT_REGS+13) /* S5 */
-#  define REG_S6            (SW_XCPT_REGS+14) /* S6 */
-#  define REG_S7            (SW_XCPT_REGS+15) /* S7 */
-#  define REG_S8            (SW_XCPT_REGS+16) /* S8 */
-#  define REG_S9            (SW_XCPT_REGS+17) /* S9 */
-#  define REG_S10           (SW_XCPT_REGS+18) /* S10 */
-#  define REG_S11           (SW_XCPT_REGS+19) /* S11 */
-#  define REG_S12           (SW_XCPT_REGS+20) /* S12 */
-#  define REG_S13           (SW_XCPT_REGS+21) /* S13 */
-#  define REG_S14           (SW_XCPT_REGS+22) /* S14 */
-#  define REG_S15           (SW_XCPT_REGS+23) /* S15 */
-#  define REG_FPSCR         (SW_XCPT_REGS+24) /* FPSCR */
-#  define REG_FPReserved    (SW_XCPT_REGS+25) /* Reserved */
-#  define HW_FPU_REGS       (18)
-#else
-#  define HW_FPU_REGS       (0)
-#endif
-
-#define HW_XCPT_REGS        (HW_INT_REGS + HW_FPU_REGS)
-#define HW_XCPT_SIZE        (4 * HW_XCPT_REGS)
-
-#define XCPTCONTEXT_REGS    (HW_XCPT_REGS + SW_XCPT_REGS)
-#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H */
-

arch/arm/include/armv7-m/irq_lazyfpu.h

@@ -1,186 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv7-m/irq_lazyfpu.h
- *
- *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H
-#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* IRQ Stack Frame Format: */
-
-/* The following additional registers are stored by the interrupt handling
- * logic.
- */
-
-#define REG_R13             (0)  /* R13 = SP at time of interrupt */
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-#  define REG_BASEPRI       (1)  /* BASEPRI */
-#else
-#  define REG_PRIMASK       (1)  /* PRIMASK */
-#endif
-#define REG_R4              (2)  /* R4 */
-#define REG_R5              (3)  /* R5 */
-#define REG_R6              (4)  /* R6 */
-#define REG_R7              (5)  /* R7 */
-#define REG_R8              (6)  /* R8 */
-#define REG_R9              (7)  /* R9 */
-#define REG_R10             (8)  /* R10 */
-#define REG_R11             (9)  /* R11 */
-
-#ifdef CONFIG_BUILD_PROTECTED
-#  define REG_EXC_RETURN    (10) /* EXC_RETURN */
-#  define SW_INT_REGS       (11)
-#else
-#  define SW_INT_REGS       (10)
-#endif
-
-/* If the MCU supports a floating point unit, then it will be necessary
- * to save the state of the FPU status register and data registers on
- * each context switch.  These registers are not saved during interrupt
- * level processing, however. So, as a consequence, floating point
- * operations may NOT be performed in interrupt handlers.
- *
- * The FPU provides an extension register file containing 32 single-
- * precision registers. These can be viewed as:
- *
- * - Sixteen 64-bit doubleword registers, D0-D15
- * - Thirty-two 32-bit single-word registers, S0-S31
- *   S<2n> maps to the least significant half of D<n>
- *   S<2n+1> maps to the most significant half of D<n>.
- */
-
-#ifdef CONFIG_ARCH_FPU
-#  define REG_D0            (SW_INT_REGS+0)  /* D0 */
-#  define REG_S0            (SW_INT_REGS+0)  /* S0 */
-#  define REG_S1            (SW_INT_REGS+1)  /* S1 */
-#  define REG_D1            (SW_INT_REGS+2)  /* D1 */
-#  define REG_S2            (SW_INT_REGS+2)  /* S2 */
-#  define REG_S3            (SW_INT_REGS+3)  /* S3 */
-#  define REG_D2            (SW_INT_REGS+4)  /* D2 */
-#  define REG_S4            (SW_INT_REGS+4)  /* S4 */
-#  define REG_S5            (SW_INT_REGS+5)  /* S5 */
-#  define REG_D3            (SW_INT_REGS+6)  /* D3 */
-#  define REG_S6            (SW_INT_REGS+6)  /* S6 */
-#  define REG_S7            (SW_INT_REGS+7)  /* S7 */
-#  define REG_D4            (SW_INT_REGS+8)  /* D4 */
-#  define REG_S8            (SW_INT_REGS+8)  /* S8 */
-#  define REG_S9            (SW_INT_REGS+9)  /* S9 */
-#  define REG_D5            (SW_INT_REGS+10) /* D5 */
-#  define REG_S10           (SW_INT_REGS+10) /* S10 */
-#  define REG_S11           (SW_INT_REGS+11) /* S11 */
-#  define REG_D6            (SW_INT_REGS+12) /* D6 */
-#  define REG_S12           (SW_INT_REGS+12) /* S12 */
-#  define REG_S13           (SW_INT_REGS+13) /* S13 */
-#  define REG_D7            (SW_INT_REGS+14) /* D7 */
-#  define REG_S14           (SW_INT_REGS+14) /* S14 */
-#  define REG_S15           (SW_INT_REGS+15) /* S15 */
-#  define REG_D8            (SW_INT_REGS+16) /* D8 */
-#  define REG_S16           (SW_INT_REGS+16) /* S16 */
-#  define REG_S17           (SW_INT_REGS+17) /* S17 */
-#  define REG_D9            (SW_INT_REGS+18) /* D9 */
-#  define REG_S18           (SW_INT_REGS+18) /* S18 */
-#  define REG_S19           (SW_INT_REGS+19) /* S19 */
-#  define REG_D10           (SW_INT_REGS+20) /* D10 */
-#  define REG_S20           (SW_INT_REGS+20) /* S20 */
-#  define REG_S21           (SW_INT_REGS+21) /* S21 */
-#  define REG_D11           (SW_INT_REGS+22) /* D11 */
-#  define REG_S22           (SW_INT_REGS+22) /* S22 */
-#  define REG_S23           (SW_INT_REGS+23) /* S23 */
-#  define REG_D12           (SW_INT_REGS+24) /* D12 */
-#  define REG_S24           (SW_INT_REGS+24) /* S24 */
-#  define REG_S25           (SW_INT_REGS+25) /* S25 */
-#  define REG_D13           (SW_INT_REGS+26) /* D13 */
-#  define REG_S26           (SW_INT_REGS+26) /* S26 */
-#  define REG_S27           (SW_INT_REGS+27) /* S27 */
-#  define REG_D14           (SW_INT_REGS+28) /* D14 */
-#  define REG_S28           (SW_INT_REGS+28) /* S28 */
-#  define REG_S29           (SW_INT_REGS+29) /* S29 */
-#  define REG_D15           (SW_INT_REGS+30) /* D15 */
-#  define REG_S30           (SW_INT_REGS+30) /* S30 */
-#  define REG_S31           (SW_INT_REGS+31) /* S31 */
-#  define REG_FPSCR         (SW_INT_REGS+32) /* Floating point status and control */
-#  define SW_FPU_REGS       (33)
-#else
-#  define SW_FPU_REGS       (0)
-#endif
-
-/* The total number of registers saved by software */
-
-#define SW_XCPT_REGS        (SW_INT_REGS + SW_FPU_REGS)
-#define SW_XCPT_SIZE        (4 * SW_XCPT_REGS)
-
-/* On entry into an IRQ, the hardware automatically saves the following
- * registers on the stack in this (address) order:
- */
-
-#define REG_R0              (SW_XCPT_REGS+0) /* R0 */
-#define REG_R1              (SW_XCPT_REGS+1) /* R1 */
-#define REG_R2              (SW_XCPT_REGS+2) /* R2 */
-#define REG_R3              (SW_XCPT_REGS+3) /* R3 */
-#define REG_R12             (SW_XCPT_REGS+4) /* R12 */
-#define REG_R14             (SW_XCPT_REGS+5) /* R14 = LR */
-#define REG_R15             (SW_XCPT_REGS+6) /* R15 = PC */
-#define REG_XPSR            (SW_XCPT_REGS+7) /* xPSR */
-
-#define HW_XCPT_REGS        (8)
-#define HW_XCPT_SIZE        (4 * HW_XCPT_REGS)
-
-#define XCPTCONTEXT_REGS    (HW_XCPT_REGS + SW_XCPT_REGS)
-#define XCPTCONTEXT_SIZE    (HW_XCPT_SIZE + SW_XCPT_SIZE)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H */
-

arch/arm/include/armv7-m/syscall.h

@@ -1,267 +0,0 @@
-/****************************************************************************
- * arch/arm/include/armv7-m/syscall.h
- *
- *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through include/syscall.h or include/sys/sycall.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
-#define __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* This is the value used as the argument to the SVC instruction.  It is not
- * used.
- */
-
-#define SYS_syscall 0x00
-
-/* The SYS_signal_handler_return is executed here... its value is not always
- * available in this context and so is assumed to be 7.
- */
-
-#ifndef SYS_signal_handler_return
-#  define SYS_signal_handler_return (7)
-#elif SYS_signal_handler_return != 7
-#  error "SYS_signal_handler_return was assumed to be 7"
-#endif
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* SVC call with SYS_ call number and no parameters */
-
-static inline uintptr_t sys_call0(unsigned int nbr)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and one parameter */
-
-static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and two parameters */
-
-static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and three parameters */
-
-static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and four parameters.
- *
- * NOTE the nonstandard parameter passing:  parm4 is in R4
- */
-
-static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and five parameters.
- *
- * NOTE the nonstandard parameter passing:  parm4 and parm5 are in R4 and R5
- */
-
-static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/* SVC call with SYS_ call number and six parameters.
- *
- * NOTE the nonstandard parameter passing:  parm4-parm6 are in R4-R6
- */
-
-static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
-                                  uintptr_t parm2, uintptr_t parm3,
-                                  uintptr_t parm4, uintptr_t parm5,
-                                  uintptr_t parm6)
-{
-  register long reg0 __asm__("r0") = (long)(nbr);
-  register long reg6 __asm__("r6") = (long)(parm6);
-  register long reg5 __asm__("r5") = (long)(parm5);
-  register long reg4 __asm__("r4") = (long)(parm4);
-  register long reg3 __asm__("r3") = (long)(parm3);
-  register long reg2 __asm__("r2") = (long)(parm2);
-  register long reg1 __asm__("r1") = (long)(parm1);
-
-  __asm__ __volatile__
-  (
-    "svc %1"
-    : "=r"(reg0)
-    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
-      "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
-    : "memory"
-  );
-
-  return reg0;
-}
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H */
-

arch/arm/include/c5471/irq.h

@@ -1,106 +0,0 @@
-/****************************************************************************
- * arch/arm/include/c5471/irq.h
- *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_C5471_IRQ_H
-#define __ARCH_ARM_INCLUDE_C5471_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* C5471 Interrupts */
-
-#define C5471_IRQ_TIMER0         0
-#define C5471_IRQ_TIMER1         1
-#define C5471_IRQ_TIMER2         2
-#define C5471_IRQ_GPIO0          3
-#define C5471_IRQ_ETHER          4
-#define C5471_IRQ_KBGPIO_0_7     5
-#define C5471_IRQ_UART           6
-#define C5471_IRQ_UART_IRDA      7
-#define C5471_IRQ_KBGPIO_8_15    8
-#define C5471_IRQ_GPIO3          9
-#define C5471_IRQ_GPIO2         10
-#define C5471_IRQ_I2C           11
-#define C5471_IRQ_GPIO1         12
-#define C5471_IRQ_SPI           13
-#define C5471_IRQ_GPIO_4_19     14
-#define C5471_IRQ_API           15
-
-#define C5471_IRQ_WATCHDOG      C5471_IRQ_TIMER0
-#define C5471_IRQ_SYSTIMER      C5471_IRQ_TIMER2
-#define NR_IRQS                 (C5471_IRQ_API+1)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_C5471_IRQ_H */
-

arch/arm/include/calypso/armio.h

@@ -1,49 +0,0 @@
-/****************************************************************************
- * Driver for Calypso ARMIO
- *
- *   Copyright (C) 2011 Stefan Richter. All rights reserved.
- *   Author: Stefan Richter <ichgeh@l--putt.de>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <stdint.h>
-
-/****************************************************************************
- * Prototypes for interrupt handling
- ****************************************************************************/
-
-inline int calypso_kbd_irq(int irq, uint32_t *regs);
-
-/****************************************************************************
- * Initialize device, add /dev/... nodes
- ****************************************************************************/
-
-void calypso_armio(void);

arch/arm/include/calypso/clock.h

@@ -1,67 +0,0 @@
-#ifndef _CALYPSO_CLK_H
-#define _CALYPSO_CLK_H
-
-#include <stdint.h>
-
-#define CALYPSO_PLL26_52_MHZ	((2 << 8) | 0)
-#define CALYPSO_PLL26_86_7_MHZ	((10 << 8) | 2)
-#define CALYPSO_PLL26_87_MHZ	((3 << 8) | 0)
-#define CALYPSO_PLL13_104_MHZ	((8 << 8) | 0)
-
-enum mclk_div {
-	_ARM_MCLK_DIV_1		= 0,
-	ARM_MCLK_DIV_1		= 1,
-	ARM_MCLK_DIV_2		= 2,
-	ARM_MCLK_DIV_3		= 3,
-	ARM_MCLK_DIV_4		= 4,
-	ARM_MCLK_DIV_5		= 5,
-	ARM_MCLK_DIV_6		= 6,
-	ARM_MCLK_DIV_7		= 7,
-	ARM_MCLK_DIV_1_5	= 0x80 | 1,
-	ARM_MCLK_DIV_2_5	= 0x80 | 2,
-};
-
-void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div);
-void calypso_pll_set(uint16_t inp);
-void calypso_clk_dump(void);
-
-/* CNTL_RST */
-enum calypso_rst {
-	RESET_DSP	= (1 << 1),
-	RESET_EXT	= (1 << 2),
-	RESET_WDOG	= (1 << 3),
-};
-
-void calypso_reset_set(enum calypso_rst calypso_rst, int active);
-int calypso_reset_get(enum calypso_rst);
-
-enum calypso_bank {
-	CALYPSO_nCS0	= 0,
-	CALYPSO_nCS1	= 2,
-	CALYPSO_nCS2	= 4,
-	CALYPSO_nCS3	= 6,
-	CALYPSO_nCS7	= 8,
-	CALYPSO_CS4	= 0xa,
-	CALYPSO_nCS6	= 0xc,
-};
-
-enum calypso_mem_width {
-	CALYPSO_MEM_8bit	= 0,
-	CALYPSO_MEM_16bit	= 1,
-	CALYPSO_MEM_32bit	= 2,
-};
-
-void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
-		     enum calypso_mem_width width, int we);
-
-/* Enable or disable the internal bootrom mapped to 0x0000'0000 */
-void calypso_bootrom(int enable);
-
-/* Enable or disable the debug unit */
-void calypso_debugunit(int enable);
-
-/* configure the RHEA bus bridge[s] */
-void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
-		      uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
-
-#endif /* _CALYPSO_CLK_H */

arch/arm/include/calypso/debug.h

@@ -1,31 +0,0 @@
-#ifndef _DEBUG_H
-#define _DEBUG_H
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#endif
-
-/*
- * Check at compile time that something is of a particular type.
- * Always evaluates to 1 so you may use it easily in comparisons.
- */
-#define typecheck(type,x) \
-({	type __dummy; \
-	typeof(x) __dummy2; \
-	(void)(&__dummy == &__dummy2); \
-	1; \
-})
-
-#ifdef DEBUG
-#define dputchar(x) putchar(x)
-#define dputs(x) puts(x)
-#define dphex(x,y) phex(x,y)
-#define printd(x, ...) printf(x, ##__VA_ARGS__)
-#else
-#define dputchar(x)
-#define dputs(x)
-#define dphex(x,y)
-#define printd(x, args ...)
-#endif
-
-#endif /* _DEBUG_H */

arch/arm/include/calypso/defines.h

@@ -1,18 +0,0 @@
-
-#ifndef _DEFINES_H
-#define _DEFINES_H
-
-#define __attribute_const__	__attribute__((__const__))
-
-/* type properties */
-#define __packed		__attribute__((packed))
-#define __aligned(alignment)	__attribute__((aligned(alignment)))
-#define __unused		__attribute__((unused))
-
-/* linkage */
-#define __section(name) __attribute__((section(name)))
-
-/* force placement in zero-waitstate memory */
-#define __ramtext __section(".ramtext")
-
-#endif /* !_DEFINES_H */

arch/arm/include/calypso/irq.h

@@ -1,81 +0,0 @@
-/****************************************************************************
- * arch/arm/include/calypso/irq.h
- * Driver for Calypso IRQ controller
- *
- * (C) 2010 by Harald Welte <laforge@gnumonks.org>
- * (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
- *
- * This source code is derivated from Osmocom-BB project and was
- * relicensed as BSD with permission from original authors.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- **************************************************************************/
-
-#ifndef __INCLUDE_NUTTX_IRQ_H
-#error "This file should never be included directly! Use <nuttx/irq.h>"
-#endif
-
-#ifndef _CALYPSO_IRQ_H
-#define _CALYPSO_IRQ_H
-
-#ifndef __ASSEMBLY__
-
-enum irq_nr {
-	IRQ_WATCHDOG		= 0,
-	IRQ_TIMER1		= 1,
-	IRQ_TIMER2		= 2,
-	IRQ_TSP_RX		= 3,
-	IRQ_TPU_FRAME		= 4,
-	IRQ_TPU_PAGE		= 5,
-	IRQ_SIMCARD		= 6,
-	IRQ_UART_MODEM		= 7,
-	IRQ_KEYPAD_GPIO		= 8,
-	IRQ_RTC_TIMER		= 9,
-	IRQ_RTC_ALARM_I2C	= 10,
-	IRQ_ULPD_GAUGING	= 11,
-	IRQ_EXTERNAL		= 12,
-	IRQ_SPI			= 13,
-	IRQ_DMA			= 14,
-	IRQ_API			= 15,
-	IRQ_SIM_DETECT		= 16,
-	IRQ_EXTERNAL_FIQ	= 17,
-	IRQ_UART_IRDA		= 18,
-	IRQ_ULPD_GSM_TIMER	= 19,
-	IRQ_GEA			= 20,
-	_NR_IRQS
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* Don't use _NR_IRQS!!! Won't work in preprocessor... */
-#define NR_IRQS			21
-
-#define IRQ_SYSTIMER		IRQ_TIMER2
-
-#endif /* _CALYPSO_IRQ_H */

arch/arm/include/calypso/memory.h

@@ -1,28 +0,0 @@
-#ifndef _MEMORY_H
-#define _MEMORY_H
-
-#define __arch_getb(a)			(*(volatile unsigned char *)(a))
-#define __arch_getw(a)			(*(volatile unsigned short *)(a))
-#define __arch_getl(a)			(*(volatile unsigned int *)(a))
-
-#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
-
-#define __raw_writeb(v,a)		__arch_putb(v,a)
-#define __raw_writew(v,a)		__arch_putw(v,a)
-#define __raw_writel(v,a)		__arch_putl(v,a)
-
-#define __raw_readb(a)			__arch_getb(a)
-#define __raw_readw(a)			__arch_getw(a)
-#define __raw_readl(a)			__arch_getl(a)
-
-#define writeb(v,a)			__arch_putb(v,a)
-#define writew(v,a)			__arch_putw(v,a)
-#define writel(v,a)			__arch_putl(v,a)
-
-#define readb(a)			__arch_getb(a)
-#define readw(a)			__arch_getw(a)
-#define readl(a)			__arch_getl(a)
-
-#endif /* _MEMORY_H */

arch/arm/include/calypso/timer.h

@@ -1,25 +0,0 @@
-#ifndef _CAL_TIMER_H
-#define _CAL_TIMER_H
-
-/* Enable or Disable a timer */
-void hwtimer_enable(int num, int on);
-
-/* Configure pre-scaler and if timer is auto-reload */
-void hwtimer_config(int num, uint8_t pre_scale, int auto_reload);
-
-/* Load a timer with the given value */
-void hwtimer_load(int num, uint16_t val);
-
-/* Read the current timer value */
-uint16_t hwtimer_read(int num);
-
-/* Enable or disable the watchdog */
-void wdog_enable(int on);
-
-/* Reset cpu using watchdog */
-void wdog_reset(void);
-
-/* power up the timers */
-void hwtimer_init(void);
-
-#endif /* _CAL_TIMER_H */

arch/arm/include/calypso/uwire.h

@@ -1,6 +0,0 @@
-#ifndef _CALYPSO_UWIRE_H
-#define _CALYPSO_UWIRE_H
-void uwire_init(void);
-int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
-#endif
-

arch/arm/include/dm320/irq.h

@@ -1,135 +0,0 @@
-/****************************************************************************
- * arch/arm/include/dm320/irq.h
- *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_DM320_IRQ_H
-#define __ARCH_ARM_INCLUDE_DM320_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* DM320 Interrupts */
-
-#define DM320_IRQ_TMR0      0 /* IRQ0:  Timer 0 Interrupt */
-#define DM320_IRQ_TMR1      1 /* IRQ1:  Timer 1 Interrupt */
-#define DM320_IRQ_TMR2      2 /* IRQ2:  Timer 2 Interrupt (CCD timer 0) */
-#define DM320_IRQ_TMR3      3 /* IRQ3:  Timer 3 Interrupt (CCD timer 1) */
-#define DM320_IRQ_CCDVD0    4 /* IRQ4:  CCD VD Interrupt #0 */
-#define DM320_IRQ_CCDVD1    5 /* IRQ5:  CCD VD Interrupt #1 */
-#define DM320_IRQ_CCDWEN    6 /* IRQ6:  CCD WEN Interrupt */
-#define DM320_IRQ_VENC      7 /* IRQ7:  Video Encoder Interrupt */
-#define DM320_IRQ_SP0       8 /* IRQ8:  Serial Port 0 Interrupt (with DMA) */
-#define DM320_IRQ_SP1       9 /* IRQ9:  Serial Port 1 Interrupt */
-#define DM320_IRQ_EXTHOST  10 /* IRQ10: External host interrupt */
-#define DM320_IRQ_IMGBUF   11 /* IRQ11: Image Buffer */
-#define DM320_IRQ_UART0    12 /* IRQ12: UART0 Interrupt */
-#define DM320_IRQ_UART1    13 /* IRQ13: UART1 Interrupt */
-#define DM320_IRQ_USB0     14 /* IRQ14: USB 0 Interrupt (DMA) */
-#define DM320_IRQ_USB1     15 /* IRQ15: USB 1 Interrupt (Core) */
-#define DM320_IRQ_VLYNQ    16 /* IRQ16: VLYNQ Interrupt */
-#define DM320_IRQ_MTC0     17 /* IRQ17: Memory Traffic Controller 0 (DMA) */
-#define DM320_IRQ_MTC1     18 /* IRQ18: Memory Traffic Controller 1 (CFC_RDY) */
-#define DM320_IRQ_MMCSD0   19 /* IRQ19: MMC/SD or MS 0 Interrupt */
-#define DM320_IRQ_MMCSD1   20 /* IRQ20: MMC/SD or MS 1 Interrupt */
-#define DM320_IRQ_EXT0     21 /* IRQ21: External Interrupt #0 (GIO0) */
-#define DM320_IRQ_EXT1     22 /* IRQ22: External Interrupt #1 (GIO1) */
-#define DM320_IRQ_EXT2     23 /* IRQ23: External Interrupt #2 (GIO2) */
-#define DM320_IRQ_EXT3     24 /* IRQ24: External Interrupt #3 (GIO3) */
-#define DM320_IRQ_EXT4     25 /* IRQ25: External Interrupt #4 (GIO4) */
-#define DM320_IRQ_EXT5     26 /* IRQ26: External Interrupt #5 (GIO5) */
-#define DM320_IRQ_EXT6     27 /* IRQ27: External Interrupt #6 (GIO6) */
-#define DM320_IRQ_EXT7     28 /* IRQ28: External Interrupt #7 (GIO7) */
-#define DM320_IRQ_EXT8     29 /* IRQ29: External Interrupt #8 (GIO8) */
-#define DM320_IRQ_EXT9     30 /* IRQ30: External Interrupt #9 (GIO9) */
-#define DM320_IRQ_EXT10    31 /* IRQ31: External Interrupt #10 (GIO10) */
-#define DM320_IRQ_EXT11    32 /* IRQ32: External Interrupt #11 (GIO11) */
-#define DM320_IRQ_EXT12    33 /* IRQ33: External Interrupt #12 (GIO12) */
-#define DM320_IRQ_EXT13    34 /* IRQ34: External Interrupt #13 (GIO13) */
-#define DM320_IRQ_EXT14    35 /* IRQ35: External Interrupt #14 (GIO14) */
-#define DM320_IRQ_EXT15    36 /* IRQ36: External Interrupt #15 (GIO15) */
-#define DM320_IRQ_PREV0    37 /* IRQ37: Preview Engine 0 (Preview Over) */
-#define DM320_IRQ_PREV1    38 /* IRQ38: Preview Engine 1 (Preview Historgram Over) */
-#define DM320_IRQ_WDT      39 /* IRQ39: Watchdog Timer Interrupt */
-#define DM320_IRQ_I2C      40 /* IRQ40: I2C Interrupt */
-#define DM320_IRQ_CLKC     41 /* IRQ41: Clock controller Interrupt (wake up) */
-#define DM320_IRQ_E2ICE    42 /* IRQ42: Embedded ICE Interrupt */
-#define DM320_IRQ_ARMCOMRX 43 /* IRQ43: ARMCOMM Receive Interrupt */
-#define DM320_IRQ_ARMCOMTX 44 /* IRQ44: ARMCOMM Transmit Interrupt */
-#define DM320_IRQ_RSV      45 /* IRQ45: Reserved Interrupt */
-
-#define DM320_IRQ_SYSTIMER DM320_IRQ_TMR0
-#define NR_IRQS            (DM320_IRQ_RSV+1)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_DM320_IRQ_H */
-

arch/arm/include/efm32/chip.h

@@ -1,129 +0,0 @@
-/************************************************************************************
- * arch/arm/include/efm32/chip.h
- *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_EFM32_CHIP_H
-#define __ARCH_ARM_INCLUDE_EFM32_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* EFM32 EnergyMicro ****************************************************************/
-
-/* Tiny Gecko with 32KiB FLASH and 4KiB RAM in a QFN64 package */
-
-#if defined(CONFIG_ARCH_CHIP_EFM32TG840F32)
-
-/* Gecko with 128KiB FLASH and 16KiB SRAM in LQFP100 (EFM32G880F128) or BGA112
- * (EFM32G890F128) package
- */
-
-#elif defined(CONFIG_ARCH_CHIP_EFM32G880F128) || \
-      defined(CONFIG_ARCH_CHIP_EFM32G890F128)
-
-/* Giant Gecko with 1024KiB FLASH and 128KiB RAM in a QFP64 package
- * (EFM32GG332F1024) or BGA112 (EFM32GG990F1024) package
- */
-
-#elif defined(CONFIG_ARCH_CHIP_EFM32GG332F1024) || \
-      defined(CONFIG_ARCH_CHIP_EFM32GG990F1024)
-
-#else
-#  error "Unsupported EFM32 chip"
-#endif
-
-/* NVIC priority levels *************************************************************/
-
-#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* Bits [7:5] set in minimum priority */
-#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
-#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP    0x20 /* Three bits of interrupt priority used */
-
-/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
- * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
- * interrupts will not have execution priority.  SVCall must have execution
- * priority in all cases.
- *
- * In the normal cases, interrupts are not nest-able and all interrupts run
- * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
- * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
- *
- * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
- * high priority interrupts are supported.  These are not "nested" in the
- * normal sense of the word.  These high priority interrupts can interrupt
- * normal processing but execute outside of OS (although they can "get back
- * into the game" via a PendSV interrupt).
- *
- * In the normal course of things, interrupts must occasionally be disabled
- * using the irqsave() inline function to prevent contention in use of
- * resources that may be shared between interrupt level and non-interrupt
- * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
- * do we disable all interrupts (except SVCall), or do we only disable the
- * "normal" interrupts.  Since the high priority interrupts cannot interact
- * with the OS, you may want to permit the high priority interrupts even if
- * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
- * used to select either behavior:
- *
- *   ----------------------------+--------------+----------------------------
- *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
- *   ----------------------------+--------------+--------------+-------------
- *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
- *   ----------------------------+--------------+--------------+-------------
- *                               |              |              |    SVCall
- *                               |    SVCall    |    SVCall    |    HIGH
- *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
- *                               |              |    MAXNORMAL |
- *   ----------------------------+--------------+--------------+-------------
- */
-
-#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
-#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
-#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
-#else
-#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
-#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
-#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_EFM32_CHIP_H */

arch/arm/include/efm32/efm32g_irq.h

@@ -1,121 +0,0 @@
-/*****************************************************************************
- * arch/arm/include/efm32s/efm32g_irq.h
- *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_EFM32G_IRQ_H
-#define __ARCH_ARM_INCLUDE_EFM32G_IRQ_H
-
-/*****************************************************************************
- * Included Files
- *****************************************************************************/
-
-/*****************************************************************************
- * Pre-processor Definitions
- *****************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- *
- * Processor Exceptions (vectors 0-15).  These common definitions can be
- * found in nuttx/arch/arm/include/efm32/irq.h
- *
- * External interrupts (vectors >= 16)
- */
-                                                        /* IRQ# Source      */
-#define EFM32_IRQ_DMA        (EFM32_IRQ_INTERRUPTS+ 0)  /*  0   DMA         */
-#define EFM32_IRQ_GPIO_EVEN  (EFM32_IRQ_INTERRUPTS+ 1)  /*  1   GPIO_EVEN   */
-#define EFM32_IRQ_TIMER0     (EFM32_IRQ_INTERRUPTS+ 2)  /*  2   TIMER0      */
-#define EFM32_IRQ_USART0_RX  (EFM32_IRQ_INTERRUPTS+ 3)  /*  3   USART0_RX   */
-#define EFM32_IRQ_USART0_TX  (EFM32_IRQ_INTERRUPTS+ 4)  /*  4   USART0_TX   */
-#define EFM32_IRQ_ACMP       (EFM32_IRQ_INTERRUPTS+ 5)  /*  5   ACMP0/ACMP1 */
-#define EFM32_IRQ_ADC0       (EFM32_IRQ_INTERRUPTS+ 6)  /*  6   ADC0        */
-#define EFM32_IRQ_DAC0       (EFM32_IRQ_INTERRUPTS+ 7)  /*  7   DAC0        */
-#define EFM32_IRQ_I2C0       (EFM32_IRQ_INTERRUPTS+ 8)  /*  8   I2C0        */
-#define EFM32_IRQ_GPIO_ODD   (EFM32_IRQ_INTERRUPTS+ 9)  /*  9   GPIO_ODD    */
-#define EFM32_IRQ_TIMER1     (EFM32_IRQ_INTERRUPTS+10)  /* 10   TIMER1      */
-#define EFM32_IRQ_TIMER2     (EFM32_IRQ_INTERRUPTS+11)  /* 11   TIMER2      */
-#define EFM32_IRQ_USART1_RX  (EFM32_IRQ_INTERRUPTS+12)  /* 12   USART1_RX   */
-#define EFM32_IRQ_USART1_TX  (EFM32_IRQ_INTERRUPTS+13)  /* 13   USART1_TX   */
-#define EFM32_IRQ_USART2_RX  (EFM32_IRQ_INTERRUPTS+14)  /* 14   USART2_RX   */
-#define EFM32_IRQ_USART2_TX  (EFM32_IRQ_INTERRUPTS+15)  /* 15   USART2_TX   */
-#define EFM32_IRQ_UART0_RX   (EFM32_IRQ_INTERRUPTS+16)  /* 16   UART0_RX    */
-#define EFM32_IRQ_UART0_TX   (EFM32_IRQ_INTERRUPTS+17)  /* 17   UART0_TX    */
-#define EFM32_IRQ_LEUART0    (EFM32_IRQ_INTERRUPTS+18)  /* 18   LEUART0     */
-#define EFM32_IRQ_LEUART1    (EFM32_IRQ_INTERRUPTS+19)  /* 19   LEUART1     */
-#define EFM32_IRQ_LETIMER0   (EFM32_IRQ_INTERRUPTS+20)  /* 20   LETIMER0    */
-#define EFM32_IRQ_PCNT0      (EFM32_IRQ_INTERRUPTS+21)  /* 21   PCNT0       */
-#define EFM32_IRQ_PCNT1      (EFM32_IRQ_INTERRUPTS+22)  /* 22   PCNT1       */
-#define EFM32_IRQ_PCNT2      (EFM32_IRQ_INTERRUPTS+23)  /* 23   PCNT2       */
-#define EFM32_IRQ_RTC        (EFM32_IRQ_INTERRUPTS+24)  /* 24   RTC         */
-#define EFM32_IRQ_CMU        (EFM32_IRQ_INTERRUPTS+25)  /* 25   CMU         */
-#define EFM32_IRQ_VCMP       (EFM32_IRQ_INTERRUPTS+26)  /* 26   VCMP        */
-#define EFM32_IRQ_LCD        (EFM32_IRQ_INTERRUPTS+27)  /* 27   LCD         */
-#define EFM32_IRQ_MSC        (EFM32_IRQ_INTERRUPTS+28)  /* 28   MSC         */
-#define EFM32_IRQ_AES        (EFM32_IRQ_INTERRUPTS+29)  /* 29   AES         */
-
-#define NR_VECTORS           (EFM32_IRQ_INTERRUPTS+30)
-
-/*****************************************************************************
- * Public Types
- *****************************************************************************/
-
-/*****************************************************************************
- * Public Data
- *****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/*****************************************************************************
- * Public Functions
- *****************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_EFM32G_IRQ_H */

arch/arm/include/efm32/efm32gg_irq.h

@@ -1,130 +0,0 @@
-/*****************************************************************************
- * arch/arm/include/efm32s/efm32gg_irq.h
- *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_EFM32GG_IRQ_H
-#define __ARCH_ARM_INCLUDE_EFM32GG_IRQ_H
-
-/*****************************************************************************
- * Included Files
- *****************************************************************************/
-
-/*****************************************************************************
- * Pre-processor Definitions
- *****************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- *
- * Processor Exceptions (vectors 0-15).  These common definitions can be
- * found in nuttx/arch/arm/include/efm32/irq.h
- *
- * External interrupts (vectors >= 16)
- */
-
-#define EFM32_IRQ_DMA           (EFM32_IRQ_INTERRUPTS+ 0)
-#define EFM32_IRQ_GPIO_EVEN     (EFM32_IRQ_INTERRUPTS+ 1)
-#define EFM32_IRQ_TIMER0        (EFM32_IRQ_INTERRUPTS+ 2)
-#define EFM32_IRQ_USART0_RX     (EFM32_IRQ_INTERRUPTS+ 3)
-#define EFM32_IRQ_USART0_TX     (EFM32_IRQ_INTERRUPTS+ 4)
-#define EFM32_IRQ_USB           (EFM32_IRQ_INTERRUPTS+ 5)
-#define EFM32_IRQ_ACMP          (EFM32_IRQ_INTERRUPTS+ 6)
-#define EFM32_IRQ_ADC0          (EFM32_IRQ_INTERRUPTS+ 7)
-#define EFM32_IRQ_DAC0          (EFM32_IRQ_INTERRUPTS+ 8)
-#define EFM32_IRQ_I2C0          (EFM32_IRQ_INTERRUPTS+ 9)
-#define EFM32_IRQ_I2C1          (EFM32_IRQ_INTERRUPTS+10)
-#define EFM32_IRQ_GPIO_ODD      (EFM32_IRQ_INTERRUPTS+11)
-#define EFM32_IRQ_TIMER1        (EFM32_IRQ_INTERRUPTS+12)
-#define EFM32_IRQ_TIMER2        (EFM32_IRQ_INTERRUPTS+13)
-#define EFM32_IRQ_TIMER3        (EFM32_IRQ_INTERRUPTS+14)
-#define EFM32_IRQ_USART1_RX     (EFM32_IRQ_INTERRUPTS+15)
-#define EFM32_IRQ_USART1_TX     (EFM32_IRQ_INTERRUPTS+16)
-#define EFM32_IRQ_LESENSE       (EFM32_IRQ_INTERRUPTS+17)
-#define EFM32_IRQ_USART2_RX     (EFM32_IRQ_INTERRUPTS+18)
-#define EFM32_IRQ_USART2_TX     (EFM32_IRQ_INTERRUPTS+19)
-#define EFM32_IRQ_UART0_RX      (EFM32_IRQ_INTERRUPTS+20)
-#define EFM32_IRQ_UART0_TX      (EFM32_IRQ_INTERRUPTS+21)
-#define EFM32_IRQ_UART1_RX      (EFM32_IRQ_INTERRUPTS+22)
-#define EFM32_IRQ_UART1_TX      (EFM32_IRQ_INTERRUPTS+23)
-#define EFM32_IRQ_LEUART0       (EFM32_IRQ_INTERRUPTS+24)
-#define EFM32_IRQ_LEUART1       (EFM32_IRQ_INTERRUPTS+25)
-#define EFM32_IRQ_LETIMER0      (EFM32_IRQ_INTERRUPTS+26)
-#define EFM32_IRQ_PCNT0         (EFM32_IRQ_INTERRUPTS+27)
-#define EFM32_IRQ_PCNT1         (EFM32_IRQ_INTERRUPTS+28)
-#define EFM32_IRQ_PCNT2         (EFM32_IRQ_INTERRUPTS+29)
-#define EFM32_IRQ_RTC           (EFM32_IRQ_INTERRUPTS+30)
-#define EFM32_IRQ_BURTC         (EFM32_IRQ_INTERRUPTS+31)
-#define EFM32_IRQ_CMU           (EFM32_IRQ_INTERRUPTS+32)
-#define EFM32_IRQ_VCMP          (EFM32_IRQ_INTERRUPTS+33)
-#define EFM32_IRQ_LCD           (EFM32_IRQ_INTERRUPTS+34)
-#define EFM32_IRQ_MSC           (EFM32_IRQ_INTERRUPTS+35)
-#define EFM32_IRQ_AES           (EFM32_IRQ_INTERRUPTS+36)
-#define EFM32_IRQ_EBI           (EFM32_IRQ_INTERRUPTS+37)
-#define EFM32_IRQ_EMI           (EFM32_IRQ_INTERRUPTS+38)
-
-#define NR_VECTORS              (EFM32_IRQ_INTERRUPTS+39)
-
-/*****************************************************************************
- * Public Types
- *****************************************************************************/
-
-/*****************************************************************************
- * Public Data
- *****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/*****************************************************************************
- * Public Functions
- *****************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_EFM32GG_IRQ_H */

arch/arm/include/efm32/efm32tg_irq.h

@@ -1,114 +0,0 @@
-/*****************************************************************************
- * arch/arm/include/efm32s/efm32tg_irq.h
- *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_EFM32TG_IRQ_H
-#define __ARCH_ARM_INCLUDE_EFM32TG_IRQ_H
-
-/*****************************************************************************
- * Included Files
- *****************************************************************************/
-
-/*****************************************************************************
- * Pre-processor Definitions
- *****************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- *
- * Processor Exceptions (vectors 0-15).  These common definitions can be
- * found in nuttx/arch/arm/include/efm32/irq.h
- *
- * External interrupts (vectors >= 16)
- */
-
-#define EFM32_IRQ_DMA         (EFM32_IRQ_INTERRUPTS+ 0)
-#define EFM32_IRQ_GPIO_EVEN   (EFM32_IRQ_INTERRUPTS+ 1)
-#define EFM32_IRQ_TIMER0      (EFM32_IRQ_INTERRUPTS+ 2)
-#define EFM32_IRQ_USART0_RX   (EFM32_IRQ_INTERRUPTS+ 3)
-#define EFM32_IRQ_USART0_TX   (EFM32_IRQ_INTERRUPTS+ 4)
-#define EFM32_IRQ_ACMP        (EFM32_IRQ_INTERRUPTS+ 5)
-#define EFM32_IRQ_ADC0        (EFM32_IRQ_INTERRUPTS+ 6)
-#define EFM32_IRQ_DAC0        (EFM32_IRQ_INTERRUPTS+ 7)
-#define EFM32_IRQ_I2C0        (EFM32_IRQ_INTERRUPTS+ 8)
-#define EFM32_IRQ_GPIO_ODD    (EFM32_IRQ_INTERRUPTS+ 9)
-#define EFM32_IRQ_TIMER1      (EFM32_IRQ_INTERRUPTS+10)
-#define EFM32_IRQ_USART1_RX   (EFM32_IRQ_INTERRUPTS+11)
-#define EFM32_IRQ_USART1_TX   (EFM32_IRQ_INTERRUPTS+12)
-#define EFM32_IRQ_LESENSE     (EFM32_IRQ_INTERRUPTS+13)
-#define EFM32_IRQ_LEUART0     (EFM32_IRQ_INTERRUPTS+14)
-#define EFM32_IRQ_LETIMER0    (EFM32_IRQ_INTERRUPTS+15)
-#define EFM32_IRQ_PCNT0       (EFM32_IRQ_INTERRUPTS+16)
-#define EFM32_IRQ_RTC         (EFM32_IRQ_INTERRUPTS+17)
-#define EFM32_IRQ_CMU         (EFM32_IRQ_INTERRUPTS+18)
-#define EFM32_IRQ_VCMP        (EFM32_IRQ_INTERRUPTS+19)
-#define EFM32_IRQ_LCD         (EFM32_IRQ_INTERRUPTS+20)
-#define EFM32_IRQ_MSC         (EFM32_IRQ_INTERRUPTS+21)
-#define EFM32_IRQ_AES         (EFM32_IRQ_INTERRUPTS+22)
-
-#define NR_VECTORS            (EFM32_IRQ_INTERRUPTS+23)
-
-/*****************************************************************************
- * Public Types
- *****************************************************************************/
-
-/*****************************************************************************
- * Public Data
- *****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/*****************************************************************************
- * Public Functions
- *****************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_EFM32TG_IRQ_H */

arch/arm/include/efm32/irq.h

@@ -1,147 +0,0 @@
-/************************************************************************************
- * arch/arm/include/efm32s/irq.h
- *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_EFM32_IRQ_H
-#define __ARCH_ARM_INCLUDE_EFM32_IRQ_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/irq.h>
-#include <arch/efm32/chip.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
- */
-
-/* Processor Exceptions (vectors 0-15) */
-
-#define EFM32_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
-                                   /* Vector  0: Reset stack pointer value */
-                                   /* Vector  1: Reset (not handler as an IRQ) */
-#define EFM32_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define EFM32_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
-#define EFM32_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
-#define EFM32_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
-#define EFM32_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
-#define EFM32_IRQ_SVCALL      (11) /* Vector 11: SVC call */
-#define EFM32_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
-                                   /* Vector 13: Reserved */
-#define EFM32_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
-#define EFM32_IRQ_SYSTICK     (15) /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16).  These definitions are chip-specific */
-
-#define EFM32_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
-
-#if defined(CONFIG_EFM32_EFM32TG)
-#  include <arch/efm32/efm32tg_irq.h>
-#elif defined(CONFIG_EFM32_EFM32G)
-#  include <arch/efm32/efm32g_irq.h>
-#elif defined(CONFIG_EFM32_EFM32GG)
-#  include <arch/efm32/efm32gg_irq.h>
-#else
-#  error "Unsupported EFM32 chip"
-#endif
-
-#ifdef CONFIG_EFM32_GPIO_IRQ
-/* If GPIO interrupt support is enabled then up to 16 additional GPIO interrupt
- * sources are available.  There are actually only two physical interrupt lines:
- * GPIO_EVEN and GPIO_ODD.  However, from the software point of view, there are
- * 16-additional interrupts generated from a second level of decoding.
- */
-
-#  define EFM32_IRQ_EXTI0     (NR_VECTORS+0)  /* Port[n], pin0 external interrupt */
-#  define EFM32_IRQ_EXTI1     (NR_VECTORS+1)  /* Port[n], pin1 external interrupt */
-#  define EFM32_IRQ_EXTI2     (NR_VECTORS+2)  /* Port[n], pin2 external interrupt */
-#  define EFM32_IRQ_EXTI3     (NR_VECTORS+3)  /* Port[n], pin3 external interrupt */
-#  define EFM32_IRQ_EXTI4     (NR_VECTORS+4)  /* Port[n], pin4 external interrupt */
-#  define EFM32_IRQ_EXTI5     (NR_VECTORS+5)  /* Port[n], pin5 external interrupt */
-#  define EFM32_IRQ_EXTI6     (NR_VECTORS+6)  /* Port[n], pin6 external interrupt */
-#  define EFM32_IRQ_EXTI7     (NR_VECTORS+7)  /* Port[n], pin7 external interrupt */
-#  define EFM32_IRQ_EXTI8     (NR_VECTORS+8)  /* Port[n], pin8 external interrupt */
-#  define EFM32_IRQ_EXTI9     (NR_VECTORS+9)  /* Port[n], pin9 external interrupt */
-#  define EFM32_IRQ_EXTI10    (NR_VECTORS+10) /* Port[n], pin10 external interrupt */
-#  define EFM32_IRQ_EXTI11    (NR_VECTORS+11) /* Port[n], pin11 external interrupt */
-#  define EFM32_IRQ_EXTI12    (NR_VECTORS+12) /* Port[n], pin12 external interrupt */
-#  define EFM32_IRQ_EXTI13    (NR_VECTORS+13) /* Port[n], pin13 external interrupt */
-#  define EFM32_IRQ_EXTI14    (NR_VECTORS+14) /* Port[n], pin14 external interrupt */
-#  define EFM32_IRQ_EXTI15    (NR_VECTORS+15) /* Port[n], pin15 external interrupt */
-
-#  define NR_IRQS             (NR_VECTORS+16) /* Total number of interrupts */
-#else
-#  define NR_IRQS             NR_VECTORS      /* Total number of interrupts */
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_EFM32_IRQ_H */

arch/arm/include/elf.h

@@ -1,243 +0,0 @@
-/****************************************************************************
- * arch/arm/include/syscall.h
- *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Reference: "ELF for the ARM® Architecture," ARM IHI 0044D, current through
- *   ABI release 2.08, October 28, 2009, ARM Limited.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_ELF_H
-#define __ARCH_ARM_INCLUDE_ELF_H
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* 4.3.1 ELF Identification.  Should have:
- *
- * e_machine         = EM_ARM
- * e_ident[EI_CLASS] = ELFCLASS32
- * e_ident[EI_DATA]  = ELFDATA2LSB (little endian) or ELFDATA2MSB (big endian)
- */
-
-#if 0 /* Defined in include/elf32.h */
-#define EM_ARM                   40
-#endif
-
-/* Table 4-2, ARM-specific e_flags */
-
-#define EF_ARM_EABI_MASK         0xff000000
-#define EF_ARM_EABI_UNKNOWN      0x00000000
-#define EF_ARM_EABI_VER1         0x01000000
-#define EF_ARM_EABI_VER2         0x02000000
-#define EF_ARM_EABI_VER3         0x03000000
-#define EF_ARM_EABI_VER4         0x04000000
-#define EF_ARM_EABI_VER5         0x05000000
-
-#define EF_ARM_BE8               0x00800000
-
-/* Table 4-4, Processor specific section types */
-
-#define SHT_ARM_EXIDX            0x70000001 /* Exception Index table */
-#define SHT_ARM_PREEMPTMAP       0x70000002 /* BPABI DLL dynamic linking pre-emption map */
-#define SHT_ARM_ATTRIBUTES       0x70000003 /* Object file compatibility attributes */
-#define SHT_ARM_DEBUGOVERLAY     0x70000004
-#define SHT_ARM_OVERLAYSECTION   0x70000005
-
-/* 4.7.1 Relocation codes
- *
- * S (when used on its own) is the address of the symbol.
- * A is the addend for the relocation.
- * P is the address of the place being relocated (derived from r_offset).
- * Pa is the adjusted address of the place being relocated, defined as (P & 0xFFFFFFFC).
- * T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction;
- *   it is 0 otherwise.
- * B(S) is the addressing origin of the output segment defining the symbol S.
- * GOT_ORG is the addressing origin of the Global Offset Table
- * GOT(S) is the address of the GOT entry for the symbol S.
- */
-
-#define R_ARM_NONE               0             /* No relocation */
-#define R_ARM_PC24               1             /* ARM       ((S + A) | T) - P */
-#define R_ARM_ABS32              2             /* Data      (S + A) | T */
-#define R_ARM_REL32              3             /* Data      ((S + A) | T) - P */
-#define R_ARM_LDR_PC_G0          4             /* ARM       S + A - P */
-#define R_ARM_ABS16              5             /* Data      S + A */
-#define R_ARM_ABS12              6             /* ARM       S + A */
-#define R_ARM_THM_ABS5           7             /* Thumb16   S + A */
-#define R_ARM_ABS8               8             /* Data      S + A */
-#define R_ARM_SBREL32            9             /* Data      ((S + A) | T) - B(S) */
-#define R_ARM_THM_CALL           10            /* Thumb32   ((S + A) | T) - P */
-#define R_ARM_THM_PC8            11            /* Thumb16   S + A - Pa */
-#define R_ARM_BREL_ADJ           12            /* Data      ?B(S) + A */
-#define R_ARM_TLS_DESC           13            /* Data     */
-#define R_ARM_THM_SWI8           14            /* Obsolete */
-#define R_ARM_XPC25              15            /* Obsolete */
-#define R_ARM_THM_XPC22          16            /* Obsolete */
-#define R_ARM_TLS_DTPMOD32       17            /* Data      Module[S] */
-#define R_ARM_TLS_DTPOFF32       18            /* Data      S + A - TLS */
-#define R_ARM_TLS_TPOFF32        19            /* Data      S + A - tp */
-#define R_ARM_COPY               20            /* Miscellaneous */
-#define R_ARM_GLOB_DAT           21            /* Data      (S + A) | T */
-#define R_ARM_JUMP_SLOT          22            /* Data      (S + A) | T */
-#define R_ARM_RELATIVE           23            /* Data      B(S) + A */
-#define R_ARM_GOTOFF32           24            /* Data      ((S + A) | T) - GOT_ORG */
-#define R_ARM_BASE_PREL          25            /* Data      B(S) + A - P */
-#define R_ARM_GOT_BREL           26            /* Data      GOT(S) + A - GOT_ORG */
-#define R_ARM_PLT32              27            /* ARM       ((S + A) | T) - P */
-#define R_ARM_CALL               28            /* ARM       ((S + A) | T) - P */
-#define R_ARM_JUMP24             29            /* ARM       ((S + A) | T) - P */
-#define R_ARM_THM_JUMP24         30            /* Thumb32   ((S + A) | T) - P */
-#define R_ARM_BASE_ABS           31            /* Data      B(S) + A */
-#define R_ARM_ALU_PCREL_7_0      32            /* Obsolete */
-#define R_ARM_ALU_PCREL_15_8     33            /* Obsolete */
-#define R_ARM_ALU_PCREL_23_15    34            /* Obsolete */
-#define R_ARM_LDR_SBREL_11_0_NC  35            /* ARM       S + A - B(S) */
-#define R_ARM_ALU_SBREL_19_12_NC 36            /* ARM       S + A - B(S) */
-#define R_ARM_ALU_SBREL_27_20_CK 37            /* ARM       S + A - B(S) */
-#define R_ARM_TARGET1            38            /* Miscellaneous (S + A) | T or ((S + A) | T) - P */
-#define R_ARM_SBREL31            39            /* Data      ((S + A) | T) - B(S) */
-#define R_ARM_V4BX               40            /* Miscellaneous */
-#define R_ARM_TARGET2            41            /* Miscellaneous */
-#define R_ARM_PREL31             42            /* Data      ((S + A) | T) - P */
-#define R_ARM_MOVW_ABS_NC        43            /* ARM       (S + A) | T */
-#define R_ARM_MOVT_ABS           44            /* ARM       S + A */
-#define R_ARM_MOVW_PREL_NC       45            /* ARM       ((S + A) | T) - P */
-#define R_ARM_MOVT_PREL          46            /* ARM       S + A - P */
-#define R_ARM_THM_MOVW_ABS_NC    47            /* Thumb32   (S + A) | T */
-#define R_ARM_THM_MOVT_ABS       48            /* Thumb32   S + A */
-#define R_ARM_THM_MOVW_PREL_NC   49            /* Thumb32   ((S + A) | T) - P */
-#define R_ARM_THM_MOVT_PREL      50            /* Thumb32   S + A - P */
-#define R_ARM_THM_JUMP19         51            /* Thumb32   ((S + A) | T) - P */
-#define R_ARM_THM_JUMP6          52            /* Thumb16   S + A - P */
-#define R_ARM_THM_ALU_PREL_11_0  53            /* Thumb32   ((S + A) | T) - Pa */
-#define R_ARM_THM_PC12           54            /* Thumb32   S + A - Pa */
-#define R_ARM_ABS32_NOI          55            /* Data      S + A */
-#define R_ARM_REL32_NOI          56            /* Data      S + A - P */
-#define R_ARM_ALU_PC_G0_NC       57            /* ARM       ((S + A) | T) - P */
-#define R_ARM_ALU_PC_G0          58            /* ARM       ((S + A) | T) - P */
-#define R_ARM_ALU_PC_G1_NC       59            /* ARM       ((S + A) | T) - P */
-#define R_ARM_ALU_PC_G1          60            /* ARM       ((S + A) | T) - P */
-#define R_ARM_ALU_PC_G2          61            /* ARM       ((S + A) | T) - P */
-#define R_ARM_LDR_PC_G1          62            /* ARM       S + A - P */
-#define R_ARM_LDR_PC_G2          63            /* ARM       S + A - P */
-#define R_ARM_LDRS_PC_G0         64            /* ARM       S + A - P */
-#define R_ARM_LDRS_PC_G1         65            /* ARM       S + A - P */
-#define R_ARM_LDRS_PC_G2         66            /* ARM       S + A - P */
-#define R_ARM_LDC_PC_G0          67            /* ARM       S + A - P */
-#define R_ARM_LDC_PC_G1          68            /* ARM       S + A - P */
-#define R_ARM_LDC_PC_G2          69            /* ARM       S + A - P */
-#define R_ARM_ALU_SB_G0_NC       70            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_ALU_SB_G0          71            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_ALU_SB_G1_NC       72            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_ALU_SB_G1          73            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_ALU_SB_G2          74            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_LDR_SB_G0          75            /* ARM       S + A - B(S) */
-#define R_ARM_LDR_SB_G1          76            /* ARM       S + A - B(S) */
-#define R_ARM_LDR_SB_G2          77            /* ARM       S + A - B(S) */
-#define R_ARM_LDRS_SB_G0         78            /* ARM       S + A - B(S) */
-#define R_ARM_LDRS_SB_G1         79            /* ARM       S + A - B(S) */
-#define R_ARM_LDRS_SB_G2         80            /* ARM       S + A - B(S) */
-#define R_ARM_LDC_SB_G0          81            /* ARM       S + A - B(S) */
-#define R_ARM_LDC_SB_G1          82            /* ARM       S + A - B(S) */
-#define R_ARM_LDC_SB_G2          83            /* ARM       S + A - B(S) */
-#define R_ARM_MOVW_BREL_NC       84            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_MOVT_BREL          85            /* ARM       S + A - B(S) */
-#define R_ARM_MOVW_BREL          86            /* ARM       ((S + A) | T) - B(S) */
-#define R_ARM_THM_MOVW_BREL_NC   87            /* Thumb32   ((S + A) | T) - B(S) */
-#define R_ARM_THM_MOVT_BREL      88            /* Thumb32   S + A - B(S) */
-#define R_ARM_THM_MOVW_BREL      89            /* Thumb32   ((S + A) | T) - B(S) */
-#define R_ARM_TLS_GOTDESC        90            /* Data */
-#define R_ARM_TLS_CALL           91            /* ARM */
-#define R_ARM_TLS_DESCSEQ        92            /* ARM       TLS relaxation */
-#define R_ARM_THM_TLS_CALL       93            /* Thumb32 */
-#define R_ARM_PLT32_ABS          94            /* Data      PLT(S) + A */
-#define R_ARM_GOT_ABS            95            /* Data      GOT(S) + A */
-#define R_ARM_GOT_PREL           96            /* Data      GOT(S) + A - P */
-#define R_ARM_GOT_BREL12         97            /* ARM       GOT(S) + A - GOT_ORG */
-#define R_ARM_GOTOFF12           98            /* ARM       S + A - GOT_ORG */
-#define R_ARM_GOTRELAX           99            /* Miscellaneous */
-#define R_ARM_GNU_VTENTRY        100           /* Data */
-#define R_ARM_GNU_VTINHERIT      101           /* Data */
-#define R_ARM_THM_JUMP11         102           /* Thumb16   S + A - P */
-#define R_ARM_THM_JUMP8          103           /* Thumb16   S + A - P */
-#define R_ARM_TLS_GD32           104           /* Data      GOT(S) + A - P */
-#define R_ARM_TLS_LDM32          105           /* Data      GOT(S) + A - P */
-#define R_ARM_TLS_LDO32          106           /* Data      S + A - TLS */
-#define R_ARM_TLS_IE32           107           /* Data      GOT(S) + A - P */
-#define R_ARM_TLS_LE32           108           /* Data      S + A - tp */
-#define R_ARM_TLS_LDO12          109           /* ARM       S + A - TLS */
-#define R_ARM_TLS_LE12           110           /* ARM       S + A - tp */
-#define R_ARM_TLS_IE12GP         111           /* ARM       GOT(S) + A - GOT_ORG */
-#define R_ARM_ME_TOO             128           /* Obsolete */
-#define R_ARM_THM_TLS_DESCSEQ16  129           /* Thumb16 */
-#define R_ARM_THM_TLS_DESCSEQ32  130           /* Thumb32 */
-
-/* 5.2.1 Platform architecture compatibility data */
-
-#define PT_ARM_ARCHEXT_FMTMSK       0xff000000
-#define PT_ARM_ARCHEXT_PROFMSK      0x00ff0000
-#define PT_ARM_ARCHEXT_ARCHMSK      0x000000ff
-
-#define PT_ARM_ARCHEXT_FMT_OS       0x00000000
-#define PT_ARM_ARCHEXT_FMT_ABI      0x01000000
-
-#define PT_ARM_ARCHEXT_PROF_NONE    0x00000000
-#define PT_ARM_ARCHEXT_PROF_ARM     0x00410000
-#define PT_ARM_ARCHEXT_PROF_RT      0x00520000
-#define PT_ARM_ARCHEXT_PROF_MC      0x004d0000
-#define PT_ARM_ARCHEXT_PROF_CLASSIC 0x00530000
-
-#define PT_ARM_ARCHEXT_ARCH_UNKNOWN 0x00
-#define PT_ARM_ARCHEXT_ARCHv4       0x01
-#define PT_ARM_ARCHEXT_ARCHv4T      0x02
-#define PT_ARM_ARCHEXT_ARCHv5T      0x03
-#define PT_ARM_ARCHEXT_ARCHv5TE     0x04
-#define PT_ARM_ARCHEXT_ARCHv5TEJ    0x05
-#define PT_ARM_ARCHEXT_ARCHv6       0x06
-#define PT_ARM_ARCHEXT_ARCHv6KZ     0x07
-#define PT_ARM_ARCHEXT_ARCHv6T2     0x08
-#define PT_ARM_ARCHEXT_ARCHv6K      0x09
-#define PT_ARM_ARCHEXT_ARCHv7       0x0a
-#define PT_ARM_ARCHEXT_ARCHv6M      0x0b
-#define PT_ARM_ARCHEXT_ARCHv6SM     0x0c
-#define PT_ARM_ARCHEXT_ARCHv7EM     0x0d
-
-/* Table 5-6, ARM-specific dynamic array tags */
-
-#define DT_ARM_RESERVED1         0x70000000
-#define DT_ARM_SYMTABSZ          0x70000001
-#define DT_ARM_PREEMPTMAP        0x70000002
-#define DT_ARM_RESERVED2         0x70000003
-
-#endif /* __ARCH_ARM_INCLUDE_ELF_H */

arch/arm/include/imx/irq.h

@@ -1,165 +0,0 @@
-/****************************************************************************
- * arch/arm/include/imx/irq.h
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_IMX_IRQ_H
-#define __ARCH_ARM_INCLUDE_IMX_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* i.MX1 Interrupts */
-
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_UART3PFERR         ( 0)
-#  define IMX_IRQ_UART3RTS           ( 1)
-#  define IMX_IRQ_UART3DTR           ( 2)
-#  define IMX_IRQ_UART3UARTC         ( 3)
-#  define IMX_IRQ_UART3TX            ( 4)
-#  define IMX_IRQ_PENUP              ( 5)
-#endif
-#define IMX_IRQ_CSI                  ( 6)
-#define IMX_IRQ_MMAMAC               ( 7)
-#define IMX_IRQ_MMA                  ( 8)
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_COMP               ( 9)
-#endif
-#define IMX_IRQ_MSHCXINT             (10)
-#define IMX_IRQ_GPIOPORTA            (11)
-#define IMX_IRQ_GPIOPORTB            (12)
-#define IMX_IRQ_GPIOPORTC            (13)
-#define IMX_IRQ_LCDC                 (14)
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_SIM                (15)
-#  define IMX_IRQ_SIMDATA            (16)
-#endif
-#define IMX_IRQ_RTC                  (17)
-#define IMX_IRQ_RTCSAMINT            (18)
-#define IMX_IRQ_UART2PFERR           (19)
-#define IMX_IRQ_UART2RTS             (20)
-#define IMX_IRQ_UART2DTR             (21)
-#define IMX_IRQ_UART2UARTC           (22)
-#define IMX_IRQ_UART2TX              (23)
-#define IMX_IRQ_UART2RX              (24)
-#define IMX_IRQ_UART1PFERR           (25)
-#define IMX_IRQ_UART1RTS             (26)
-#define IMX_IRQ_UART1DTR             (27)
-#define IMX_IRQ_UART1UARTC           (28)
-#define IMX_IRQ_UART1TX              (29)
-#define IMX_IRQ_UART1RX              (30)
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_PENDATA            (33)
-#endif
-#define IMX_IRQ_PWM                  (34)
-#define IMX_IRQ_MMCSD                (35)
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_SSI2TX             (36)
-#  define IMX_IRQ_SSI2RX             (37)
-#  define IMX_IRQ_SSI2ERR            (38)
-#endif
-#define IMX_IRQ_I2C                  (39)
-#define IMX_IRQ_CSPI2                (40)
-#define IMX_IRQ_CSPI1                (41)
-#define IMX_IRQ_SSITX                (42)
-#define IMX_IRQ_SSITXERR             (43)
-#define IMX_IRQ_SSIRX                (44)
-#define IMX_IRQ_SSIRXERR             (45)
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_TOUCH              (46)
-#endif
-#define IMX_IRQ_USBD0                (47)
-#define IMX_IRQ_USBD1                (48)
-#define IMX_IRQ_USBD2                (49)
-#define IMX_IRQ_USBD3                (50)
-#define IMX_IRQ_USBD4                (51)
-#define IMX_IRQ_USBD5                (52)
-#define IMX_IRQ_USBD6                (53)
-#ifndef CONFIG_ARCH_CHIP_IMXL
-#  define IMX_IRQ_UART3RX            (54)
-#  define IMX_IRQ_BTSYS              (55)
-#  define IMX_IRQ_BTTIM              (56)
-#  define IMX_IRQ_BTWUI              (57)
-#endif
-#define IMX_IRQ_TIMER2               (58)
-#define IMX_IRQ_TIMER1               (59)
-#define IMX_IRQ_DMAERR               (60)
-#define IMX_IRQ_DMA                  (61)
-#define IMX_IRQ_GPIOPORTD            (62)
-#define IMX_IRQ_WDT                  (63)
-
-#define IMX_IRQ_SYSTIMER             IMX_IRQ_TIMER1
-#define NR_IRQS                      (64)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_IMX_IRQ_H */
-

arch/arm/include/irq.h

@@ -1,106 +0,0 @@
-/****************************************************************************
- * arch/arm/include/irq.h
- *
- *   Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_IRQ_H
-#define __ARCH_ARM_INCLUDE_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/* Include NuttX-specific IRQ definitions */
-
-#include <nuttx/irq.h>
-
-/* Include chip-specific IRQ definitions (including IRQ numbers) */
-
-#include <arch/chip/irq.h>
-
-/* Include ARM architecture-specific IRQ definitions (including register
- * save structure and irqsave()/irqrestore() macros)
- */
-
-#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8)
-#  include <arch/armv7-a/irq.h>
-#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
-      defined(CONFIG_ARCH_CORTEXM7)
-#  include <arch/armv7-m/irq.h>
-#elif defined(CONFIG_ARCH_CORTEXM0)
-#  include <arch/armv6-m/irq.h>
-#else
-#  include <arch/arm/irq.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_IRQ_H */
-

arch/arm/include/kinetis/irq.h

@@ -1,423 +0,0 @@
-/************************************************************************************
- * arch/arm/include/kinetis/irq.h
- *
- *   Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_KINETIS_IRQ_H
-#define __ARCH_ARM_INCLUDE_KINETIS_IRQ_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/irq.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-/* IRQ numbers **********************************************************************/
-/* The IRQ numbers corresponds directly to vector numbers and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
- */
-
-/* Processor Exceptions (vectors 0-15) */
-
-#define KINETIS_IRQ_RESERVED      (0)   /* Reserved vector (only used with CONFIG_DEBUG) */
-                                        /* Vector  0: Reset stack pointer value */
-                                        /* Vector  1: Reset (not handler as an IRQ) */
-#define KINETIS_IRQ_NMI           (2)   /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define KINETIS_IRQ_HARDFAULT     (3)   /* Vector  3: Hard fault */
-#define KINETIS_IRQ_MEMFAULT      (4)   /* Vector  4: Memory management (MPU) */
-#define KINETIS_IRQ_BUSFAULT      (5)   /* Vector  5: Bus fault */
-#define KINETIS_IRQ_USAGEFAULT    (6)   /* Vector  6: Usage fault */
-                                        /* Vectors 7-10: Reserved */
-#define KINETIS_IRQ_SVCALL        (11)  /* Vector 11: SVC call */
-#define KINETIS_IRQ_DBGMONITOR    (12)  /* Vector 12: Debug Monitor */
-                                        /* Vector 13: Reserved */
-#define KINETIS_IRQ_PENDSV        (14)  /* Vector 14: Pendable system service request */
-#define KINETIS_IRQ_SYSTICK       (15)  /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16) */
-
-#define KINETIS_IRQ_EXTINT        (16)
-
-/* K20 Family ***********************************************************************
- *
- * The interrupt vectors  for the following parts is defined in Freescale document
- * K20P64M72SF1RM
- */
-
-#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
-#  define KINETIS_IRQ_DMACH0      (16)  /* Vector 16: DMA channel 0 transfer complete */
-#  define KINETIS_IRQ_DMACH1      (17)  /* Vector 17: DMA channel 1 transfer complete */
-#  define KINETIS_IRQ_DMACH2      (18)  /* Vector 18: DMA channel 2 transfer complete */
-#  define KINETIS_IRQ_DMACH3      (19)  /* Vector 19: DMA channel 3 transfer complete */
-#  define KINETIS_IRQ_DMACH4      (20)  /* Vector 20: DMA channel 4 transfer complete */
-#  define KINETIS_IRQ_DMACH5      (21)  /* Vector 21: DMA channel 5 transfer complete */
-#  define KINETIS_IRQ_DMACH6      (22)  /* Vector 22: DMA channel 6 transfer complete */
-#  define KINETIS_IRQ_DMACH7      (23)  /* Vector 23: DMA channel 7 transfer complete */
-#  define KINETIS_IRQ_DMACH8      (24)  /* Vector 24: DMA channel 8 transfer complete */
-#  define KINETIS_IRQ_DMACH9      (25)  /* Vector 25: DMA channel 9 transfer complete */
-#  define KINETIS_IRQ_DMACH10     (26)  /* Vector 26: DMA channel 10 transfer complete */
-#  define KINETIS_IRQ_DMACH11     (27)  /* Vector 27: DMA channel 11 transfer complete */
-#  define KINETIS_IRQ_DMACH12     (28)  /* Vector 28: DMA channel 12 transfer complete */
-#  define KINETIS_IRQ_DMACH13     (29)  /* Vector 29: DMA channel 13 transfer complete */
-#  define KINETIS_IRQ_DMACH14     (30)  /* Vector 30: DMA channel 14 transfer complete */
-#  define KINETIS_IRQ_DMACH15     (31)  /* Vector 31: DMA channel 15 transfer complete */
-#  define KINETIS_IRQ_DMAERR      (32)  /* Vector 32: DMA error interrupt channels 0-15 */
-#  define KINETIS_IRQ_FLASHCC     (34)  /* Vector 34: Flash memory command complete */
-#  define KINETIS_IRQ_FLASHRC     (35)  /* Vector 35: Flash memory read collision */
-#  define KINETIS_IRQ_SMCLVD      (36)  /* Vector 36: Mode Controller low-voltage
-                                         *            detect, low-voltage warning */
-#  define KINETIS_IRQ_LLWU        (37)  /* Vector 37: LLWU Normal Low Leakage Wakeup */
-#  define KINETIS_IRQ_WDOG        (38)  /* Vector 38: Watchdog */
-#  define KINETIS_IRQ_I2C0        (40)  /* Vector 40: I2C0 */
-#  define KINETIS_IRQ_I2C1        (41)  /* Vector 41: I2C1 */
-#  define KINETIS_IRQ_SPI0        (42)  /* Vector 42: SPI0 all sources */
-#  define KINETIS_IRQ_SPI1        (43)  /* Vector 43: SPI1 all sources */
-#  define KINETIS_IRQ_CAN0MB      (45)  /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
-#  define KINETIS_IRQ_CAN0BO      (46)  /* Vector 46: CAN0 Bus Off */
-#  define KINETIS_IRQ_CAN0ERR     (47)  /* Vector 47: CAN0 Error */
-#  define KINETIS_IRQ_CAN0TW      (48)  /* Vector 48: CAN0 Transmit Warning */
-#  define KINETIS_IRQ_CAN0RW      (49)  /* Vector 49: CAN0 Receive Warning */
-#  define KINETIS_IRQ_CAN0WU      (50)  /* Vector 50: CAN0 Wake UP */
-//TODO UART0_LON
-#  define KINETIS_IRQ_UART0S      (61)  /* Vector 61: UART0 status */
-#  define KINETIS_IRQ_UART0E      (62)  /* Vector 62: UART0 error */
-#  define KINETIS_IRQ_UART1S      (63)  /* Vector 63: UART1 status */
-#  define KINETIS_IRQ_UART1E      (64)  /* Vector 64: UART1 error */
-#  define KINETIS_IRQ_UART2S      (65)  /* Vector 65: UART2 status */
-#  define KINETIS_IRQ_UART2E      (66)  /* Vector 66: UART2 error */
-#  define KINETIS_IRQ_ADC0        (73)  /* Vector 73: ADC0 */
-#  define KINETIS_IRQ_ADC1        (74)  /* Vector 74: ADC1 */
-#  define KINETIS_IRQ_CMP0        (75)  /* Vector 75: CMP0 */
-#  define KINETIS_IRQ_CMP1        (76)  /* Vector 76: CMP1 */
-#  define KINETIS_IRQ_CMP2        (77)  /* Vector 77: CMP2 */
-#  define KINETIS_IRQ_FTM0        (78)  /* Vector 78: FTM0 all sources */
-#  define KINETIS_IRQ_FTM1        (79)  /* Vector 79: FTM1 all sources */
-#  define KINETIS_IRQ_FTM2        (80)  /* Vector 80: FTM2 all sources */
-#  define KINETIS_IRQ_CMT         (81)  /* Vector 81: CMT */
-#  define KINETIS_IRQ_RTC         (82)  /* Vector 82: RTC alarm interrupt */
-//TODO RTC_SECOND
-#  define KINETIS_IRQ_PITCH0      (84)  /* Vector 84: PIT channel 0 */
-#  define KINETIS_IRQ_PITCH1      (85)  /* Vector 85: PIT channel 1 */
-#  define KINETIS_IRQ_PITCH2      (86)  /* Vector 86: PIT channel 2 */
-#  define KINETIS_IRQ_PITCH3      (87)  /* Vector 87: PIT channel 3 */
-#  define KINETIS_IRQ_PDB         (88)  /* Vector 88: PDB */
-#  define KINETIS_IRQ_USBOTG      (89)  /* Vector 88: USB OTG */
-#  define KINETIS_IRQ_USBCD       (90)  /* Vector 90: USB charger detect */
-#  define KINETIS_IRQ_DAC0        (97)  /* Vector 97: DAC0 */
-#  define KINETIS_IRQ_TSI         (99)  /* Vector 97: TSI all sources */
-#  define KINETIS_IRQ_MCG         (100) /* Vector 100: MCG */
-#  define KINETIS_IRQ_LPT         (101) /* Vector 101: Low power timer */
-#  define KINETIS_IRQ_PORTA       (103) /* Vector 103: Pin detect port A */
-#  define KINETIS_IRQ_PORTB       (104) /* Vector 104: Pin detect port B */
-#  define KINETIS_IRQ_PORTC       (105) /* Vector 105: Pin detect port C */
-#  define KINETIS_IRQ_PORTD       (106) /* Vector 106: Pin detect port D */
-#  define KINETIS_IRQ_PORTE       (107) /* Vector 107: Pin detect port E */
-#  define KINETIS_IRQ_SWI         (110) /* Vector 110: Software interrupt */
-
-#  define NR_VECTORS              (111) /* 111 vectors */
-#  define NR_IRQS                 (111) /* 94 interrupts but 111 IRQ numbers */
-
-/* K40 Family ***********************************************************************
- *
- * The interrupt vectors  for the following parts is defined in Freescale document
- * K40P144M100SF2RM
- */
-
-#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
-    defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
-    defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
-
-#  define KINETIS_IRQ_DMACH0      (16)  /* Vector 16: DMA channel 0 transfer complete */
-#  define KINETIS_IRQ_DMACH1      (17)  /* Vector 17: DMA channel 1 transfer complete */
-#  define KINETIS_IRQ_DMACH2      (18)  /* Vector 18: DMA channel 2 transfer complete */
-#  define KINETIS_IRQ_DMACH3      (19)  /* Vector 19: DMA channel 3 transfer complete */
-#  define KINETIS_IRQ_DMACH4      (20)  /* Vector 20: DMA channel 4 transfer complete */
-#  define KINETIS_IRQ_DMACH5      (21)  /* Vector 21: DMA channel 5 transfer complete */
-#  define KINETIS_IRQ_DMACH6      (22)  /* Vector 22: DMA channel 6 transfer complete */
-#  define KINETIS_IRQ_DMACH7      (23)  /* Vector 23: DMA channel 7 transfer complete */
-#  define KINETIS_IRQ_DMACH8      (24)  /* Vector 24: DMA channel 8 transfer complete */
-#  define KINETIS_IRQ_DMACH9      (25)  /* Vector 25: DMA channel 9 transfer complete */
-#  define KINETIS_IRQ_DMACH10     (26)  /* Vector 26: DMA channel 10 transfer complete */
-#  define KINETIS_IRQ_DMACH11     (27)  /* Vector 27: DMA channel 11 transfer complete */
-#  define KINETIS_IRQ_DMACH12     (28)  /* Vector 28: DMA channel 12 transfer complete */
-#  define KINETIS_IRQ_DMACH13     (29)  /* Vector 29: DMA channel 13 transfer complete */
-#  define KINETIS_IRQ_DMACH14     (30)  /* Vector 30: DMA channel 14 transfer complete */
-#  define KINETIS_IRQ_DMACH15     (31)  /* Vector 31: DMA channel 15 transfer complete */
-#  define KINETIS_IRQ_DMAERR      (32)  /* Vector 32: DMA error interrupt channels 0-15 */
-#  define KINETIS_IRQ_MCM         (33)  /* Vector 33: MCM Normal interrupt */
-#  define KINETIS_IRQ_FLASHCC     (34)  /* Vector 34: Flash memory command complete */
-#  define KINETIS_IRQ_FLASHRC     (35)  /* Vector 35: Flash memory read collision */
-#  define KINETIS_IRQ_SMCLVD      (36)  /* Vector 36: Mode Controller low-voltage
-                                         *            detect, low-voltage warning */
-#  define KINETIS_IRQ_LLWU        (37)  /* Vector 37: LLWU Normal Low Leakage Wakeup */
-#  define KINETIS_IRQ_WDOG        (38)  /* Vector 38: Watchdog */
-                                        /* Vector 39: Reserved */
-#  define KINETIS_IRQ_I2C0        (40)  /* Vector 40: I2C0 */
-#  define KINETIS_IRQ_I2C1        (41)  /* Vector 41: I2C1 */
-#  define KINETIS_IRQ_SPI0        (42)  /* Vector 42: SPI0 all sources */
-#  define KINETIS_IRQ_SPI1        (43)  /* Vector 43: SPI1 all sources */
-#  define KINETIS_IRQ_SPI2        (44)  /* Vector 44: SPI2 all sources */
-#  define KINETIS_IRQ_CAN0MB      (45)  /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
-#  define KINETIS_IRQ_CAN0BO      (46)  /* Vector 46: CAN0 Bus Off */
-#  define KINETIS_IRQ_CAN0ERR     (47)  /* Vector 47: CAN0 Error */
-#  define KINETIS_IRQ_CAN0TW      (48)  /* Vector 48: CAN0 Transmit Warning */
-#  define KINETIS_IRQ_CAN0RW      (49)  /* Vector 49: CAN0 Receive Warning */
-#  define KINETIS_IRQ_CAN0WU      (50)  /* Vector 50: CAN0 Wake UP */
-                                        /* Vectors 51-52: Reserved */
-#  define KINETIS_IRQ_CAN1MB      (53)  /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
-#  define KINETIS_IRQ_CAN1BO      (54)  /* Vector 54: CAN1 Bus Off */
-#  define KINETIS_IRQ_CAN1ERR     (55)  /* Vector 55: CAN1 Error */
-#  define KINETIS_IRQ_CAN1TW      (56)  /* Vector 56: CAN1 Transmit Warning */
-#  define KINETIS_IRQ_CAN1RW      (57)  /* Vector 57: CAN1 Receive Warning */
-#  define KINETIS_IRQ_CAN1WU      (58)  /* Vector 58: CAN1 Wake UP */
-                                        /* Vectors 59-60: Reserved */
-#  define KINETIS_IRQ_UART0S      (61)  /* Vector 61: UART0 status */
-#  define KINETIS_IRQ_UART0E      (62)  /* Vector 62: UART0 error */
-#  define KINETIS_IRQ_UART1S      (63)  /* Vector 63: UART1 status */
-#  define KINETIS_IRQ_UART1E      (64)  /* Vector 64: UART1 error */
-#  define KINETIS_IRQ_UART2S      (65)  /* Vector 65: UART2 status */
-#  define KINETIS_IRQ_UART2E      (66)  /* Vector 66: UART2 error */
-#  define KINETIS_IRQ_UART3S      (67)  /* Vector 67: UART3 status */
-#  define KINETIS_IRQ_UART3E      (68)  /* Vector 68: UART3 error */
-#  define KINETIS_IRQ_UART4S      (69)  /* Vector 69: UART4 status */
-#  define KINETIS_IRQ_UART4E      (70)  /* Vector 70: UART4 error */
-#  define KINETIS_IRQ_UART5S      (71)  /* Vector 71: UART5 status */
-#  define KINETIS_IRQ_UART5E      (72)  /* Vector 72: UART5 error */
-#  define KINETIS_IRQ_ADC0        (73)  /* Vector 73: ADC0 */
-#  define KINETIS_IRQ_ADC1        (74)  /* Vector 74: ADC1 */
-#  define KINETIS_IRQ_CMP0        (75)  /* Vector 75: CMP0 */
-#  define KINETIS_IRQ_CMP1        (76)  /* Vector 76: CMP1 */
-#  define KINETIS_IRQ_CMP2        (77)  /* Vector 77: CMP2 */
-#  define KINETIS_IRQ_FTM0        (78)  /* Vector 78: FTM0 all sources */
-#  define KINETIS_IRQ_FTM1        (79)  /* Vector 79: FTM1 all sources */
-#  define KINETIS_IRQ_FTM2        (80)  /* Vector 80: FTM2 all sources */
-#  define KINETIS_IRQ_CMT         (81)  /* Vector 81: CMT */
-#  define KINETIS_IRQ_RTC         (82)  /* Vector 82: RTC alarm interrupt */
-                                        /* Vector 83: Reserved */
-#  define KINETIS_IRQ_PITCH0      (84)  /* Vector 84: PIT channel 0 */
-#  define KINETIS_IRQ_PITCH1      (85)  /* Vector 85: PIT channel 1 */
-#  define KINETIS_IRQ_PITCH2      (86)  /* Vector 86: PIT channel 2 */
-#  define KINETIS_IRQ_PITCH3      (87)  /* Vector 87: PIT channel 3 */
-#  define KINETIS_IRQ_PDB         (88)  /* Vector 88: PDB */
-#  define KINETIS_IRQ_USBOTG      (89)  /* Vector 88: USB OTG */
-#  define KINETIS_IRQ_USBCD       (90)  /* Vector 90: USB charger detect */
-                                        /* Vectors 91-94: Reserved */
-#  define KINETIS_IRQ_I2S0        (95)  /* Vector 95: I2S0 */
-#  define KINETIS_IRQ_SDHC        (96)  /* Vector 96: SDHC */
-#  define KINETIS_IRQ_DAC0        (97)  /* Vector 97: DAC0 */
-#  define KINETIS_IRQ_DAC1        (98)  /* Vector 98: DAC1 */
-#  define KINETIS_IRQ_TSI         (99)  /* Vector 97: TSI all sources */
-#  define KINETIS_IRQ_MCG         (100) /* Vector 100: MCG */
-#  define KINETIS_IRQ_LPT         (101) /* Vector 101: Low power timer */
-#  define KINETIS_IRQ_SLCD        (102) /* Vector 102: Segment LCD all sources */
-#  define KINETIS_IRQ_PORTA       (103) /* Vector 103: Pin detect port A */
-#  define KINETIS_IRQ_PORTB       (104) /* Vector 104: Pin detect port B */
-#  define KINETIS_IRQ_PORTC       (105) /* Vector 105: Pin detect port C */
-#  define KINETIS_IRQ_PORTD       (106) /* Vector 106: Pin detect port D */
-#  define KINETIS_IRQ_PORTE       (107) /* Vector 107: Pin detect port E */
-                                        /* Vectors 108-109: Reserved */
-#  define KINETIS_IRQ_SWI         (110) /* Vector 110: Software interrupt */
-
-/* Note that the total number of IRQ numbers supported is equal to the number of
- * valid interrupt vectors.  This is wasteful in that certain tables are sized by
- * this value.  There are only 94 valid interrupts so, potentially the numver of
- * IRQs to could be reduced to 94.  However, equating IRQ numbers with vector numbers
- * also simplifies operations on NVIC registers and (at least in my state of mind
- * now) seems to justify the waste.
- */
-
-#  define NR_VECTORS              (111) /* 111 vectors */
-#  define NR_IRQS                 (111) /* 94 interrupts but 111 IRQ numbers */
-
-/* K60 Family ***********************************************************************
- *
- * The memory map for the following parts is defined in Freescale document
- * K60P144M100SF2RM
- */
-
-#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
-      defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
-      defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
-
-#  define KINETIS_IRQ_DMACH0      (16)  /* Vector 16: DMA channel 0 transfer complete */
-#  define KINETIS_IRQ_DMACH1      (17)  /* Vector 17: DMA channel 1 transfer complete */
-#  define KINETIS_IRQ_DMACH2      (18)  /* Vector 18: DMA channel 2 transfer complete */
-#  define KINETIS_IRQ_DMACH3      (19)  /* Vector 19: DMA channel 3 transfer complete */
-#  define KINETIS_IRQ_DMACH4      (20)  /* Vector 20: DMA channel 4 transfer complete */
-#  define KINETIS_IRQ_DMACH5      (21)  /* Vector 21: DMA channel 5 transfer complete */
-#  define KINETIS_IRQ_DMACH6      (22)  /* Vector 22: DMA channel 6 transfer complete */
-#  define KINETIS_IRQ_DMACH7      (23)  /* Vector 23: DMA channel 7 transfer complete */
-#  define KINETIS_IRQ_DMACH8      (24)  /* Vector 24: DMA channel 8 transfer complete */
-#  define KINETIS_IRQ_DMACH9      (25)  /* Vector 25: DMA channel 9 transfer complete */
-#  define KINETIS_IRQ_DMACH10     (26)  /* Vector 26: DMA channel 10 transfer complete */
-#  define KINETIS_IRQ_DMACH11     (27)  /* Vector 27: DMA channel 11 transfer complete */
-#  define KINETIS_IRQ_DMACH12     (28)  /* Vector 28: DMA channel 12 transfer complete */
-#  define KINETIS_IRQ_DMACH13     (29)  /* Vector 29: DMA channel 13 transfer complete */
-#  define KINETIS_IRQ_DMACH14     (30)  /* Vector 30: DMA channel 14 transfer complete */
-#  define KINETIS_IRQ_DMACH15     (31)  /* Vector 31: DMA channel 15 transfer complete */
-#  define KINETIS_IRQ_DMAERR      (32)  /* Vector 32: DMA error interrupt channels 0-15 */
-#  define KINETIS_IRQ_MCM         (33)  /* Vector 33: MCM Normal interrupt */
-#  define KINETIS_IRQ_FLASHCC     (34)  /* Vector 34: Flash memory command complete */
-#  define KINETIS_IRQ_FLASHRC     (35)  /* Vector 35: Flash memory read collision */
-#  define KINETIS_IRQ_SMCLVD      (36)  /* Vector 36: Mode Controller low-voltage
-                                         *            detect, low-voltage warning */
-#  define KINETIS_IRQ_LLWU        (37)  /* Vector 37: LLWU Normal Low Leakage Wakeup */
-#  define KINETIS_IRQ_WDOG        (38)  /* Vector 38: Watchdog */
-#  define KINETIS_IRQ_RNGB        (39)  /* Vector 39: Random number generator */
-#  define KINETIS_IRQ_I2C0        (40)  /* Vector 40: I2C0 */
-#  define KINETIS_IRQ_I2C1        (41)  /* Vector 41: I2C1 */
-#  define KINETIS_IRQ_SPI0        (42)  /* Vector 42: SPI0 all sources */
-#  define KINETIS_IRQ_SPI1        (43)  /* Vector 43: SPI1 all sources */
-#  define KINETIS_IRQ_SPI2        (44)  /* Vector 44: SPI2 all sources */
-#  define KINETIS_IRQ_CAN0MB      (45)  /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
-#  define KINETIS_IRQ_CAN0BO      (46)  /* Vector 46: CAN0 Bus Off */
-#  define KINETIS_IRQ_CAN0ERR     (47)  /* Vector 47: CAN0 Error */
-#  define KINETIS_IRQ_CAN0TW      (48)  /* Vector 48: CAN0 Transmit Warning */
-#  define KINETIS_IRQ_CAN0RW      (49)  /* Vector 49: CAN0 Receive Warning */
-#  define KINETIS_IRQ_CAN0WU      (50)  /* Vector 50: CAN0 Wake UP */
-                                        /* Vectors 51-52: Reserved */
-#  define KINETIS_IRQ_CAN1MB      (53)  /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
-#  define KINETIS_IRQ_CAN1BO      (54)  /* Vector 54: CAN1 Bus Off */
-#  define KINETIS_IRQ_CAN1ERR     (55)  /* Vector 55: CAN1 Error */
-#  define KINETIS_IRQ_CAN1TW      (56)  /* Vector 56: CAN1 Transmit Warning */
-#  define KINETIS_IRQ_CAN1RW      (57)  /* Vector 57: CAN1 Receive Warning */
-#  define KINETIS_IRQ_CAN1WU      (58)  /* Vector 58: CAN1 Wake UP */
-                                        /* Vectors 59-60: Reserved */
-#  define KINETIS_IRQ_UART0S      (61)  /* Vector 61: UART0 status */
-#  define KINETIS_IRQ_UART0E      (62)  /* Vector 62: UART0 error */
-#  define KINETIS_IRQ_UART1S      (63)  /* Vector 63: UART1 status */
-#  define KINETIS_IRQ_UART1E      (64)  /* Vector 64: UART1 error */
-#  define KINETIS_IRQ_UART2S      (65)  /* Vector 65: UART2 status */
-#  define KINETIS_IRQ_UART2E      (66)  /* Vector 66: UART2 error */
-#  define KINETIS_IRQ_UART3S      (67)  /* Vector 67: UART3 status */
-#  define KINETIS_IRQ_UART3E      (68)  /* Vector 68: UART3 error */
-#  define KINETIS_IRQ_UART4S      (69)  /* Vector 69: UART4 status */
-#  define KINETIS_IRQ_UART4E      (70)  /* Vector 70: UART4 error */
-#  define KINETIS_IRQ_UART5S      (71)  /* Vector 71: UART5 status */
-#  define KINETIS_IRQ_UART5E      (72)  /* Vector 72: UART5 error */
-#  define KINETIS_IRQ_ADC0        (73)  /* Vector 73: ADC0 */
-#  define KINETIS_IRQ_ADC1        (74)  /* Vector 74: ADC1 */
-#  define KINETIS_IRQ_CMP0        (75)  /* Vector 75: CMP0 */
-#  define KINETIS_IRQ_CMP1        (76)  /* Vector 76: CMP1 */
-#  define KINETIS_IRQ_CMP2        (77)  /* Vector 77: CMP2 */
-#  define KINETIS_IRQ_FTM0        (78)  /* Vector 78: FTM0 all sources */
-#  define KINETIS_IRQ_FTM1        (79)  /* Vector 79: FTM1 all sources */
-#  define KINETIS_IRQ_FTM2        (80)  /* Vector 80: FTM2 all sources */
-#  define KINETIS_IRQ_CMT         (81)  /* Vector 81: CMT */
-#  define KINETIS_IRQ_RTC         (82)  /* Vector 82: RTC alarm interrupt */
-                                        /* Vector 83: Reserved */
-#  define KINETIS_IRQ_PITCH0      (84)  /* Vector 84: PIT channel 0 */
-#  define KINETIS_IRQ_PITCH1      (85)  /* Vector 85: PIT channel 1 */
-#  define KINETIS_IRQ_PITCH2      (86)  /* Vector 86: PIT channel 2 */
-#  define KINETIS_IRQ_PITCH3      (87)  /* Vector 87: PIT channel 3 */
-#  define KINETIS_IRQ_PDB         (88)  /* Vector 88: PDB */
-#  define KINETIS_IRQ_USBOTG      (89)  /* Vector 88: USB OTG */
-#  define KINETIS_IRQ_USBCD       (90)  /* Vector 90: USB charger detect */
-#  define KINETIS_IRQ_EMACTMR     (91)  /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
-#  define KINETIS_IRQ_EMACTX      (92)  /* Vector 92: Ethernet MAC transmit interrupt */
-#  define KINETIS_IRQ_EMACRX      (93)  /* Vector 93: Ethernet MAC receive interrupt */
-#  define KINETIS_IRQ_EMACMISC    (94)  /* Vector 94: Ethernet MAC error and misc interrupt */
-#  define KINETIS_IRQ_I2S0        (95)  /* Vector 95: I2S0 */
-#  define KINETIS_IRQ_SDHC        (96)  /* Vector 96: SDHC */
-#  define KINETIS_IRQ_DAC0        (97)  /* Vector 97: DAC0 */
-#  define KINETIS_IRQ_DAC1        (98)  /* Vector 98: DAC1 */
-#  define KINETIS_IRQ_TSI         (99)  /* Vector 97: TSI all sources */
-#  define KINETIS_IRQ_MCG         (100) /* Vector 100: MCG */
-#  define KINETIS_IRQ_LPT         (101) /* Vector 101: Low power timer */
-                                        /* Vector 102: Reserved */
-#  define KINETIS_IRQ_PORTA       (103) /* Vector 103: Pin detect port A */
-#  define KINETIS_IRQ_PORTB       (104) /* Vector 104: Pin detect port B */
-#  define KINETIS_IRQ_PORTC       (105) /* Vector 105: Pin detect port C */
-#  define KINETIS_IRQ_PORTD       (106) /* Vector 106: Pin detect port D */
-#  define KINETIS_IRQ_PORTE       (107) /* Vector 107: Pin detect port E */
-                                        /* Vectors 108-119: Reserved */
-
-/* Note that the total number of IRQ numbers supported is equal to the number of
- * valid interrupt vectors.  This is wasteful in that certain tables are sized by
- * this value.  There are only 97 valid interrupts so, potentially the number of
- * IRQs to could be reduced to 97.  However, equating IRQ numbers with vector numbers
- * also simplifies operations on NVIC registers and (at least in my state of mind
- * now) seems to justify the waste.
- */
-
-#  define NR_VECTORS              (120) /* 120 vectors */
-#  define NR_IRQS                 (108) /* 120 interrupts but 108 IRQ numbers */
-
-#else
-  /* The interrupt vectors for other parts are defined in other documents and may or
-   * may not be the same as above (the family members are all very similar)  This
-   * error just means that you have to look at the document and determine for yourself
-   * if the vectors are the same.
-   */
-
-#  error "No IRQ numbers for this Kinetis part"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_KINETIS_IRQ_H */
-

arch/arm/include/kl/chip.h

@@ -1,193 +0,0 @@
-/************************************************************************************
- * arch/arm/include/kinetis/chip.h
- *
- *   Copyright (C) 2013, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_KL_CHIP_H
-#define __ARCH_ARM_INCLUDE_KL_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Get customizations for each supported chip */
-
-#if defined(CONFIG_ARCH_CHIP_MKL25Z64)
-
-#  define KL_Z64             1          /* Kinetics KL25Z128 family */
-#  define KL_FLASH_SIZE      (64*1024)  /* 64Kb */
-#  define KL_SRAM_SIZE       (8*1024)   /* 8Kb */
-#  undef  KL_MPU                        /* No memory protection unit */
-#  undef  KL_EXTBUS                     /* No external bus interface */
-#  define KL_NDMACH          4          /* Up to 4 DMA channels */
-#  undef  KL_NENET                      /* No Ethernet controller */
-#  define KL_NUSBHOST        1          /* One USB host controller */
-#  define KL_NUSBOTG         1          /* With USB OTG controller */
-#  define KL_NUSBDEV         1          /* One USB device controller */
-#  undef  KL_NSDHC                      /* No SD host controller */
-#  define KL_NTOUCHIF        1          /* Xtrinsic touch sensing interface */
-#  define KL_NI2C            2          /* Two I2C modules */
-#  define KL_NUART           3          /* Three UARTs */
-#  define KL_NSPI            2          /* Two SPI modules */
-#  undef  KL_NCAN                       /* No CAN in 64-pin chips */
-#  define KL_NI2S            1          /* One I2S module */
-#  undef  KL_NSLCD                      /* One segment LCD interface (up to 25x8/29x4) */
-#  define KL_NADC16          1          /* One 16-bit ADC */
-#  undef  KL_NADC12                     /* No 12-channel ADC */
-#  undef  KL_NADC13                     /* No 13-channel ADC */
-#  undef  KL_NADC15                     /* No 15-channel ADC */
-#  undef  KL_NADC18                     /* No 18-channel ADC */
-#  undef  KL_NPGA                       /* No Programmable Gain Amplifiers */
-#  define KL_NCMP            1          /* One analog comparator */
-#  define KL_NDAC6           1          /* Three 6-bit DAC */
-#  define KL_NDAC12          1          /* Two 12-bit DAC */
-#  define KL_NVREF           1          /* Voltage reference */
-#  define KL_NTIMERS6        1          /* One 6 channel timer */
-#  define KL_NTIMERS2        2          /* Two 2 channel timers */
-#  undef  KL_NRNG                       /* No random number generator */
-#  define KL_NRTC            1          /* Real time clock */
-#  undef  KL_NMMCAU                     /* No hardware encryption */
-#  undef  KL_NTAMPER                    /* No tamper detect */
-#  undef  KL_NCRC                       /* No CRC */
-
-#elif defined(CONFIG_ARCH_CHIP_MKL25Z128)
-
-#  define KL_Z128            1          /* Kinetics KL25Z128 family */
-#  define KL_FLASH_SIZE      (128*1024) /* 64Kb */
-#  define KL_SRAM_SIZE       (16*1024)  /* 16Kb */
-#  undef  KL_MPU                        /* No memory protection unit */
-#  undef  KL_EXTBUS                     /* No external bus interface */
-#  define KL_NDMACH          4          /* Up to 4 DMA channels */
-#  undef  KL_NENET                      /* No Ethernet controller */
-#  define KL_NUSBHOST        1          /* One USB host controller */
-#  define KL_NUSBOTG         1          /* With USB OTG controller */
-#  define KL_NUSBDEV         1          /* One USB device controller */
-#  undef  KL_NSDHC                      /* No SD host controller */
-#  define KL_NTOUCHIF        1          /* Xtrinsic touch sensing interface */
-#  define KL_NI2C            2          /* Two I2C modules */
-#  define KL_NUART           3          /* Three UARTs */
-#  define KL_NSPI            2          /* Two SPI modules */
-#  undef  KL_NCAN                       /* No CAN in 64-pin chips */
-#  define KL_NI2S            1          /* One I2S module */
-#  undef  KL_NSLCD                      /* One segment LCD interface (up to 25x8/29x4) */
-#  define KL_NADC16          1          /* One 16-bit ADC */
-#  undef  KL_NADC12                     /* No 12-channel ADC */
-#  undef  KL_NADC13                     /* No 13-channel ADC */
-#  undef  KL_NADC15                     /* No 15-channel ADC */
-#  undef  KL_NADC18                     /* No 18-channel ADC */
-#  undef  KL_NPGA                       /* No Programmable Gain Amplifiers */
-#  define KL_NCMP            1          /* One analog comparator */
-#  define KL_NDAC6           1          /* Three 6-bit DAC */
-#  define KL_NDAC12          1          /* Two 12-bit DAC */
-#  define KL_NVREF           1          /* Voltage reference */
-#  define KL_NTIMERS8        1          /* One 8 channel timers */
-#  undef  KL_NTIMERS12                  /* No 12 channel timers */
-#  undef  KL_NTIMERS20                  /* No 20 channel timers */
-#  undef  KL_NRNG                       /* No random number generator */
-#  define KL_NRTC            1          /* Real time clock */
-#  undef  KL_NMMCAU                     /* No hardware encryption */
-#  undef  KL_NTAMPER                    /* No tamper detect */
-#  undef  KL_NCRC                       /* No CRC */
-
-#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
-
-#  define KL_Z128            1          /* Kinetics KL25Z128 family */
-#  define KL_FLASH_SIZE      (128*1024) /* 64Kb */
-#  define KL_SRAM_SIZE       (16*1024)  /* 16Kb */
-#  undef  KL_MPU                        /* No memory protection unit */
-#  undef  KL_EXTBUS                     /* No external bus interface */
-#  define KL_NDMACH          4          /* Up to 4 DMA channels */
-#  undef  KL_NENET                      /* No Ethernet controller */
-#  define KL_NUSBHOST        1          /* One USB host controller */
-#  define KL_NUSBOTG         1          /* With USB OTG controller */
-#  define KL_NUSBDEV         1          /* One USB device controller */
-#  undef  KL_NSDHC                      /* No SD host controller */
-#  define KL_NTOUCHIF        1          /* Xtrinsic touch sensing interface */
-#  define KL_NI2C            2          /* Two I2C modules */
-#  define KL_NUART           3          /* Three UARTs */
-#  define KL_NSPI            2          /* Two SPI modules */
-#  undef  KL_NCAN                       /* No CAN in 64-pin chips */
-#  define KL_NI2S            1          /* One I2S module */
-#  undef  KL_NSLCD                      /* One segment LCD interface (up to 25x8/29x4) */
-#  define KL_NADC16          1          /* One 16-bit ADC */
-#  undef  KL_NADC12                     /* No 12-channel ADC */
-#  undef  KL_NADC13                     /* No 13-channel ADC */
-#  undef  KL_NADC15                     /* No 15-channel ADC */
-#  undef  KL_NADC18                     /* No 18-channel ADC */
-#  undef  KL_NPGA                       /* No Programmable Gain Amplifiers */
-#  define KL_NCMP            1          /* One analog comparator */
-#  define KL_NDAC6           1          /* Three 6-bit DAC */
-#  define KL_NDAC12          1          /* Two 12-bit DAC */
-#  define KL_NVREF           1          /* Voltage reference */
-#  define KL_NTIMERS8        1          /* One 8 channel timers */
-#  undef  KL_NTIMERS12                  /* No 12 channel timers */
-#  undef  KL_NTIMERS20                  /* No 20 channel timers */
-#  undef  KL_NRNG                       /* No random number generator */
-#  define KL_NRTC            1          /* Real time clock */
-#  undef  KL_NMMCAU                     /* No hardware encryption */
-#  undef  KL_NTAMPER                    /* No tamper detect */
-#  undef  KL_NCRC                       /* No CRC */
-
-#else
-#  error "Unsupported Kinetis chip"
-#endif
-
-/* NVIC priority levels *************************************************************/
-/* Each priority field holds a priority value, 0-15. The lower the value, the greater
- * the priority of the corresponding interrupt. The processor implements only
- * bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
- */
-
-#define NVIC_SYSH_PRIORITY_MIN     0xc0 /* All bits[7:6] set is minimum priority */
-#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
-#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP    0x40 /* Steps between supported priority values */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-#endif /* __ARCH_ARM_INCLUDE_KL_CHIP_H */

arch/arm/include/kl/irq.h

@@ -1,212 +0,0 @@
-/************************************************************************************
- * arch/arm/include/kinetis/irq.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_KL_IRQ_H
-#define __ARCH_ARM_INCLUDE_KL_IRQ_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/irq.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-/* IRQ numbers **********************************************************************/
-/* The IRQ numbers corresponds directly to vector numbers and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
- */
-
-/* Processor Exceptions (vectors 0-15) */
-
-#define KL_IRQ_RESERVED      (0)   /* Reserved vector (only used with CONFIG_DEBUG) */
-                                        /* Vector  0: Reset stack pointer value */
-                                        /* Vector  1: Reset (not handler as an IRQ) */
-#define KL_IRQ_NMI           (2)   /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define KL_IRQ_HARDFAULT     (3)   /* Vector  3: Hard fault */
-                                        /* Vectors 4-10: Reserved */
-#define KL_IRQ_SVCALL        (11)  /* Vector 11: SVC call */
-                                        /* Vector 12-13: Reserved */
-#define KL_IRQ_PENDSV        (14)  /* Vector 14: Pendable system service request */
-#define KL_IRQ_SYSTICK       (15)  /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16) */
-
-#define KL_IRQ_EXTINT        (16)
-
-/* K40 Family ***********************************************************************
- *
- * The interrupt vectors  for the following parts is defined in Freescale document
- * K40P144M100SF2RM
- */
-
-#if defined(CONFIG_ARCH_CHIP_MKL25Z128) || defined(CONFIG_ARCH_CHIP_MKL25Z64)
-
-#  define KL_IRQ_DMACH0        (16)  /* Vector 16: DMA channel 0 transfer complete */
-#  define KL_IRQ_DMACH1        (17)  /* Vector 17: DMA channel 1 transfer complete */
-#  define KL_IRQ_DMACH2        (18)  /* Vector 18: DMA channel 2 transfer complete */
-#  define KL_IRQ_DMACH3        (19)  /* Vector 19: DMA channel 3 transfer complete */
-                                     /* Vector 20: Reserved */
-#  define KL_IRQ_FTFA          (21)  /* Vector 21: FTFA */
-#  define KL_IRQ_LVDLVW        (22)  /* Vector 22: LVD_LVW */
-#  define KL_IRQ_LLW           (23)  /* Vector 23: LLW */
-#  define KL_IRQ_I2C0          (24)  /* Vector 24: I2C0 */
-#  define KL_IRQ_I2C1          (25)  /* Vector 25: I2C1 */
-#  define KL_IRQ_SPI0          (26)  /* Vector 26: SPI0 */
-#  define KL_IRQ_SPI1          (27)  /* Vector 27: SPI1 */
-#  define KL_IRQ_UART0         (28)  /* Vector 28: UART0 */
-#  define KL_IRQ_UART1         (29)  /* Vector 29: UART1 */
-#  define KL_IRQ_UART2         (30)  /* Vector 30: UART2 */
-#  define KL_IRQ_ADC0          (31)  /* Vector 31: Analog Device Converter 0 */
-#  define KL_IRQ_CMP0          (32)  /* Vector 32: Comparator 0 */
-#  define KL_IRQ_TPM0          (33)  /* Vector 33: Timer/PWM Module 0 */
-#  define KL_IRQ_TPM1          (34)  /* Vector 34: Timer/PWM Module 1 */
-#  define KL_IRQ_TPM2          (35)  /* Vector 35: Timer/PWM Module 2 */
-#  define KL_IRQ_RTC           (36)  /* Vector 36: Realtime Clock */
-#  define KL_IRQ_RTCSEC        (37)  /* Vector 37: Realtime Clock, seconds interrupt */
-#  define KL_IRQ_PIT           (38)  /* Vector 38: Programmable Interrupt Timer */
-                                     /* Vector 39: Reserved */
-#  define KL_IRQ_USB0          (40)  /* Vector 40: USB0 */
-#  define KL_IRQ_DAC0          (41)  /* Vector 41: Digital Analog Converter 0 */
-#  define KL_IRQ_TSI0          (42)  /* Vector 42: TSI0 */
-#  define KL_IRQ_MCG           (43)  /* Vector 43: MCG */
-#  define KL_IRQ_LPTIMER       (44)  /* Vector 44: Low Power Timer */
-                                     /* Vector 45: Reserved */
-#  define KL_IRQ_PORTA         (46)  /* Vector 46: GPIO Port A */
-#  define KL_IRQ_PORTD         (47)  /* Vector 47: GPIO Port D */
-
-/* Note that the total number of IRQ numbers supported is equal to the number of
- * valid interrupt vectors.  This is wasteful in that certain tables are sized by
- * this value.  There are only 94 valid interrupts so, potentially the numver of
- * IRQs to could be reduced to 94.  However, equating IRQ numbers with vector numbers
- * also simplifies operations on NVIC registers and (at least in my state of mind
- * now) seems to justify the waste.
- */
-
-#  define NR_VECTORS           (64) /* 64 vectors */
-#  define NR_IRQS              (48) /* 64 interrupts but 48 IRQ numbers */
-
-#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
-
-#  define KL_IRQ_DMACH0        (16)  /* Vector 16: DMA channel 0 transfer complete */
-#  define KL_IRQ_DMACH1        (17)  /* Vector 17: DMA channel 1 transfer complete */
-#  define KL_IRQ_DMACH2        (18)  /* Vector 18: DMA channel 2 transfer complete */
-#  define KL_IRQ_DMACH3        (19)  /* Vector 19: DMA channel 3 transfer complete */
-                                     /* Vector 20: Reserved */
-#  define KL_IRQ_FTFA          (21)  /* Vector 21: FTFA */
-#  define KL_IRQ_LVDLVW        (22)  /* Vector 22: LVD_LVW */
-#  define KL_IRQ_LLW           (23)  /* Vector 23: LLW */
-#  define KL_IRQ_I2C0          (24)  /* Vector 24: I2C0 */
-#  define KL_IRQ_I2C1          (25)  /* Vector 25: I2C1 */
-#  define KL_IRQ_SPI0          (26)  /* Vector 26: SPI0 */
-#  define KL_IRQ_SPI1          (27)  /* Vector 27: SPI1 */
-#  define KL_IRQ_UART0         (28)  /* Vector 28: UART0 */
-#  define KL_IRQ_UART1         (29)  /* Vector 29: UART1 */
-#  define KL_IRQ_UART2         (30)  /* Vector 30: UART2 */
-#  define KL_IRQ_ADC0          (31)  /* Vector 31: Analog Device Converter 0 */
-#  define KL_IRQ_CMP0          (32)  /* Vector 32: Comparator 0 */
-#  define KL_IRQ_TPM0          (33)  /* Vector 33: Timer/PWM Module 0 */
-#  define KL_IRQ_TPM1          (34)  /* Vector 34: Timer/PWM Module 1 */
-#  define KL_IRQ_TPM2          (35)  /* Vector 35: Timer/PWM Module 2 */
-#  define KL_IRQ_RTC           (36)  /* Vector 36: Realtime Clock */
-#  define KL_IRQ_RTCSEC        (37)  /* Vector 37: Realtime Clock, seconds interrupt */
-#  define KL_IRQ_PIT           (38)  /* Vector 38: Programmable Interrupt Timer */
-                                     /* Vector 39: Reserved */
-#  define KL_IRQ_USB0          (40)  /* Vector 40: USB0 */
-#  define KL_IRQ_DAC0          (41)  /* Vector 41: Digital Analog Converter 0 */
-#  define KL_IRQ_TSI0          (42)  /* Vector 42: TSI0 */
-#  define KL_IRQ_MCG           (43)  /* Vector 43: MCG */
-#  define KL_IRQ_LPTIMER       (44)  /* Vector 44: Low Power Timer */
-                                     /* Vector 45: Reserved */
-#  define KL_IRQ_PORTA         (46)  /* Vector 46: GPIO Port A */
-#  define KL_IRQ_PORTD         (47)  /* Vector 47: GPIO Port D */
-
-/* Note that the total number of IRQ numbers supported is equal to the number of
- * valid interrupt vectors.  This is wasteful in that certain tables are sized by
- * this value.  There are only 94 valid interrupts so, potentially the numver of
- * IRQs to could be reduced to 94.  However, equating IRQ numbers with vector numbers
- * also simplifies operations on NVIC registers and (at least in my state of mind
- * now) seems to justify the waste.
- */
-
-#  define NR_VECTORS           (64) /* 64 vectors */
-#  define NR_IRQS              (48) /* 64 interrupts but 48 IRQ numbers */
-
-#else
-  /* The interrupt vectors for other parts are defined in other documents and may or
-   * may not be the same as above (the family members are all very similar)  This
-   * error just means that you have to look at the document and determine for yourself
-   * if the vectors are the same.
-   */
-
-#  error "No IRQ numbers for this Kinetis L part"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_KL_IRQ_H */
-

arch/arm/include/limits.h

@@ -1,86 +0,0 @@
-/****************************************************************************
- * arch/arm/include/limits.h
- *
- *   Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_LIMITS_H
-#define __ARCH_ARM_INCLUDE_LIMITS_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define CHAR_BIT    8
-#define SCHAR_MIN  (-SCHAR_MAX - 1)
-#define SCHAR_MAX   127
-#define UCHAR_MAX   255
-
-/* These could be different on machines where char is unsigned */
-
-#ifdef __CHAR_UNSIGNED__
-#define CHAR_MIN    0
-#define CHAR_MAX    UCHAR_MAX
-#else
-#define CHAR_MIN    SCHAR_MIN
-#define CHAR_MAX    SCHAR_MAX
-#endif
-
-#define SHRT_MIN    (-SHRT_MAX - 1)
-#define SHRT_MAX    32767
-#define USHRT_MAX   65535U
-
-#define INT_MIN     (-INT_MAX - 1)
-#define INT_MAX     2147483647
-#define UINT_MAX    4294967295U
-
-/* These change on 32-bit and 64-bit platforms */
-
-#define LONG_MIN    (-LONG_MAX - 1)
-#define LONG_MAX    2147483647L
-#define ULONG_MAX   4294967295UL
-
-#define LLONG_MIN   (-LLONG_MAX - 1)
-#define LLONG_MAX   9223372036854775807LL
-#define ULLONG_MAX  18446744073709551615ULL
-
-/* A pointer is 4 bytes */
-
-#define PTR_MIN     (-PTR_MAX - 1)
-#define PTR_MAX     2147483647
-#define UPTR_MAX    4294967295U
-
-#endif /* __ARCH_ARM_INCLUDE_LIMITS_H */

arch/arm/include/lpc11xx/chip.h

@@ -1,141 +0,0 @@
-/************************************************************************************
- * arch/arm/include/lpc11xx/chip.h
- *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
-#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Get customizations for each supported chip */
-
-#if defined(CONFIG_ARCH_CHIP_LPC1115)
-#  define LPC111x               1  /* LPC111x family */
-#  define LPC11_FLASH_SIZE      (64*1024) /* 64Kb */
-#  define LPC11_SRAM_SIZE       (8*1024)  /*  8Kb */
-#  define LPC11_CPUSRAM_SIZE    (8*1024)
-#  undef  LPC11_HAVE_BANK0         /* No AHB SRAM bank 0 */
-#  undef  LPC11_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC11_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC11_NUSBHOST        0  /* No USB host controller */
-#  define LPC11_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC11_NUSBDEV         1  /* One USB device controller */
-#  define LPC11_NCAN            1  /* One CAN controller */
-#  define LPC11_NI2S            0  /* No I2S modules */
-#  define LPC11_NDAC            0  /* No DAC module */
-#else
-#  error "Unsupported LPC11xx chip"
-#endif
-
-/* NVIC priority levels *************************************************************/
-/* Each priority field holds a priority value, 0-31. The lower the value, the greater
- * the priority of the corresponding interrupt. The processor implements only
- * bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
- */
-
-#define NVIC_SYSH_PRIORITY_MIN     0xf8 /* All bits[7:3] set is minimum priority */
-#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
-#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP    0x08 /* Five bits of interrupt priority used */
-
-/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
- * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
- * interrupts will not have execution priority.  SVCall must have execution
- * priority in all cases.
- *
- * In the normal cases, interrupts are not nest-able and all interrupts run
- * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
- * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
- *
- * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
- * high priority interrupts are supported.  These are not "nested" in the
- * normal sense of the word.  These high priority interrupts can interrupt
- * normal processing but execute outside of OS (although they can "get back
- * into the game" via a PendSV interrupt).
- *
- * In the normal course of things, interrupts must occasionally be disabled
- * using the irqsave() inline function to prevent contention in use of
- * resources that may be shared between interrupt level and non-interrupt
- * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
- * do we disable all interrupts (except SVCall), or do we only disable the
- * "normal" interrupts.  Since the high priority interrupts cannot interact
- * with the OS, you may want to permit the high priority interrupts even if
- * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
- * used to select either behavior:
- *
- *   ----------------------------+--------------+----------------------------
- *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
- *   ----------------------------+--------------+--------------+-------------
- *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
- *   ----------------------------+--------------+--------------+-------------
- *                               |              |              |    SVCall
- *                               |    SVCall    |    SVCall    |    HIGH
- *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
- *                               |              |    MAXNORMAL |
- *   ----------------------------+--------------+--------------+-------------
- */
-
-#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
-#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
-#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
-#else
-#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
-#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
-#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */

arch/arm/include/lpc11xx/irq.h

@@ -1,144 +0,0 @@
-/****************************************************************************
- * arch/arm/include/lpc11xxx/irq.h
- *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
-#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-#include <arch/lpc11xx/chip.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- */
-
-/* Common Processor Exceptions (vectors 0-15) */
-
-#define LPC11_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG) */
-                                        /* Vector  0: Reset stack pointer value */
-                                        /* Vector  1: Reset (not handler as an IRQ) */
-#define LPC11_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define LPC11_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
-                                        /* Vectors 4-10: Reserved */
-#define LPC11_IRQ_SVCALL        (11) /* Vector 11: SVC call */
-                                        /* Vector 12-13: Reserved */
-#define LPC11_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
-#define LPC11_IRQ_SYSTICK       (15) /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16) */
-
-#define LPC11_IRQ_EXTINT        (16) /* Vector number of the first external interrupt */
-
-#if defined(CONFIG_ARCH_CHIP_LPC1115)
-#define LPC11_IRQ_PIO0_0        (16) /* Vector 16: PIO0_0 */
-#define LPC11_IRQ_PIO0_1        (17) /* Vector 17: PIO0_1 */
-#define LPC11_IRQ_PIO0_2        (18) /* Vector 18: PIO0_2 */
-#define LPC11_IRQ_PIO0_3        (19) /* Vector 19: PIO0_3 */
-#define LPC11_IRQ_PIO0_4        (20) /* Vector 20: PIO0_4 */
-#define LPC11_IRQ_PIO0_5        (21) /* Vector 21: PIO0_5 */
-#define LPC11_IRQ_PIO0_6        (22) /* Vector 22: PIO0_6 */
-#define LPC11_IRQ_PIO0_7        (23) /* Vector 23: PIO0_7 */
-#define LPC11_IRQ_PIO0_8        (24) /* Vector 24: PIO0_8 */
-#define LPC11_IRQ_PIO0_9        (25) /* Vector 25: PIO0_9 */
-#define LPC11_IRQ_PIO0_10       (26) /* Vector 26: PIO0_10 */
-#define LPC11_IRQ_PIO0_11       (27) /* Vector 27: PIO0_11 */
-#define LPC11_IRQ_PIO1_0        (28) /* Vector 28: PIO1_0 */
-#define LPC11_IRQ_CCAN          (29) /* Vector 29: C_CAN controller for LPC11Cxx */
-#define LPC11_IRQ_SSP1          (30) /* Vector 30: SPI1/SSP1 */
-#define LPC11_IRQ_I2C           (31) /* Vector 31: I2C */
-#define LPC11_IRQ_CT16B0        (32) /* Vector 32: Clock/Timer0 16 bits */
-#define LPC11_IRQ_CT16B1        (33) /* Vector 33: Clock/Timer1 16 bits */
-#define LPC11_IRQ_CT32B0        (34) /* Vector 34: Clock/Timer0 32 bits */
-#define LPC11_IRQ_CT32B1        (35) /* Vector 35: Clock/Timer1 32 bits */
-#define LPC11_IRQ_SSP0          (36) /* Vector 36: SPI0/SSP0 */
-#define LPC11_IRQ_UART          (37) /* Vector 37: UART */
-                                     /* Vector 38: Reserved */
-                                     /* Vector 39: Reserved */
-#define LPC11_IRQ_ADC           (40) /* Vector 40: Analog/Digital Converter */
-#define LPC11_IRQ_WDT           (41) /* Vector 41: Watchdog timer */
-#define LPC11_IRQ_BOD           (42) /* Vector 42: Brownout Detection */
-                                     /* Vector 43: Reserved */
-#define LPC11_IRQ_PIO3          (44) /* Vector 44: PIO3 */
-#define LPC11_IRQ_PIO2          (45) /* Vector 45: PIO2 */
-#define LPC11_IRQ_PIO1          (46) /* Vector 46: PIO1 */
-#define LPC11_IRQ_PIO0          (47) /* Vector 47: PIO0 */
-#endif
-
-#define NR_VECTORS           (64) /* 64 vectors */
-#define NR_IRQS              (48) /* 64 interrupts but 48 IRQ numbers */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-typedef void (*vic_vector_t)(uint32_t *regs);
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */

arch/arm/include/lpc17xx/chip.h

@@ -1,437 +0,0 @@
-/************************************************************************************
- * arch/arm/include/lpc17xx/chip.h
- *
- *   Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *           with LPC178x support from Rommel Marcelo
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
-#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Get customizations for each supported chip */
-
-#if defined(CONFIG_ARCH_CHIP_LPC1751)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (32*1024) /* 32Kb */
-#  define LPC17_SRAM_SIZE       (8*1024)  /*  8Kb */
-#  define LPC17_CPUSRAM_SIZE    (8*1024)
-#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            1  /* One CAN controller */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1752)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (64*1024) /* 65Kb */
-#  define LPC17_SRAM_SIZE       (16*1024) /* 16Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            1  /* One CAN controller */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1754)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
-#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  define  LPC17_HAVE_BANK0     1  /* Have AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            1  /* One CAN controller */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1756)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  define LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1758)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1759)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1764)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
-#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1765)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1766)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1767)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         0  /* No USB device controller */
-#  define LPC17_NCAN            0  /* No CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
-#  define LPC176x               1  /* LPC175/6 family */
-#  undef  LPC178x                  /* Not LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1773)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
-#  define LPC17_SRAM_SIZE       (40*1024)  /*  40Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No Peripheral SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LPC17_NUSBHOST           /* No USB host controller */
-#  undef  LPC17_NUSBOTG            /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_HAVE_SPIFI      1  /* Have SPIFI interface */
-#  undef  LPC17_HAVE_LCD           /* No LCD controller */
-#  undef  LPC17_HAVE_QEI           /* No QEI interface */
-#  undef  LPC17_HAVE_SD            /* No SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1774)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
-#  define LPC17_SRAM_SIZE       (40*1024)  /*  40Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0*/
-#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LPC17_NUSBHOST           /* One USB host controller */
-#  undef  LPC17_NUSBOTG            /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  undef  LPC17_HAVE_LCD           /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1776)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (80*1024)  /*  80Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0  */
-#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  undef  LPC17_HAVE_LCD           /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1777)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (96*1024)  /*  96Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
-#  undef  LPC17_NETHCONTROLLERS    /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  undef  LPC17_HAVE_LCD           /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1778)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (96*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  undef  LPC17_HAVE_LCD           /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1785)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (80*1024)  /*  80Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
-#  undef  LPC17_NETHCONTROLLERS    /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  define LPC17_HAVE_LCD        1  /* One LCD controller */
-#  undef  LPC17_HAVE_QEI           /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1786)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (80*1024)  /*  80Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  define LPC17_HAVE_LCD        1  /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1787)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (96*1024)  /*  96Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
-#  undef  LPC17_NETHCONTROLLERS    /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  define LPC17_HAVE_LCD        1  /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#elif defined(CONFIG_ARCH_CHIP_LPC1788)
-#  undef  LPC176x                  /* Not LPC175/6 family */
-#  define LPC178x               1  /* LPC177/8 family */
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (96*1024)  /*  96Kb */
-#  define LPC17_CPUSRAM_SIZE    (64*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
-#  define LPC17_HAVE_LCD        1  /* One LCD controller */
-#  define LPC17_HAVE_QEI        1  /* One QEI interface */
-#  define LPC17_HAVE_SD         1  /* One SD controller */
-#else
-#  error "Unsupported LPC17xx chip"
-#endif
-
-/* NVIC priority levels *************************************************************/
-/* Each priority field holds a priority value, 0-31. The lower the value, the greater
- * the priority of the corresponding interrupt. The processor implements only
- * bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
- */
-
-#define NVIC_SYSH_PRIORITY_MIN     0xf8 /* All bits[7:3] set is minimum priority */
-#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
-#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP    0x08 /* Five bits of interrupt priority used */
-
-/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
- * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
- * interrupts will not have execution priority.  SVCall must have execution
- * priority in all cases.
- *
- * In the normal cases, interrupts are not nest-able and all interrupts run
- * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
- * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
- *
- * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
- * high priority interrupts are supported.  These are not "nested" in the
- * normal sense of the word.  These high priority interrupts can interrupt
- * normal processing but execute outside of OS (although they can "get back
- * into the game" via a PendSV interrupt).
- *
- * In the normal course of things, interrupts must occasionally be disabled
- * using the irqsave() inline function to prevent contention in use of
- * resources that may be shared between interrupt level and non-interrupt
- * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
- * do we disable all interrupts (except SVCall), or do we only disable the
- * "normal" interrupts.  Since the high priority interrupts cannot interact
- * with the OS, you may want to permit the high priority interrupts even if
- * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
- * used to select either behavior:
- *
- *   ----------------------------+--------------+----------------------------
- *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
- *   ----------------------------+--------------+--------------+-------------
- *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
- *   ----------------------------+--------------+--------------+-------------
- *                               |              |              |    SVCall
- *                               |    SVCall    |    SVCall    |    HIGH
- *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
- *                               |              |    MAXNORMAL |
- *   ----------------------------+--------------+--------------+-------------
- */
-
-#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
-#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
-#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
-#else
-#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
-#  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
-#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
-#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */

arch/arm/include/lpc17xx/irq.h

@@ -1,119 +0,0 @@
-/****************************************************************************
- * arch/arm/include/lpc17xxx/irq.h
- *
- *   Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
-#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-#include <arch/lpc17xx/chip.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- */
-
-/* Common Processor Exceptions (vectors 0-15) */
-
-#define LPC17_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG) */
-                                     /* Vector  0: Reset stack pointer value */
-                                     /* Vector  1: Reset (not handler as an IRQ) */
-#define LPC17_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define LPC17_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
-#define LPC17_IRQ_MEMFAULT       (4) /* Vector  4: Memory management (MPU) */
-#define LPC17_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
-#define LPC17_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
-#define LPC17_IRQ_SVCALL        (11) /* Vector 11: SVC call */
-#define LPC17_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
-                                     /* Vector 13: Reserved */
-#define LPC17_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
-#define LPC17_IRQ_SYSTICK       (15) /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16) */
-
-#define LPC17_IRQ_EXTINT        (16) /* Vector number of the first external interrupt */
-
-/* Family Specfic Interrupts */
-
-#if defined(LPC176x)                 /* LPC175/6 family */
-#  include <arch/lpc17xx/lpc176x_irq.h>
-#elif defined(LPC178x)               /* LPC177/8 family */
-#  include <arch/lpc17xx/lpc178x_irq.h>
-#else
-#  error "Unknown LPC17xx family"
-#endif
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-typedef void (*vic_vector_t)(uint32_t *regs);
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */

arch/arm/include/lpc17xx/lpc176x_irq.h

@@ -1,246 +0,0 @@
-/****************************************************************************
- * arch/lpc17xx/lpc176x_irq.h
- *
- *   Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather, only indirectly
- * through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
-#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- */
-
-/* External interrupts (vectors >= 16) */
-
-#define LPC17_IRQ_WDT           (LPC17_IRQ_EXTINT+0)  /* WDT Watchdog Interrupt (WDINT) */
-#define LPC17_IRQ_TMR0          (LPC17_IRQ_EXTINT+1)  /* Timer 0 Match 0 - 1 (MR0, MR1)
-                                                       * Capture 0 - 1 (CR0, CR1) */
-#define LPC17_IRQ_TMR1          (LPC17_IRQ_EXTINT+2)  /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
-                                                       * Capture 0 - 1 (CR0, CR1) */
-#define LPC17_IRQ_TMR2          (LPC17_IRQ_EXTINT+3)  /* Timer 2 Match 0-3
-                                                       * Capture 0-1 */
-#define LPC17_IRQ_TMR3          (LPC17_IRQ_EXTINT+4)  /* Timer 3 Match 0-3
-                                                       * Capture 0-1 */
-#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART 0 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART 1 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * Modem Control Change
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART2         (LPC17_IRQ_EXTINT+7)  /* UART 2 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART3         (LPC17_IRQ_EXTINT+8)  /* UART 3 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_PWM1          (LPC17_IRQ_EXTINT+9)  /* PWM1 Match 0 - 6 of PWM1
-                                                       * Capture 0-1 of PWM1 */
-#define LPC17_IRQ_I2C0          (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
-#define LPC17_IRQ_I2C1          (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
-#define LPC17_IRQ_I2C2          (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
-#define LPC17_IRQ_SPIF          (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
-                                                       * Mode Fault (MODF) */
-#define LPC17_IRQ_SSP0          (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
-                                                       * Rx FIFO half full of SSP0
-                                                       * Rx Timeout of SSP0
-                                                       * Rx Overrun of SSP0 */
-#define LPC17_IRQ_SSP1          (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
-                                                       * Rx FIFO half full
-                                                       * Rx Timeout
-                                                       * Rx Overrun */
-#define LPC17_IRQ_PLL0          (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
-#define LPC17_IRQ_RTC           (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
-                                                       * Alarm (RTCALF) */
-#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
-#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
-#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
-#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
-                                                       * Note: EINT3 channel is shared with GPIO interrupts */
-#define LPC17_IRQ_ADC           (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
-#define LPC17_IRQ_BOD           (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
-#define LPC17_IRQ_USB           (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
-                                                       * USB_INT_REQ_DMA */
-#define LPC17_IRQ_CAN           (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
-                                                       *                 CAN 1 Tx, CAN 1 Rx */
-#define LPC17_IRQ_GPDMA         (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
-                                                       *       IntStatus of DMA channel 1 */
-#define LPC17_IRQ_I2S           (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
-#define LPC17_IRQ_ETH           (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
-                                                       * TxFinishedInt, TxErrorInt,* TxUnderrunInt,
-                                                       * RxDoneInt, RxFinishedInt, RxErrorInt,
-                                                       * RxOverrunInt */
-#define LPC17_IRQ_RITINT        (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
-#define LPC17_IRQ_MCPWM         (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
-                                                       * ICAP[2:0], FES */
-#define LPC17_IRQ_QEI           (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
-                                                       * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
-                                                       * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
-                                                       * POS2REV_Int */
-#define LPC17_IRQ_PLL1          (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
-#define LPC17_IRQ_USBACT        (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
-#define LPC17_IRQ_CANACT        (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
-#define LPC17_IRQ_NEXTINT       (35)
-#define LPC17_IRQ_NIRQS         (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
-
-/* GPIO interrupts.  The LPC17xx supports several interrupts on ports 0 and
- * 2 (only).  We go through some special efforts to keep the number of IRQs
- * to a minimum in this sparse interrupt case.
- *
- * 28 interrupts on Port 0:  p0.0 - p0.11, p0.15-p0.30
- * 14 interrupts on Port 2:  p2.0 - p2.13
- * --
- * 42
- */
-
-#ifdef CONFIG_GPIO_IRQ
-#  define LPC17_VALID_GPIOINT0  (0x7fff8ffful) /* GPIO port 0 interrupt set */
-#  define LPC17_VALID_GPIOINT2  (0x00003ffful) /* GPIO port 2 interrupt set */
-
-   /* Set 1: 12 interrupts p0.0-p0.11 */
-
-#  define LPC17_VALID_GPIOINT0L (0x00000ffful)
-#  define LPC17_VALID_SHIFT0L   (0)
-#  define LPC17_VALID_FIRST0L   (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
-
-#  define LPC17_IRQ_P0p0        (LPC17_VALID_FIRST0L+0)
-#  define LPC17_IRQ_P0p1        (LPC17_VALID_FIRST0L+1)
-#  define LPC17_IRQ_P0p2        (LPC17_VALID_FIRST0L+2)
-#  define LPC17_IRQ_P0p3        (LPC17_VALID_FIRST0L+3)
-#  define LPC17_IRQ_P0p4        (LPC17_VALID_FIRST0L+4)
-#  define LPC17_IRQ_P0p5        (LPC17_VALID_FIRST0L+5)
-#  define LPC17_IRQ_P0p6        (LPC17_VALID_FIRST0L+6)
-#  define LPC17_IRQ_P0p7        (LPC17_VALID_FIRST0L+7)
-#  define LPC17_IRQ_P0p8        (LPC17_VALID_FIRST0L+8)
-#  define LPC17_IRQ_P0p9        (LPC17_VALID_FIRST0L+9)
-#  define LPC17_IRQ_P0p10       (LPC17_VALID_FIRST0L+10)
-#  define LPC17_IRQ_P0p11       (LPC17_VALID_FIRST0L+11)
-#  define LPC17_VALID_NIRQS0L   (12)
-
-   /* Set 2: 16 interrupts p0.15-p0.30 */
-
-#  define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
-#  define LPC17_VALID_SHIFT0H   (15)
-#  define LPC17_VALID_FIRST0H   (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
-
-#  define LPC17_IRQ_P0p15       (LPC17_VALID_FIRST0H+0)
-#  define LPC17_IRQ_P0p16       (LPC17_VALID_FIRST0H+1)
-#  define LPC17_IRQ_P0p17       (LPC17_VALID_FIRST0H+2)
-#  define LPC17_IRQ_P0p18       (LPC17_VALID_FIRST0H+3)
-#  define LPC17_IRQ_P0p19       (LPC17_VALID_FIRST0H+4)
-#  define LPC17_IRQ_P0p20       (LPC17_VALID_FIRST0H+5)
-#  define LPC17_IRQ_P0p21       (LPC17_VALID_FIRST0H+6)
-#  define LPC17_IRQ_P0p22       (LPC17_VALID_FIRST0H+7)
-#  define LPC17_IRQ_P0p23       (LPC17_VALID_FIRST0H+8)
-#  define LPC17_IRQ_P0p24       (LPC17_VALID_FIRST0H+9)
-#  define LPC17_IRQ_P0p25       (LPC17_VALID_FIRST0H+10)
-#  define LPC17_IRQ_P0p26       (LPC17_VALID_FIRST0H+11)
-#  define LPC17_IRQ_P0p27       (LPC17_VALID_FIRST0H+12)
-#  define LPC17_IRQ_P0p28       (LPC17_VALID_FIRST0H+13)
-#  define LPC17_IRQ_P0p29       (LPC17_VALID_FIRST0H+14)
-#  define LPC17_IRQ_P0p30       (LPC17_VALID_FIRST0H+15)
-#  define LPC17_VALID_NIRQS0H   (16)
-
-   /* Set 3: 14 interrupts p2.0-p2.13 */
-
-#  define LPC17_VALID_GPIOINT2  (0x00003ffful)
-#  define LPC17_VALID_SHIFT2    (0)
-#  define LPC17_VALID_FIRST2    (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
-
-#  define LPC17_IRQ_P2p0        (LPC17_VALID_FIRST2+0)
-#  define LPC17_IRQ_P2p1        (LPC17_VALID_FIRST2+1)
-#  define LPC17_IRQ_P2p2        (LPC17_VALID_FIRST2+2)
-#  define LPC17_IRQ_P2p3        (LPC17_VALID_FIRST2+3)
-#  define LPC17_IRQ_P2p4        (LPC17_VALID_FIRST2+4)
-#  define LPC17_IRQ_P2p5        (LPC17_VALID_FIRST2+5)
-#  define LPC17_IRQ_P2p6        (LPC17_VALID_FIRST2+6)
-#  define LPC17_IRQ_P2p7        (LPC17_VALID_FIRST2+7)
-#  define LPC17_IRQ_P2p8        (LPC17_VALID_FIRST2+8)
-#  define LPC17_IRQ_P2p9        (LPC17_VALID_FIRST2+9)
-#  define LPC17_IRQ_P2p10       (LPC17_VALID_FIRST2+10)
-#  define LPC17_IRQ_P2p11       (LPC17_VALID_FIRST2+11)
-#  define LPC17_IRQ_P2p12       (LPC17_VALID_FIRST2+12)
-#  define LPC17_IRQ_P2p13       (LPC17_VALID_FIRST2+13)
-#  define LPC17_VALID_NIRQS2    (14)
-#  define LPC17_NGPIOAIRQS      (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
-#else
-#  define LPC17_NGPIOAIRQS      (0)
-#endif
-
-/* Total number of IRQ numbers */
-
-#define NR_VECTORS              LPC17_IRQ_NIRQS
-#define NR_IRQS                 (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */
-

arch/arm/include/lpc17xx/lpc178x_irq.h

@@ -1,292 +0,0 @@
-/****************************************************************************
- * arch/arm/include/lpc17xxx/lpc178x_irq.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Authors: Rommel Marcelo
- *            Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
-#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map
- * directly to bits in the NVIC.  This does, however, waste several words of
- * memory in the IRQ to handle mapping tables.
- */
-
-/* External interrupts (vectors >= 16) */
-
-#define LPC17_IRQ_WDT           (LPC17_IRQ_EXTINT+0)  /* WDT Watchdog Interrupt (WDINT) */
-#define LPC17_IRQ_TMR0          (LPC17_IRQ_EXTINT+1)  /* Timer 0 Match 0 - 1 (MR0, MR1)
-                                                       * Capture 0 - 1 (CR0, CR1) */
-#define LPC17_IRQ_TMR1          (LPC17_IRQ_EXTINT+2)  /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
-                                                       * Capture 0 - 1 (CR0, CR1) */
-#define LPC17_IRQ_TMR2          (LPC17_IRQ_EXTINT+3)  /* Timer 2 Match 0-3
-                                                       * Capture 0-1 */
-#define LPC17_IRQ_TMR3          (LPC17_IRQ_EXTINT+4)  /* Timer 3 Match 0-3
-                                                       * Capture 0-1 */
-#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART 0 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART 1 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * Modem Control Change
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART2         (LPC17_IRQ_EXTINT+7)  /* UART 2 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART3         (LPC17_IRQ_EXTINT+8)  /* UART 3 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_PWM1          (LPC17_IRQ_EXTINT+9)  /* PWM1 Match 0 - 6 of PWM1
-                                                       * Capture 0-1 of PWM1 */
-#define LPC17_IRQ_I2C0          (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
-#define LPC17_IRQ_I2C1          (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
-#define LPC17_IRQ_I2C2          (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
-#define LPC17_IRQ_RESERVED29    (LPC17_IRQ_EXTINT+13) /* Unused  */
-#define LPC17_IRQ_SSP0          (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
-                                                       * Rx FIFO half full of SSP0
-                                                       * Rx Timeout of SSP0
-                                                       * Rx Overrun of SSP0 */
-#define LPC17_IRQ_SSP1          (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
-                                                       * Rx FIFO half full
-                                                       * Rx Timeout
-                                                       * Rx Overrun */
-#define LPC17_IRQ_PLL0          (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
-#define LPC17_IRQ_RTC           (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
-                                                       * Alarm (RTCALF) */
-#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
-#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
-#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
-#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
-                                                       * Note: EINT3 channel is shared with GPIO interrupts */
-#define LPC17_IRQ_ADC           (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
-#define LPC17_IRQ_BOD           (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
-#define LPC17_IRQ_USB           (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
-                                                       * USB_INT_REQ_DMA */
-#define LPC17_IRQ_CAN           (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
-                                                       *                 CAN 1 Tx, CAN 1 Rx */
-#define LPC17_IRQ_GPDMA         (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
-                                                       *       IntStatus of DMA channel 1 */
-#define LPC17_IRQ_I2S           (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
-#define LPC17_IRQ_ETH           (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
-                                                       * TxFinishedInt, TxErrorInt,* TxUnderrunInt,
-                                                       * RxDoneInt, RxFinishedInt, RxErrorInt,
-                                                       * RxOverrunInt */
-#define LPC17_IRQ_MCI           (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */
-#define LPC17_IRQ_MCPWM         (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
-                                                       * ICAP[2:0], FES */
-#define LPC17_IRQ_QEI           (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
-                                                       * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
-                                                       * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
-                                                       * POS2REV_Int */
-#define LPC17_IRQ_PLL1          (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
-#define LPC17_IRQ_USBACT        (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
-#define LPC17_IRQ_CANACT        (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
-#define LPC17_IRQ_UART4         (LPC17_IRQ_EXTINT+35)  /* UART 4 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_SSP2          (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
-                                                       * Rx FIFO half full of SSP2
-                                                       * Rx Timeout of SSP2
-                                                       * Rx Overrun of SSP2 */
-#define LPC17_IRQ_LCD           (LPC17_IRQ_EXTINT+37) /* LCD interrupt
-                                                       * BER, VCompI, LNBUI, FUFI, CrsrI */
-#define LPC17_IRQ_GPIO          (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt
-                                                       * P0xREI, P2xREI, P0xFEI, P2xFEI */
-#define LPC17_IRQ_PWM0          (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
-                                                       * Capture 0-1 of PWM0 */
-#define LPC17_IRQ_EEPROM        (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt
-                                                       * EE_PROG_DONE, EE_RW_DONE */
-#define LPC17_IRQ_NEXTINT       (40)
-#define LPC17_IRQ_NIRQS         (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
-
-/* GPIO interrupts.  The LPC177x_8x supports several interrupts on ports 0 and
- * 2 (only).  We go through some special efforts to keep the number of IRQs
- * to a minimum in this sparse interrupt case.
- *
- * 31 interrupts on Port 0:  p0.0 - p0.30
- * 31 interrupts on Port 2:  p2.0 - p2.30
- * --
- * 42
- */
-
-#ifdef CONFIG_GPIO_IRQ
-#  define LPC17_VALID_GPIOINT0  (0xfffffffful) /* GPIO port 0 interrupt set */
-#  define LPC17_VALID_GPIOINT2  (0xfffffffful) /* GPIO port 2 interrupt set */
-
-   /* Set 1: 16 interrupts p0.0-p0.15 */
-
-#  define LPC17_VALID_SHIFT0L   (0)
-#  define LPC17_VALID_FIRST0L   (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
-
-#  define LPC17_IRQ_P0p0        (LPC17_VALID_FIRST0L+0)
-#  define LPC17_IRQ_P0p1        (LPC17_VALID_FIRST0L+1)
-#  define LPC17_IRQ_P0p2        (LPC17_VALID_FIRST0L+2)
-#  define LPC17_IRQ_P0p3        (LPC17_VALID_FIRST0L+3)
-#  define LPC17_IRQ_P0p4        (LPC17_VALID_FIRST0L+4)
-#  define LPC17_IRQ_P0p5        (LPC17_VALID_FIRST0L+5)
-#  define LPC17_IRQ_P0p6        (LPC17_VALID_FIRST0L+6)
-#  define LPC17_IRQ_P0p7        (LPC17_VALID_FIRST0L+7)
-#  define LPC17_IRQ_P0p8        (LPC17_VALID_FIRST0L+8)
-#  define LPC17_IRQ_P0p9        (LPC17_VALID_FIRST0L+9)
-#  define LPC17_IRQ_P0p10       (LPC17_VALID_FIRST0L+10)
-#  define LPC17_IRQ_P0p11       (LPC17_VALID_FIRST0L+11)
-#  define LPC17_IRQ_P0p12       (LPC17_VALID_FIRST0L+12)
-#  define LPC17_IRQ_P0p13       (LPC17_VALID_FIRST0L+13)
-#  define LPC17_IRQ_P0p14       (LPC17_VALID_FIRST0L+14)
-#  define LPC17_IRQ_P0p15       (LPC17_VALID_FIRST0L+15)
-#  define LPC17_VALID_NIRQS0L   (16)
-
-   /* Set 2: 16 interrupts p0.16-p0.31 */
-
-#  define LPC17_VALID_SHIFT0H   (16)
-#  define LPC17_VALID_FIRST0H   (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
-
-#  define LPC17_IRQ_P0p16       (LPC17_VALID_FIRST0H+0)
-#  define LPC17_IRQ_P0p17       (LPC17_VALID_FIRST0H+1)
-#  define LPC17_IRQ_P0p18       (LPC17_VALID_FIRST0H+2)
-#  define LPC17_IRQ_P0p19       (LPC17_VALID_FIRST0H+3)
-#  define LPC17_IRQ_P0p20       (LPC17_VALID_FIRST0H+4)
-#  define LPC17_IRQ_P0p21       (LPC17_VALID_FIRST0H+5)
-#  define LPC17_IRQ_P0p22       (LPC17_VALID_FIRST0H+6)
-#  define LPC17_IRQ_P0p23       (LPC17_VALID_FIRST0H+7)
-#  define LPC17_IRQ_P0p24       (LPC17_VALID_FIRST0H+8)
-#  define LPC17_IRQ_P0p25       (LPC17_VALID_FIRST0H+9)
-#  define LPC17_IRQ_P0p26       (LPC17_VALID_FIRST0H+10)
-#  define LPC17_IRQ_P0p27       (LPC17_VALID_FIRST0H+11)
-#  define LPC17_IRQ_P0p28       (LPC17_VALID_FIRST0H+12)
-#  define LPC17_IRQ_P0p29       (LPC17_VALID_FIRST0H+13)
-#  define LPC17_IRQ_P0p30       (LPC17_VALID_FIRST0H+14)
-#  define LPC17_IRQ_P0p31       (LPC17_VALID_FIRST0H+15)
-#  define LPC17_VALID_NIRQS0H   (16)
-
-   /* Set 3: 16 interrupts p2.0-p2.15 */
-
-#  define LPC17_VALID_SHIFT2L   (0)
-#  define LPC17_VALID_FIRST2L   (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
-
-#  define LPC17_IRQ_P2p0        (LPC17_VALID_FIRST2L+0)
-#  define LPC17_IRQ_P2p1        (LPC17_VALID_FIRST2L+1)
-#  define LPC17_IRQ_P2p2        (LPC17_VALID_FIRST2L+2)
-#  define LPC17_IRQ_P2p3        (LPC17_VALID_FIRST2L+3)
-#  define LPC17_IRQ_P2p4        (LPC17_VALID_FIRST2L+4)
-#  define LPC17_IRQ_P2p5        (LPC17_VALID_FIRST2L+5)
-#  define LPC17_IRQ_P2p6        (LPC17_VALID_FIRST2L+6)
-#  define LPC17_IRQ_P2p7        (LPC17_VALID_FIRST2L+7)
-#  define LPC17_IRQ_P2p8        (LPC17_VALID_FIRST2L+8)
-#  define LPC17_IRQ_P2p9        (LPC17_VALID_FIRST2L+9)
-#  define LPC17_IRQ_P2p10       (LPC17_VALID_FIRST2L+10)
-#  define LPC17_IRQ_P2p11       (LPC17_VALID_FIRST2L+11)
-#  define LPC17_IRQ_P2p12       (LPC17_VALID_FIRST2L+12)
-#  define LPC17_IRQ_P2p13       (LPC17_VALID_FIRST2L+13)
-#  define LPC17_IRQ_P2p14       (LPC17_VALID_FIRST2L+14)
-#  define LPC17_IRQ_P2p15       (LPC17_VALID_FIRST2L+15)
-#  define LPC17_VALID_NIRQS2L   (16)
-
-   /* Set 4: 16 interrupts p2.16 - p2.31 */
-
-#  define LPC17_VALID_SHIFT2H   (16)
-#  define LPC17_VALID_FIRST2H   (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L)
-
-#  define LPC17_IRQ_P2p16       (LPC17_VALID_FIRST2H+0)
-#  define LPC17_IRQ_P2p17       (LPC17_VALID_FIRST2H+1)
-#  define LPC17_IRQ_P2p18       (LPC17_VALID_FIRST2H+2)
-#  define LPC17_IRQ_P2p19       (LPC17_VALID_FIRST2H+3)
-#  define LPC17_IRQ_P2p20       (LPC17_VALID_FIRST2H+4)
-#  define LPC17_IRQ_P2p21       (LPC17_VALID_FIRST2H+5)
-#  define LPC17_IRQ_P2p22       (LPC17_VALID_FIRST2H+6)
-#  define LPC17_IRQ_P2p23       (LPC17_VALID_FIRST2H+7)
-#  define LPC17_IRQ_P2p24       (LPC17_VALID_FIRST2H+8)
-#  define LPC17_IRQ_P2p25       (LPC17_VALID_FIRST2H+9)
-#  define LPC17_IRQ_P2p26       (LPC17_VALID_FIRST2H+10)
-#  define LPC17_IRQ_P2p27       (LPC17_VALID_FIRST2H+11)
-#  define LPC17_IRQ_P2p28       (LPC17_VALID_FIRST2H+12)
-#  define LPC17_IRQ_P2p29       (LPC17_VALID_FIRST2H+13)
-#  define LPC17_IRQ_P2p30       (LPC17_VALID_FIRST2H+14)
-#  define LPC17_IRQ_P2p31       (LPC17_VALID_FIRST2H+15)
-#  define LPC17_VALID_NIRQS2H   (16)
-
-#  define LPC17_NGPIOAIRQS      (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H)
-#else
-#  define LPC17_NGPIOAIRQS      (0)
-#endif
-
-/* Total number of IRQ numbers */
-
-#define NR_VECTORS              LPC17_IRQ_NIRQS
-#define NR_IRQS                 (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */
-

arch/arm/include/lpc214x/irq.h

@@ -1,131 +0,0 @@
-/****************************************************************************
- * arch/lpc214x/irq.h
- *
- *   Copyright (C) 2007, 2008, 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
-#ifndef __ARCH_LPC214X_IRQ_H
-#define __ARCH_LPC214X_IRQ_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#  include <stdint.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* LPC214X Interrupts */
-
-#define LPC214X_WDT_IRQ        0 /* Watchdog */
-#define LPC214X_RESERVED_IRQ   1 /* SWI only */
-#define LPC214X_DBGCOMMRX_IRQ  2 /* Embedded debug */
-#define LPC214X_DBGCOMMTX_IRQ  3 /* Embedded debug */
-#define LPC214X_TIMER0_IRQ     4 /* Timer 0 */
-#define LPC214X_TIMER1_IRQ     5 /* Timer 1 */
-#define LPC214X_UART0_IRQ      6 /* UART 0 */
-#define LPC214X_UART1_IRQ      7 /* UART 1 */
-#define LPC214X_PWM0_IRQ       8 /* PWM 0 */
-#define LPC214X_I2C0_IRQ       9 /* I2C 0 */
-#define LPC214X_SPI0_IRQ      10 /* SPI 0 */
-#define LPC214X_SPI1_IRQ      11 /* SPI 1 */
-#define LPC214X_PLL_IRQ       12 /* PLL Lock IRQ */
-#define LPC214X_RTC_IRQ       13 /* Real Time Clock */
-#define LPC214X_EINT0_IRQ     14 /* External interrupt 0 */
-#define LPC214X_EINT1_IRQ     15 /* External interrupt 1 */
-#define LPC214X_EINT2_IRQ     16 /* External interrupt 2 */
-#define LPC214X_EINT3_IRQ     17 /* External interrupt 3 */
-#define LPC214X_ADC0_IRQ      18 /* ADC 0 */
-#define LPC214X_I2C1_IRQ      19 /* I2C 1 */
-#define LPC214X_BOD_IRQ       20 /* Brown Out Detect */
-#define LPC214X_ADC1_IRQ      21 /* ADC 1 */
-#define LPC214X_USB_IRQ       22 /* USB */
-
-#define LPC214X_IRQ_SYSTIMER  LPC214X_TIMER0_IRQ
-#define NR_IRQS               23
-
-/* There are 16 vectored interrupts.  If vectored interrupts are enabled, the
- * following will be used by the system.
- */
-
-#define LPC214X_SYSTIMER_VEC  0 /* System timer */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-typedef void (*vic_vector_t)(uint32_t *regs);
-#endif
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#ifndef CONFIG_VECTORED_INTERRUPTS
-void up_attach_vector(int irq, int vector, vic_vector_t handler);
-void up_detach_vector(int vector);
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_LPC214X_IRQ_H */
-