From e8134a8b578b9cecf4c40cc9ff1c72462c0c08af Mon Sep 17 00:00:00 2001 From: Abdelatif Guettouche Date: Thu, 7 Apr 2022 20:34:55 +0200 Subject: [PATCH] riscv/riscv_exception_common.S: Allow chips to define the exception section. Signed-off-by: Abdelatif Guettouche --- arch/risc-v/src/common/riscv_exception_common.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S index 4b4a5c57f57..d30c3f5adb0 100644 --- a/arch/risc-v/src/common/riscv_exception_common.S +++ b/arch/risc-v/src/common/riscv_exception_common.S @@ -49,6 +49,12 @@ # endif #endif +/* Provide a default section for the exeception handler. */ + +#ifndef EXCEPTION_SECTION +# define EXCEPTION_SECTION .text +#endif + /**************************************************************************** * Public Symbols ****************************************************************************/ @@ -62,7 +68,7 @@ * ****************************************************************************/ - .section .text + .section EXCEPTION_SECTION .global exception_common .align 8