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Squashed commit of the following:

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Finishes peripheral clock initialization:

      arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c
      arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c
        Provide MCU-specific mapping of clock names to PCC control registers.

      boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
        Provides initial clocking for for the S32K118EVB

    arch/arm/src/s32k1xx/s32k1xx_periphclocks.c:  Add logic to initialize peripheral clocking.

    arch/arm/src/s32k1xx/s32k1xx_clockconfig.c:  Add SIM clock configuration.
This commit is contained in:
Gregory Nutt
2019-08-17 11:50:32 -06:00
parent 1f021add53
commit e7a3231d7a
16 changed files with 1061 additions and 110 deletions
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boards/arm/s32k1xx/s32k118evb/src/Makefile
+3 -2
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@@ -35,8 +35,9 @@
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = s32k118_boot.c s32k118_bringup.c s32k118_clockconfig.c
ASRCS =
CSRCS = s32k118_boot.c s32k118_bringup.c s32k118_clockconfig.c
CSRCS += s32k118_periphclocks.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += s32k118_autoleds.c
boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
+3 -13
View File
@@ -65,22 +65,10 @@
#include "s32k1xx_start.h"
#include "s32k118evb.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Count of peripheral clock user configurations */
#define NUM_OF_PERIPHERAL_CLOCKS_0 10U
/****************************************************************************
* Public Data
****************************************************************************/
/* User peripheral configuration structure 0 */
extern struct peripheral_clock_config_s g_peripheral_clockconfig0[];
/* Each S32K1xx board must provide the following initialized structure. This is
* needed to establish the initial board clocking.
*/
@@ -190,15 +178,17 @@ const struct clock_configuration_s g_initial_clkconfig =
.traceclk = /* Debug trace Clock Configuration. */
{
.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
.divider = 0, /* TRACEDIV */
.divider = 1, /* TRACEDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = true, /* TRACEDIVEN */
.fraction = false, /* TRACEFRAC */
},
#ifdef CONFIG_S32K1XX_HAVE_QSPI
.qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
{
.refclk = false, /* Qspi reference clock gating */
},
#endif
},
.pcc =
{
boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
+152
View File
@@ -0,0 +1,152 @@
/****************************************************************************
* boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclks.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Most of the settings within this file derives from NXP sample code for
* the S32K118 MCUs. That sample code has this licensing information:
*
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "s32k1xx_periphclocks.h"
#include "s32k118evb.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* Each S32K1xx board must provide the following initialized structure. This is
* needed to establish the initial peripheral clocking.
*/
const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
{
{
.clkname = ADC0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = DMAMUX0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = LPTMR0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = LPUART0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = LPUART1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PORTA_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PORTB_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PORTC_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PORTD_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PORTE_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
};
boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
+11
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@@ -42,8 +42,11 @@
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
#include "s32k1xx_periphclocks.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -64,6 +67,10 @@
/* SPI chip selects */
/* Count of peripheral clock user configurations */
#define NUM_OF_PERIPHERAL_CLOCKS_0 10U
/****************************************************************************
* Public Types
****************************************************************************/
@@ -74,6 +81,10 @@
#ifndef __ASSEMBLY__
/* User peripheral configuration structure 0 */
extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
/****************************************************************************
* Public Functions
****************************************************************************/