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Add beginning of Nokia6100 driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3162 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2010-12-05 16:16:50 +00:00
parent a6958d7942
commit e67b0093be
6 changed files with 1135 additions and 4 deletions
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drivers/lcd/Make.defs
+6 -2
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@@ -33,11 +33,15 @@
#
############################################################################
LCD_ASRCS =
LCD_ASRCS =
LCD_CSRCS =
ifeq ($(CONFIG_NX_LCDDRIVER),y)
ifeq ($(CONFIG_LCD_P14201),y)
LCD_CSRCS = p14201.c
else
LCD_CSRCS =
ifeq ($(CONFIG_LCD_NOKIA6100),y)
LCD_CSRCS = nokia6100.c
else
endif
drivers/lcd/nokia6100.c
Executable
+997
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File diff suppressed because it is too large Load Diff
drivers/lcd/pcf8833.h
+8
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@@ -107,6 +107,14 @@
#define PCF8833_ECM 0xf0 /* Enter Calibration mode; Data: (1) Calibration control settings */
#define PCF8833_OTPSHTIN 0xf1 /* Shift data in OTP shift registers; Data: Any number of bytes */
/* Memory data access control (MADCTL) bit definitions */
#define MADCTL_RGB (1 << 3) /* Bit 3: BGR */
#define MADCTL_LAO (1 << 4) /* Bit 4: Line address order bottom to top */
#define MADCTL_V (1 << 5) /* Bit 5: Vertical RAM write; in Y direction */
#define MADCTL_MX (1 << 6) /* Bit 6: Mirror X */
#define MADCTL_MY (1 << 7) /* Bit 7: Mirror Y */
/* PCF8833 status register bit definitions */
/* CMD format: RDDST command followed by four status bytes: */
/* Byte 1: D31 d30 D29 D28 D27 D26 --- --- */
drivers/lcd/s1d15g10.h
+35
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@@ -85,6 +85,41 @@
#define S1D15G10_NOP 0x25 /* NOP intruction (0x45?); Data: none */
#define S1D15G10_STREAD 0x20 /* Status read; Data: none */
/* Display control (DISCTL) bit definitions */
#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */
#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT)
# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT)
# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT)
# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT)
# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT)
#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */
#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT)
# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT)
# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT)
# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT)
# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT)
/* Power control (PWRCTR) bit definitions */
#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */
#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */
#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */
#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */
#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */
/* Data control (DATCTL) bit definitions */
#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */
#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */
#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */
#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */
#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */
#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */
#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */
/* Status register bit definions (after reset or NOP) */
#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */