diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h
index 4bc10ab8931..921aa4c3fcf 100644
--- a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h
@@ -52,7 +52,7 @@
 #if defined(CONFIG_STM32L4_STM32F40XX)
 #  define STM32L4_SPI_CLK_MAX     37500000UL
 #else
-#  define STM32L4_SPI_CLK_MAX     18000000UL
+#  define STM32L4_SPI_CLK_MAX     40000000UL
 #endif
 
 /* Register Offsets *****************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c
index dc73a52f0bd..79cf4dc62e2 100644
--- a/arch/arm/src/stm32l4/stm32l4_lptim.c
+++ b/arch/arm/src/stm32l4/stm32l4_lptim.c
@@ -130,7 +130,7 @@ static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops =
   .setchannel = &stm32l4_lptim_setchannel,
 };
 
-#if CONFIG_STM32L4_LPTIM1
+#if defined(CONFIG_STM32L4_LPTIM1)
 static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv =
 {
   .ops        = &stm32l4_lptim_ops,
@@ -140,7 +140,7 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv =
 };
 #endif
 
-#if CONFIG_STM32L4_LPTIM2
+#if defined(CONFIG_STM32L4_LPTIM2)
 static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv =
 {
   .ops        = &stm32l4_lptim_ops,
@@ -162,11 +162,11 @@ static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer)
 {
   switch (timer)
     {
-#if CONFIG_STM32L4_LPTIM1
+#if defined(CONFIG_STM32L4_LPTIM1)
       case 1:
         return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv;
 #endif
-#if CONFIG_STM32L4_LPTIM2
+#if defined(CONFIG_STM32L4_LPTIM2)
       case 2:
         return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv;
 #endif
@@ -196,12 +196,12 @@ static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev)
 
   switch (((struct stm32l4_lptim_priv_s *)dev)->base)
     {
-#if CONFIG_STM32L4_LPTIM1
+#if defined(CONFIG_STM32L4_LPTIM1)
       case STM32L4_LPTIM1_BASE:
         modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN);
         break;
 #endif
-#if CONFIG_STM32L4_LPTIM2
+#if defined(CONFIG_STM32L4_LPTIM2)
       case STM32L4_LPTIM2_BASE:
         modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN);
         break;
@@ -224,12 +224,12 @@ static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev)
 
   switch (((struct stm32l4_lptim_priv_s *)dev)->base)
     {
-#if CONFIG_STM32L4_LPTIM1
+#if defined(CONFIG_STM32L4_LPTIM1)
       case STM32L4_LPTIM1_BASE:
         modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0);
         break;
 #endif
-#if CONFIG_STM32L4_LPTIM2
+#if defined(CONFIG_STM32L4_LPTIM2)
       case STM32L4_LPTIM2_BASE:
         modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0);
         break;
@@ -252,13 +252,13 @@ static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev)
 
   switch (((struct stm32l4_lptim_priv_s *)dev)->base)
     {
-#if CONFIG_STM32L4_LPTIM1
+#if defined(CONFIG_STM32L4_LPTIM1)
       case STM32L4_LPTIM1_BASE:
         modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST);
         modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0);
         break;
 #endif
-#if CONFIG_STM32L4_LPTIM2
+#if defined(CONFIG_STM32L4_LPTIM2)
       case STM32L4_LPTIM2_BASE:
         modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST);
         modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0);
@@ -283,7 +283,7 @@ static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev,
 
   switch (((struct stm32l4_lptim_priv_s *)dev)->base)
     {
-#if CONFIG_STM32L4_LPTIM1
+#if defined(CONFIG_STM32L4_LPTIM1)
       case STM32L4_LPTIM1_BASE:
         switch (channel)
           {
@@ -308,7 +308,7 @@ static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev,
         break;
 #endif /* CONFIG_STM32L4_LPTIM1 */
 
-#if CONFIG_STM32L4_LPTIM2
+#if defined(CONFIG_STM32L4_LPTIM2)
       case STM32L4_LPTIM2_BASE:
         switch (channel)
           {