diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c
index 97b75f75d5d..35c0bc65b91 100644
--- a/arch/arm/src/efm32/efm32_usbhost.c
+++ b/arch/arm/src/efm32/efm32_usbhost.c
@@ -1171,7 +1171,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
   /* Loop, testing for an end of transfer condition.  The channel 'result'
    * was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
    * will be set to false and 'result' will be set appropriately when the
-   * tranfer is completed.
+   * transfer is completed.
    */
 
   do
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h
index 0136ac105f8..4e1e499eb1c 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h
@@ -60,7 +60,7 @@ typedef FAR void *DMA_HANDLE;
  * function is called at the completion of the DMA transfer.  'arg' is the
  * same 'arg' value that was provided when lpc17_dmastart() was called and
  * result indicates the result of the transfer:  Zero indicates a successful
- * tranfers.  On failure, a negated errno is returned indicating the general
+ * transfers.  On failure, a negated errno is returned indicating the general
  * nature of the DMA faiure.
  */
 
diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c
index 876584ba337..1ab475edc07 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -2457,7 +2457,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy,
   dmadesc->size = (uint32_t)packet;
 #endif
 
-  /* Enable DMA tranfer for this endpoint */
+  /* Enable DMA transfer for this endpoint */
 
   putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN);
 
diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c
index f1d21bab434..a1427d883e5 100644
--- a/arch/arm/src/lpc214x/lpc214x_usbdev.c
+++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c
@@ -2422,7 +2422,7 @@ static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy,
   dmadesc->size = (uint32_t)packet;
 #endif
 
-  /* Enable DMA tranfer for this endpoint */
+  /* Enable DMA transfer for this endpoint */
 
   putreq32(1 << epphy, LPC214X_USBDEV_EPDMAEN);
 
diff --git a/arch/arm/src/nuc1xx/chip/nuc_gcr.h b/arch/arm/src/nuc1xx/chip/nuc_gcr.h
index c9ad2df98ad..065c3defbb2 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_gcr.h
+++ b/arch/arm/src/nuc1xx/chip/nuc_gcr.h
@@ -356,7 +356,7 @@
 #  define GCR_REGWRPROT_2        (0x16)
 #  define GCR_REGWRPROT_3        (0x88)
                                            /* Read: */
-#define GCR_REGWRPROT_DIS        (1 << 0)  /* Bit 0: Register write protectino disable index */
+#define GCR_REGWRPROT_DIS        (1 << 0)  /* Bit 0: Register write protection disable index */
 
 /********************************************************************************************
  * Public Types
diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c
index 63b46ada61d..d9f31eb52db 100644
--- a/arch/arm/src/sam34/sam_dmac.c
+++ b/arch/arm/src/sam34/sam_dmac.c
@@ -1225,7 +1225,7 @@ static inline int sam_multiple(struct sam_dma_s *dmach)
    * Additionally, the CTRLA DONE bit is asserted when the buffer transfer has completed.
    *
    * The DMAC transfer continues until the CTRLB register disables the descriptor
-   * (DSCR bits) registers at the final buffer tranfer.
+   * (DSCR bits) registers at the final buffer transfer.
    *
    * Enable error, buffer complete and transfer complete interrupts.  We
    * don't really need the buffer complete interrupts, but we will take them
diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c
index f248d58937c..300c4e11f4f 100644
--- a/arch/arm/src/sama5/sam_dmac.c
+++ b/arch/arm/src/sama5/sam_dmac.c
@@ -1721,7 +1721,7 @@ static inline int sam_multiple(struct sam_dmach_s *dmach)
    * buffer transfer has completed.
    *
    * The DMAC transfer continues until the CTRLB register disables the
-   * descriptor (DSCR bits) registers at the final buffer tranfer.
+   * descriptor (DSCR bits) registers at the final buffer transfer.
    *
    * Enable error, buffer complete and transfer complete interrupts.  We
    * don't really need the buffer complete interrupts, but we will take them
@@ -2309,7 +2309,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
       dmach->callback = callback;
       dmach->arg      = arg;
 
-      /* Is this a single block transfer?  Or a multiple block tranfer? */
+      /* Is this a single block transfer?  Or a multiple block transfer? */
 
       if (dmach->llhead == dmach->lltail)
         {
diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c
index 7d4d700cd97..dbc7c6ce1c8 100644
--- a/arch/arm/src/sama5/sam_udphs.c
+++ b/arch/arm/src/sama5/sam_udphs.c
@@ -1280,7 +1280,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
  *     When a request is queued, the request 'len' is the number of bytes
  *     to transfer and 'xfrd' and 'inflight' must be zero.
  *
- *     When this function starts a tranfer it will update the request
+ *     When this function starts a transfer it will update the request
  *     'inflight' field to indicate the size of the transfer.
  *
  *     When the transfer completes, the the 'inflight' field must hold the
@@ -1547,7 +1547,7 @@ static void sam_req_rddisable(uint8_t epno)
  *   - When receiving data via DMA, then data has already been transferred
  *     and this function is called on the terminating event.  The transfer
  *     is complete and we just need to check for end of request events and
- *     if we need to setup the tranfer for the next request.
+ *     if we need to setup the transfer for the next request.
  *   - When receiving via the FIFO, the transfer is not complete.  The
  *     data is in the FIFO and must be transferred from the FIFO to the
  *     request buffer.  No setup is needed for the next transfer other than
diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c
index ba3af1b2675..2936dec8d95 100644
--- a/arch/arm/src/sama5/sam_xdmac.c
+++ b/arch/arm/src/sama5/sam_xdmac.c
@@ -2355,7 +2355,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
       xdmach->callback = callback;
       xdmach->arg      = arg;
 
-      /* Is this a single block transfer?  Or a multiple block tranfer? */
+      /* Is this a single block transfer?  Or a multiple block transfer? */
 
       if (xdmach->llhead == xdmach->lltail)
         {
diff --git a/arch/arm/src/samdl/chip/saml_eic.h b/arch/arm/src/samdl/chip/saml_eic.h
index fca13fe45fc..e6bb167e2eb 100644
--- a/arch/arm/src/samdl/chip/saml_eic.h
+++ b/arch/arm/src/samdl/chip/saml_eic.h
@@ -106,7 +106,7 @@
 #  define EIC_NVMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
 #  define EIC_NVMICTRL_NMISENSE_LOW  (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
 #define EIC_NVMICTRL_NMIFLTEN        (1 << 3)  /* Bit 3: Non-maskable interrupt filter enable */
-#define EIC_NVMICTRL_ASYNC           (1 << 4)  /* Bit 4: Asynchronous edge detectino mode */
+#define EIC_NVMICTRL_ASYNC           (1 << 4)  /* Bit 4: Asynchronous edge detection mode */
 
 /* Non-maskable interrupt flas status and clear register */
 
diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c
index d435793d48d..44453b93a92 100644
--- a/arch/arm/src/samv7/sam_emac.c
+++ b/arch/arm/src/samv7/sam_emac.c
@@ -2103,7 +2103,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
  *
  * Parameters:
  *   priv - Reference to the driver state structure
- *   quid - Index of the tranfer queue that generated the interrupt
+ *   quid - Index of the transfer queue that generated the interrupt
  *
  * Returned Value:
  *   None
@@ -2230,7 +2230,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
  *
  * Parameters:
  *   priv - Reference to the driver state structure
- *   quid - Index of the tranfer queue that generated the interrupt
+ *   quid - Index of the transfer queue that generated the interrupt
  *
  * Returned Value:
  *   None
diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c
index 8ce280a2a2d..91ddd06918e 100644
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@@ -571,14 +571,14 @@ static const struct usb_epdesc_s g_ep0desc =
 
 #ifdef CONFIG_SAMV7_USBDEVHS_SCATTERGATHER
 #ifdef CONFIG_SAMV7_USBDEVHS_PREALLOCATE
-/* This is a properly aligned pool of preallocated DMA transfer desciptors */
+/* This is a properly aligned pool of preallocated DMA transfer descriptors */
 
 static struct sam_dtd_s g_dtdpool[CONFIG_SAMV7_USBDEVHS_NDTDS]
                         __attribute__ ((aligned(16)));
 #endif
 #endif
 
-/* Device error strings that may be enabled for more desciptive USB trace
+/* Device error strings that may be enabled for more descriptive USB trace
  * output.
  */
 
@@ -619,7 +619,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
 };
 #endif
 
-/* Interrupt event strings that may be enabled for more desciptive USB trace
+/* Interrupt event strings that may be enabled for more descriptive USB trace
  * output.
  */
 
@@ -1287,7 +1287,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
  *     When a request is queued, the request 'len' is the number of bytes
  *     to transfer and 'xfrd' and 'inflight' must be zero.
  *
- *     When this function starts a tranfer it will update the request
+ *     When this function starts a transfer it will update the request
  *     'inflight' field to indicate the size of the transfer.
  *
  *     When the transfer completes, the the 'inflight' field must hold the
@@ -1544,7 +1544,7 @@ static void sam_req_rddisable(uint8_t epno)
  *   - When receiving data via DMA, then data has already been transferred
  *     and this function is called on the terminating event.  The transfer
  *     is complete and we just need to check for end of request events and
- *     if we need to setup the tranfer for the next request.
+ *     if we need to setup the transfer for the next request.
  *   - When receiving via the FIFO, the transfer is not complete.  The
  *     data is in the FIFO and must be transferred from the FIFO to the
  *     request buffer.  No setup is needed for the next transfer other than
diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c
index 56e09db17a5..d717ce2eb01 100644
--- a/arch/arm/src/stm32/stm32_otgfshost.c
+++ b/arch/arm/src/stm32/stm32_otgfshost.c
@@ -1093,7 +1093,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
   /* Loop, testing for an end of transfer condition.  The channel 'result'
    * was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
    * will be set to false and 'result' will be set appropriately when the
-   * tranfer is completed.
+   * transfer is completed.
    */
 
   do
diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c
index 9e9cc0e9786..3d7340ca904 100644
--- a/arch/arm/src/stm32/stm32_otghshost.c
+++ b/arch/arm/src/stm32/stm32_otghshost.c
@@ -1093,7 +1093,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
   /* Loop, testing for an end of transfer condition.  The channel 'result'
    * was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
    * will be set to false and 'result' will be set appropriately when the
-   * tranfer is completed.
+   * transfer is completed.
    */
 
   do
diff --git a/arch/avr/src/at32uc3/at32uc3_ssc.h b/arch/avr/src/at32uc3/at32uc3_ssc.h
index 35b286b6aed..e5c1df3c624 100644
--- a/arch/avr/src/at32uc3/at32uc3_ssc.h
+++ b/arch/avr/src/at32uc3/at32uc3_ssc.h
@@ -114,7 +114,7 @@
 #define SSC_RCMR_CKI              (1 << 5)  /* Bit 5:  Receive Clock Inversion */
 #define SSC_RCMR_CKG_SHIFT        (6)       /* Bits 6-7: Receive Clock Gating Selection */
 #define SSC_RCMR_CKG_MASK         (3 << SSC_RCMR_CKG_SHIFT)
-#  define SSC_RCMR_CKG_NONE       (0 << SSC_RCMR_CKG_SHIFT) /* None, continous clock */
+#  define SSC_RCMR_CKG_NONE       (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */
 #  define SSC_RCMR_CKG_LOW        (1 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC low */
 #  define SSC_RCMR_CKG_HIGH       (2 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC high */
 #define SSC_RCMR_START_SHIFT      (8)       /* Bits 8-11: Receive Start Selection */
@@ -171,7 +171,7 @@
 #define SSC_TCMR_CKI              (1 << 5)  /* Bit 5:  Transmit Clock Inversion */
 #define SSC_TCMR_CKG_SHIFT        (6)      /* Bits 6-7: Transmit Clock Gating Selection */
 #define SSC_TCMR_CKG_MASK         (3 << SSC_TCMR_CKG_SHIFT)
-#  define SSC_TCMR_CKG_NONE       (0 << SSC_TCMR_CKG_SHIFT) /* None, continous clock */
+#  define SSC_TCMR_CKG_NONE       (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */
 #  define SSC_TCMR_CKG_LOW        (1 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC low */
 #  define SSC_TCMR_CKG_HIGH       (2 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC high */
 #define SSC_TCMR_START_SHIFT      (8)      /* Bits 8-11: Transmit Start Selection */
diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c
index c9d6c0e9d36..cc05aef6e91 100644
--- a/arch/mips/src/pic32mx/pic32mx-usbdev.c
+++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c
@@ -2876,7 +2876,7 @@ static int pic32mx_interrupt(int irq, void *context)
 
               usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_TRNCS), regval);
 
-              /* Handle the endpoint tranfer complete event. */
+              /* Handle the endpoint transfer complete event. */
 
               epno = (regval & USB_STAT_ENDPT_MASK) >> USB_STAT_ENDPT_SHIFT;
               if (epno == 0)