diff --git a/ChangeLog b/ChangeLog
index 64ab65b92cb..a8f56d1e8e2 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -10536,8 +10536,7 @@
nuttx/libc/mqueue to nuttx/sched/mqueue. Also add syscall support
for mq_setattr() and mq_getattr(). This is necessary in protected and
kernel builds because in those cases the message queue structure is
- protected and cannot be accessed directly from user mode code. Noted
- by Jouko Holopainen (2015-06-03).
+ protected and cannot be accessed directly from user mode code (2015-06-03).
* drivers/net/tun.c: TUN driver bug fix. From Max Neklyudov (2015-06-03.
* drivers/net/Kconfig, include/nuttx/net/mii.h, and
arch/arm/src/lpc17xx/lpc17_ethernet.c: Add support for the Micrel
@@ -12392,5 +12391,284 @@
banks. This fixes a race condition where the HW fills a FIFO bank
while the SW is busy, resulting in out of sequence USB packets
(2016-07-23).
+ * Freedom-K64F: Add PWM support. From Jordan MacIntyre (2016-07-25).
7.18 2016-xx-xx Gregory Nutt
+
+ * drivers/serial/pty.c, serial.c, usbdev/cdcacm.c, include/nuttx/fs/ioctl.h:
+ Fix FIONWRITE and add FIONSPACE. All implementations of FIONWRITE
+ were wrong. FIONWRITE should return the number of bytes waiting in
+ the outgoing send queue, not the free space. Rather, FIONSPACE should
+ return the free space in the send queue (2016-07-25).
+ * lib_dumpbuffer: Now prints a large on-stack buffer first to avoid
+ problems when the syslog output is prefixed with time. From Pierre-
+ noel Bouteville (2016-07-27).
+ * sched/clock and sched/sched: Add standard adjtime() interface and
+ basic timekeeping support. Normally used with an NTP client to keep
+ system time in synchronizationi. From Max Neklyudov (Merged on
+ 20160-07-28).
+ * arch/arm/src/stm32: Add timekeeping support for the STM32 tickless
+ mode. From Max Neklyudov (Merged on 20160-07-28).
+ * Top-Level Makefiles. Fix a chicken-and-egg problem. In the menuconfig
+ target, the context dependency was executed before kconfig-mconf.
+ That was necessary because the link at apps/platform/board needed to
+ be set up before creating the apps/Kconfig file. Otherwise, the
+ platform Kconfig files would not be included. But this introduces
+ the chicken-and-egg problem in some configurations.
+ In particular: (1) An NX graphics configuration is used that requires
+ auto-generation of source files using cpp, (2) the configuration is
+ set for Linux, but (3) we are running under Cygwin with (4) a Windows
+ native toolchain. In this case, POSIX-style symbolic links are set
+ up but the Windows native toolchain cannot follow them.
+ The reason we are running 'make menuconfig' is to change from Linux
+ to Cygwin, but the target fails. During the context phase, NX runs
+ CPP to generate source files but that fails because the Windows native
+ toolchain cannot follow the links. Checkmate.
+ This was fixed by changing all of the make menuconfig (and related)
+ targets. They no longer depend on context being run. Instead, they
+ depend only on the dirlinks target. The dirlinks target only sets
+ up the directory links but does not try to run all of the context
+ setup; the compiler is never invoked; no code is autogeneraed; and
+ things work (2016-07-28).
+ * tools/refresh.sh: Recent complexities added to apps/ means that
+ configuration needs correct Make.defs file in place in order to
+ configure properly (2016-07-28).
+ * tools/kconfig2html.c: Update to handle absolute paths when sourcing
+ Kconfig files (2016-07-29).
+ * libc/math: This fixes the following libc/math issues: (1) asin[f l]()
+ use Newton’s method to converge on a solution. But Newton’s method
+ converges very slowly (> 500,000 iterations) for values of x close
+ to 1.0; and, in the case of asinl(), sometimes fails to converge
+ (loops forever). The attached patch uses an trig identity for
+ values of x > sqrt(2). The resultant functions converge in no more
+ than 5 iterations, 6 for asinl(). (2) The NuttX erf[f l]() functions
+ are based on Chebyshev fitting to a good guess. The problem there’s a
+ bug in the implementation that causes the functions to blow up with x
+ near -3.0. This patch fixes that problem. It should be noted that
+ this method returns the error function erf(x) with fractional error
+ less than 1.2E-07 and that’s fine for the float version erff(), but
+ the same method is used for double and long double version which
+ will yield only slightly better precision. This patch doesn't address
+ the issue of lower precision for erf() and erfl(). (3) a faster
+ version of copysignf() for floats is included. From David S. Alessio
+ (2016-07-30).
+ * I/O Expander: Remove hard-coded PCA9555 fields from ioexpander.h
+ definitons. Add support for an attach() method that may be used when
+ any subset of pin interrupts occur (2016-07-31).
+ * PCA9555 Driver: Replace the signalling logic with a simple callback
+ using the new definitons of ioexpander.h. This repartitioning of
+ functionality is necessary because (1) the I/O expander driver is the
+ lower-lower part of any driver that uses GPIOs (include the GPIO
+ driver itself) and should not be interacting directly with the much
+ higher level application layer. And (2) in order to be compatible
+ with the GPIO driver (and any arbitrary upper half driver), the
+ PCA9555 should not directly signal, but should call back into the
+ upper half. The upper half driver that interacts directly with the
+ application is the appropriate place to be generating signal
+ (2016-07-31).
+ * drivers/ioexpander/skeleton.c: Add a skeleton I/O Expander driver
+ (based on the PCA9555 driver) (2016-07-31).
+ * I/O Expander Interface: Encode and extend I/O expander options to
+ include interrupt configuration (2016-07-31).
+ * drivers/ioexpander: Add an (untested) TCA64XX I/O Expander driver
+ leveraged from Project Ara (2016-07-31).
+ * I/O Expander Interface: Add argument to interrupt callback. Add a
+ method to detach the interrupt (2016-08-01).
+ * drivers/ioexpander: Add a GPIO lower-half driver that can be used to
+ register a GPIO character driver for accessing pins on an I/O expander
+ (2016-08-01).
+ * drivers/ioexpander: Add PCF8574 I/O Expander driver. Some cleanup
+ also of other expander drivers (2016-08-01).
+ * drivers/ioexpander: GPIO driver: Add IOCTLs to get the pin type and
+ to unregister a signal handler (2016-08-01).
+ * configs/sim: Add simulator-based test support for apps/examples/gpio
+ 2016-08-01).
+ * drivers/sensors: Add KXJT9 Accelerometer driver from the Motorola
+ Moto Z MDK (2016-08-02).
+ * arch/arm/sim: Add a simulated I/O Expander driver (2016-08-03).
+ * configs/sim: Add logic to set the simulated I/O expander for testing
+ with apps/examples/gpio (2016-08-03).
+ * fs/fat: FAT performance improvement. In large files, seeking to a
+ position from the beginning of the file can be very time consuming.
+ ftell does lssek(fd, 0, SET_CURR). In that case, that is wasted time
+ since we are going to seek to the same position. This fix short-
+ circutes fat_seek() in all cases where we attempt to seek to current
+ position. Suggested by Nate Weibley (2016-08-03).
+ * tools/sethost.sh: Add sethost.sh. This is a script that you can use
+ to quickly change the host platform from Linux to Windows/Cygwin.
+ Might save you a lot of headaches (2016-08-03).
+ * arch/arm/src/tiva: Add tiva PWM lower-half driver implementation.
+ From Young (2016-08-05).
+ * drivers/spi/spi_transfer.c: Add a helper function that encapsulates
+ and manages a sequence of SPI transfers (2016-08-05).
+ * drivers/spi: Add an SPI character driver that will permit access to
+ the SPI bus for testing purposes. This driver is a simple wrapper
+ around spi_transfer() (2016-08-05).
+ * drivers/wireless: Add MFRC522 RFID ISO14443 and Mifare transceiver
+ driver. From Alan Carvalho de Assis (2016-08-06).
+ * configs/stm32f103-minimum: Add board support to MFRC522 driver. From
+ Alan Carvalho de Assis (2016-08-06).
+ * arch/renesas: Rename arch/sh to arch/renesas (2016-08-06).
+ * arch/arm/src/efm32, stm32, stm32l4: STM32 and EFM32 SPI drivers
+ adopted an incompatible conventions somewhere along the line. The
+ set the number of bits to negative when calling SPI_SETBITS which had
+ the magical side-effect of setting LSB first order of bit
+ transmission. This is not only a hokey way to pass control
+ information but is supported by no other SPI drivers. This change
+ three things: (1) It adds HWFEAT_LSBFIRST as a new H/W feature.
+ (2) It changes the implementations of SPI_SETBITS in the STM32 and
+ EFM32 derivers so that negated bit numbers are simply errors and it
+ adds the SPI_HWFEATURES method that can set the LSB bit order, and
+ (3) It changes all calls with negative number of bits from all
+ drivers: The number of bits is now always positive and SPI_HWFEATURES
+ is called with HWFEAT_LSBFIRST to set the bit order (2016-08-08).
+ * arch/arm/src/stm32: Add missing SPI2 and SPI3 support for STM32F3F3.
+ Add STM32F37XX DMA channel configuration. For STM32F37XX,
+ SYSCFG_EXTICR_PORTE defined twice. From Alan Carvalho de Assis
+ (2016-08-08).
+ * arch/arm/src/stm32: Make stm32_pwr_enablebkp thread safe. From
+ Max Neklyudov (2016-08-09).
+ * arch/arm/src/stm32: SAM3/4 GPIO: Enable peripheral clock for GPIO port
+ when GPIO is configured as input. The value of a GPIO input is only
+ sampled when the peripheral clock for the port controller the GPIO
+ resides in is enabled. Therefore we need to enable the clock even when
+ polling a GPIO. From Wolfgang Reissnegger (2016-08-09).
+ * arch/arm/src/tiva: Fix two bugs of tiva pwm lower-half driver
+ implementation. From Young (2016-08-10).
+ * sched/group: Explicitly initialize the group tg_exitsem with
+ sem_init(). The existing logic worked because the correct
+ initialization value is all zero, but it is better to initialize the
+ semaphore explicitly (2016-08-10).
+ * arch/arm/stm32: Fix bad pllmul values for STM32F1XX connectivity line.
+ STM32F1XX connectivity line supports only x4, x5, x6, x7, x8, x9 and
+ x6.5 values. From Michał Łyszczek (2016-08-11).
+ * include/nuttx/timers: Add oneshot timer lower half interface
+ (2016-08-11).
+ * arch/arm/src/stm32: Add a experimental oneshot, lower-half driver for
+ STM32 (2016-08-11).
+ * arch/arm/src/samv7: Add option to support oneshot timer without free-
+ running timer. Add oneshot lower half driver (2016-08-11).
+ * arch/arm/src/sama5: Add option to support oneshot timer without free-
+ running timer. Add oneshot lower half driver (2016-08-11).
+ * arch/arm/src/sam34: SAM4CM: Add option to support oneshot timer without
+ free-running timer. Add oneshot lower half driver (2016-08-11).
+ * arch/arm/src/stm32l4: Add oneshot lower half driver (2016-08-11).
+ * libc/stdlib: strtod() was not returning endptr on error conditions
+ (2016-08-11).
+ * libc/math: floor(), floorf(), and floorl(): Fix logic error. Was not
+ correctly handling negative integral value (2016-08-11).
+ * configs/sim: Add a configuration useful for testing Mini Basic
+ (2016-08-12).
+ * drivers/timers: Add an upper-half, oneshot timer character driver
+ (2016-08-12).
+ * arch/sim/src: Add a simulated oneshot lowerhalf driver (2016-08-12).
+ * arch/arm/src/stm32: STM32F3 SPI: Fix the number of bit setting for
+ the F3. That and data packing work differently on the STM32F3 than
+ for other STM32 parts (2016-08-12).
+ * arch/arm/stm32 and stm32l4: Enabling SPI DMA loses other bits in CR2
+ (2016-08-13).
+ * arch/arm/src/stm32: STM32F3 SPI: Cannot write always 16-bit value to
+ DR register because of how the F3 implements data packing (2016-08-13).
+ * Kinetis: Add support for I2C and RTC. From v01d (phreakuencies)
+ (2016-08-13).
+ * teensy 3.x i2c. From v01d (phreakuencies) (2016-08-13).
+ * SH1106 0.96 OLED module support (SSD1306 compatible) + I2C fixes.
+ From v01d (phreakuencies) (2016-08-13).
+ * Add support for SAMV7 DACC module. From iotr Mienkowski (2016-08-15).
+ * Add oneshot board initialization to stm32f103-minimum. From Alan
+ Carvalho de Assis (2016-08-15).
+ * drivers/audio/tone.c: Add Audio Tone Generator for NuttX. From Alan
+ Carvalho de Assis (2016-08-16).
+ * configs/stm32f103-minimum: Add board configuration to initialize Audio
+ Tone Generator. From Alan Carvalho de Assis (2016-08-16).
+ * STM32F411 and STM32F446 map i2c2_sda_4 to different alternate function
+ numbers. From Konstantin Berezenko (2016-08-17).
+ * STM32 DMA Fix: Change stm32 adc dma callback to send channel number
+ instead of index. From Konstantin Berezenko (2016-08-17).
+ * SAMA5: Add missing oneshot max_delay method (2016-08-18).
+ * configs/stm32bufferfly2: Add support for the Kamami stm32butterfly2
+ development board with optional ETH phy. From Michał Łyszczek
+ (2016-08-19).
+ * libc/misc: Separate XorShift128 PRNG from /dev/urandom and make it
+ generally available (2016-08-20).
+ * sched/sched_cpuload_oneshot: Use the oneshot timer with optional
+ entropy to measure cPU load if so configured (2016-08-20).
+ * drivers/usbhost/usbhost_composite.c: An an EXPERIMENTAL prototype of
+ how USB host support for composite devices might be implemented. This
+ feature is EXPERIMENTAL because (1) it is untested and (2) has some
+ know design issues that must be addressed before it can be of use
+ (2016-08-28).
+ * CXXFLAGS: add -fcheck-new whenever -fno-exceptions is used. From Beat
+ Küng (2016-08-23).
+ * tools/mkfsdata.pl was still generating the old-style apps/include
+ inclusion paths (2016-08-23).
+ * drivers/sensors: Add drvier for the LIS3MDL 3 axis magnetometer. From
+ Alexander Entinger (2016-08-23).
+ * drivers/sensors: Add driver for the MLX90393 3 axis magnetometer.
+ From Alexander Entinger (2016-08-23).
+ * drivers/mtd: Add Fujistu MB85RS256B ramtron support. From Beat Küng
+ (2016-08-23).
+ * drivers/sensors: Add driver for the LIS3DSH 3 axis accelerometer. From
+ Alexander Entinger (2016-08-24).
+ * drivers/sensors: Add driver for the Bosch BMG160 3 axis gyroscope.
+ From Alexander Entinger (2016-08-24).
+ * STM32: Add IAR-style STM32F1xx vectors. Tested on STM32F103RB and
+ STM32F107RC. From Aleksandr Vyhovanec (2016-08-24).
+ * libc/header files: Add POSIX type sig_atomic_t. From Sebastien
+ Lorquet (2016-08-24).
+ * libc/header files: isatty() should be prototypes in unstid.h, not
+ termios.h. From Sebastien Lorquet (2016-08-24).
+ * Documentation: Update to NuttX C coding style document with additions
+ discussing long comments on the right side of a statement or data
+ definition (2016-08-24).
+ * LPC43xx serial: Fix typos in LPC43 serial driver. Found by Vytautas
+ Lukenskas (2016-08-24).
+ * libc/time: This commit adds the difftime() function. The function
+ depends on the toolchain-dependent CONFIG_HAVE_DOUBLE so is not
+ available on tiny platforms. From Sebastien Lorquet (2016-08-24).
+ * libc/stdio: Add support for remove(). From Sebastien Lorquet
+ (2016-08-25).
+ * STM32 OTGFS device: Fix for lost first word from FIFO
+
+ 1) Do not overwrite Reserved Bits in GINTSTS (per ref manual)*
+ 2) Acknowledge all pending int on entry to ISR that are Only rc_w1*
+ 3) Do not disable RXFVL*
+ 4) Loop until RXFVL is cleared*
+ 5) Only clear the NAK on the endpoint on the
+ OTGFS_GRXSTSD_PKTSTS_SETUPDONE to not loose the first WORD of
+ FIFO all the data (Bug Fix)
+
+ Changed marked *are just driver clean up and ensure ints are not lost.
+ The bug fix is #5
+
+ Test case open putty and observer the Set/Get LineCoding. Without this
+ fix #5 the Get will not match the Set, and in fact the data might be
+ skewed by 4 bytes, that are lost from the FIFO if the
+ OTGFS_DOEPCTL0_CNAK bit is set in the OTGFS_GRXSTSD_PKTSTS_SETUPRECVD
+ as opposed to the OTGFS_GRXSTSD_PKTSTS_SETUPDONE
+
+ Set Line Coding DATA1: 4B | 00 c2 01 00 00 00 08 | c8 1B
+ Get Line Coding DATA1: 4B | .. .. .. .. 00 00 08 c8 .. 00 00 07 | 7a 72
+
+ From David Sidrane (2016-08-25).
+ * Add system() to stdlib.h. Actual implementation is in
+ apps/system/system (2016-08-25).
+ * include/nuttx/input: Add missing prototype for btn_lower_initialize()
+ (2016-08-27).
+ * configs/stm32f103-minimum: Add board config support to SPI LCD module
+ JLX12864G-086. From Alan Carvalho de Assis (2016-08-28).
+ * net/tcp: tcp_ipvX_bind() not actually using the ported selected with
+ port==0. Also removes duplicate call to pkt_input(). Issues noted by
+ Pascal Speck (2016-08-30).
+ * STM32 F7: Remove duplicate call to pkt_input from Ethernet driver.
+ Issues noted by Pascal Speck (2016-08-30).
+ * STM32L4 OTGFS device: Apply stm32 fix to stm32l4. From Sebastien
+ Lorquet (2016-08-31).
+ * drivers/contactless: Remove contactless drivers from drivers/wireless
+ to drivers contactless. From Sebastien Lorquet (2016-08-31).
+ * USB host composite is at least partially functional. No longer depends
+ on CONFIG_EXPERIMENTAL (2016-09-02).
+ * MTD: Fixed cloned typos in several FLASH drivers. From Aleksandr
+ Vyhovanec (2016-09-02).
+ * MTD: SPI-based driver for Macronix MX25L3233F or MX25L6433F. From
+ Aleksandr Vyhovanec (2016-09-02).
diff --git a/Documentation/NuttShell.html b/Documentation/NuttShell.html
index 7af455d577e..1d284dbea7a 100644
--- a/Documentation/NuttShell.html
+++ b/Documentation/NuttShell.html
@@ -8,7 +8,7 @@
NuttShell (NSH)
- Last Updated: July 20, 2016
+ Last Updated: August 4, 2016
|
@@ -3277,7 +3277,7 @@ nsh>
mkfifo |
- CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_PIPES |
+ CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_PIPES && CONFIG_DEV_FIFO_SIZE > 0 |
CONFIG_NSH_DISABLE_MKFIFO |
diff --git a/Documentation/NuttXCCodingStandard.html b/Documentation/NuttXCCodingStandard.html
index e3b3103297a..7505acfd136 100644
--- a/Documentation/NuttXCCodingStandard.html
+++ b/Documentation/NuttXCCodingStandard.html
@@ -12,7 +12,7 @@
NuttX C Coding Standard
- Last Updated: July 28, 2015
+ Last Updated: August 24, 2016
@@ -498,8 +498,8 @@
Comments to the Right of Statements.
- Comments to the right of statements in C source files are discouraged
- If such comments are used, they should at least be aligned so that the comment begins in the same comment on each line.
+ Comments to the right of statements in C source files are discouraged.
+ If such comments are used, they should be (1) very short so that they do not exceed the line width (typically 78 characters), (2) fit on one line, and (3) be aligned so that the comment begins in the same comment on each line.
|
@@ -538,7 +538,7 @@
Comments to the Right of Data Definitions.
- Comments to the right of a declaration with an enumeration or structure, on the other hand, are encourage.
+ Comments to the right of a declaration with an enumeration or structure, on the other hand, are encouraged, provided that the comments are short and do not exceed the maximum line width (usually 78 characters).
Columnar alignment of comments is very desireable (but often cannot be achieved without violating the line width).
@@ -586,6 +586,40 @@ struct animals_s
+
+ Long Comments on the Right.
+ Comments on the right of statements or data definitions must be short and fit on the same line without exceeding the maximum line length.
+ If a longer comment is needed, then it should appear above the statement of definition rather than to the right of the definition.
+
+
+|
+ Incorrect
+
+ dog = cat; /* This assignment will convert what was at one time a lowly dog into a ferocious feline. */
+
+ |
+|
+ Acceptable
+
+ dog = cat; /* This assignment will convert what was at one time a
+ * lowly dog into a ferocious feline. */
+
+ |
+|
+ Preferred
+
+ /* This assignment will convert what was at one time a lowly dog into a
+ * ferocious feline.
+ */
+
+ dog = cat;
+
+ |
+
+
+ Note that if the comment is continued on multiple lines, the comment alignment and multi-line comment rules still apply with one exception: The closing */ appears on the same line as the final text of the comment. This exception to the rule is enforced to keep the statements and definitions from becoming to spread out.
+
+
Block comments.
Block comments are only used to delimit groupings with the overall file organization and should not be used unless the usage is consistent with delimiting logical groupings in the program.
diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html
index bf32596fef0..7fa60d4d93b 100644
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -12,7 +12,7 @@
NuttX RTOS Porting Guide
- Last Updated: June 22, 2016
+ Last Updated: August 31, 2016
|
@@ -948,22 +948,46 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- (Common ADC and DAC driver source files)
+|-- audio/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common audio device source files)
|-- bch/
| |-- Kconfig
| |-- Make.defs
| `-- (bch driver source files)
+|-- contactless/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common contactless device driver source files)
|-- input/
| |-- Kconfig
| |-- Make.defs
| `-- (Common touchscreen and keypad driver source files)
+|-- ioexpander/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common I/O expander and GPIO-related driver source files)
|-- lcd/
| |-- Kconfig
| |-- Make.defs
| `-- (Common LCD driver source files)
+|-- leds/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common LED device driver source files)
+|-- loop/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common loop device driver source files)
|-- mmcsd/
| |-- Kconfig
| |-- Make.defs
| `-- (Common MMC/SD card driver source files)
+|-- modem/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common modem driver source files)
|-- mtd/
| |-- Kconfig
| |-- Make.defs
@@ -972,11 +996,19 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- (Common network driver source files)
+|-- pipes/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common pipe and FIFO driver source files)
+|-- power/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common power-related driver source files)
|-- sensors/
| |-- Kconfig
| |-- Make.defs
| `-- (Common sensor driver source files)
-|-- serial/
+|-- sercomm/
| |-- Kconfig
| |-- Make.defs
| `-- (Files for the Calypso SERCOMM driver)
@@ -984,6 +1016,18 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- (Common front-end character drivers for chip-specific UARTs)
+|-- spi/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Common SPI-related drivers and helper fuctions)
+|-- syslog/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (System logging device support)
+|-- timers/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (Timer-based device driver support)
|-- usbdev/
| |-- Kconfig
| |-- Make.defs
@@ -992,6 +1036,10 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- (Common USB host driver source files)
+|-- usbmonitor/
+| |-- Kconfig
+| |-- Make.defs
+| `-- (USB monitor source files)
|-- wireless/
| |-- Kconfig
| |-- Make.defs
@@ -1088,16 +1136,32 @@ include/
| | `-- (Audio driver header files)
| |-binfmt/
| | `-- (Binary format header files)
+| |-contactless/
+| | `-- (Contactless driver header files)
+| |-crypto/
+| | `-- (Cryptographic support header files)
+| |-drivers/
+| | `-- (Miscellaneous driver header files)
+| |-eeprom/
+| | `-- (EEPROM driver header files)
| |-fs/
| | `-- (File System header files)
| |-input/
| | `-- (Input device driver header files)
+| |-ioexpander/
+| | `-- (I/O exander and GPIO drvier header files)
| |-lcd/
| | `-- (LCD driver header files)
+| |-leds/
+| | `-- (LED driver header files)
+| |-lib/
+| | `-- (Non-standard C library driver header files)
+| |-mm/
+| | `-- (Memory management header files)
+| |-modem/
+| | `-- (Modem driver header files)
| |-mtd/
| | `-- (Memory technology device header files)
-| |-serial/
-| | `-- (Serial driver header files)
| |-net/
| | `-- (Networking header files)
| |-nx/
@@ -1114,8 +1178,12 @@ include/
| | `-- (SPI driver header files)
| |-syslog/
| | `-- (SYSLOG header files)
+| |-timers/
+| | `-- (Timer-related driver header files)
| |-usb/
| | `-- (USB driver header files)
+| |-video/
+| | `-- (Video-related driver header files)
| `-wireless/
| `-- (Wireless device driver header files)
`- sys/
@@ -1148,16 +1216,28 @@ include/
libc/
+|-- aio/
+| `-- (Implementation of functions from aio.h)
+|-- audio/
+| `-- (Implementation of audio-related functions)
+|-- dirent/
+| `-- (Implementation of functions from dirent.h)
+|-- fixedmath/
+| `-- (Implementation of functions from fixedmath.h)
+|-- hex2bin/
+| `-- (Implementation of functions from hex2bin.h)
|-- libgen/
| `-- (Implementation of functions from libgen.h)
|-- math/
| `-- (Implementation of functions from fixedmath.h)
|-- misc/
| `-- (Implementation of miscellaneous library functions)
-|-- mqueue/
-| `-- (Implementation of some functions from mqueue.h)
|-- net/
| `-- (Implementation of network-related library functions)
+|-- netdb/
+| `-- (Implementation of functions from netdb.h)
+|-- pthread/
+| `-- (Implementation of functions from pthread.h)
|-- queue/
| `-- (Implementation of functions from queue.h)
|-- sched/
@@ -1166,16 +1246,31 @@ libc/
| `-- (Implementation of some functions from semaphore.h)
|-- signal/
| `-- (Implementation of some functions from signal.h)
+|-- spawn/
+| `-- (Implementation of some functions from spawn.h)
|-- stdio/
| `-- (Implementation of functions from stdio.h)
|-- stdlib/
| `-- (Implementation of functions from stdlib.h)
|-- string/
| `-- (Implementation of functions from string.h)
+|-- symtab/
+| `-- (Implementation of symbol-table library functions)
+|-- syslog/
+| `-- (Implementation of functions from syslog.h)
+|-- termios/
+| `-- (Implementation of functions from termios.h)
|-- time/
| `-- (Implementation of some functions from time.h)
-`-- unistd/
- `-- (Implementation of some functions from unistd.h)
+|-- tls/
+| `-- (Implementation of some functions from tls.h)
+|-- wqueue/
+| `-- (Implementation of some functions from wqueue.h)
+|-- unistd/
+| `-- (Implementation of some functions from unistd.h)
+`-- zoneinfo/
+ `-- (Implementation of timezone database)
+
diff --git a/Documentation/README.html b/Documentation/README.html
index d9199a48271..4bbe2d956d0 100644
--- a/Documentation/README.html
+++ b/Documentation/README.html
@@ -31,11 +31,11 @@ nuttx/
| |- arm/
| | `- src
| | `- lpc214x/README.txt
- | |- sh/
+ | |- renesas/
| | |- include/
- | | | `-README.txt
+ | | | `-README.txt
| | |- src/
- | | | `-README.txt
+ | | | `-README.txt
| |- x86/
| | |- include/
| | | `-README.txt
diff --git a/Kconfig b/Kconfig
index 31f6f54629c..bf1f1c7b4b3 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1367,7 +1367,6 @@ endif # DEBUG_SPI
config DEBUG_TIMER
bool "Timer Debug Features"
default n
- depends on TIMER
---help---
Enable timer debug features.
diff --git a/Makefile.unix b/Makefile.unix
index bb249788974..d1ee224a67e 100644
--- a/Makefile.unix
+++ b/Makefile.unix
@@ -181,7 +181,7 @@ endif
BIN = nuttx$(EXEEXT)
all: $(BIN)
-.PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
+.PHONY: dirlinks context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
# Target used to copy include/nuttx/lib/math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
@@ -315,6 +315,8 @@ ifneq ($(CONFIG_ARCH_CHIP),)
endif
dirlinks: include/arch include/arch/board include/arch/chip $(ARCH_SRC)/board $(ARCH_SRC)/chip
+ $(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
+ $(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@@ -470,32 +472,32 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) tools/cnvwindeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# README.txt file in the NuttX tools GIT repository for additional information.
-do_config: context apps_preconfig
+do_config: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig
config: do_config clean_context
-do_oldconfig: context apps_preconfig
+do_oldconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig
oldconfig: do_oldconfig clean_context
-do_olddefconfig: context apps_preconfig
+do_olddefconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --olddefconfig Kconfig
olddefconfig: do_olddefconfig clean_context
-do_menuconfig: context apps_preconfig
+do_menuconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig
menuconfig: do_menuconfig clean_context
-do_qconfig: context apps_preconfig
+do_qconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-qconf Kconfig
qconfig: do_qconfig clean_context
-gconfig: context apps_preconfig
+gconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig
gconfig: do_gconfig clean_context
diff --git a/Makefile.win b/Makefile.win
index 1f30310525e..b15052f16ca 100644
--- a/Makefile.win
+++ b/Makefile.win
@@ -174,7 +174,7 @@ endif
BIN = nuttx$(EXEEXT)
all: $(BIN)
-.PHONY: context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
+.PHONY: dirlinks context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
# Target used to copy include\nuttx\math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
@@ -335,6 +335,8 @@ endif
endif
dirlinks: include\arch include\arch\board include\arch\chip $(ARCH_SRC)\board $(ARCH_SRC)\chip
+ $(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
+ $(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@@ -466,22 +468,22 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# misc\tools\README.txt for additional information.
-do_config: context apps_preconfig
+do_config: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig
config: do_config clean_context
-do_oldconfig: context apps_preconfig
+do_oldconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
oldconfig: do_oldconfig clean_context
-do_olddefconfig: context apps_preconfig
+do_olddefconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig
olddefconfig: do_olddefconfig clean_context
-do_menuconfig: context configenv apps_preconfig
+do_menuconfig: dirlinks configenv apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-mconf Kconfig
menuconfig: do_menuconfig clean_context
diff --git a/README.txt b/README.txt
index 8991f5d870a..3617f874a72 100644
--- a/README.txt
+++ b/README.txt
@@ -15,6 +15,7 @@ README
- NuttX Configuration Tool
- Finding Selections in the Configuration Menus
- Reveal Hidden Configuration Options
+ - Make Sure that You on on the Right Platform
- Comparing Two Configurations
- Incompatibilities with Older Configurations
- NuttX Configuration Tool under DOS
@@ -576,6 +577,38 @@ Reveal Hidden Configuration Options
cannot be selected and has no value). About all you do is to select
the option to see what the dependencies are.
+Make Sure that You on on the Right Platform
+-------------------------------------------
+
+ Saved configurations may run on Linux, Cygwin (32- or 64-bit), or other
+ platforms. The platform characteristics can be changed use 'make
+ menuconfig'. Sometimes this can be confusing due to the differences
+ between the platforms. Enter sethost.sh
+
+ sethost.sh is a simple script that changes a configuration to your
+ host platform. This can greatly simplify life if you use many different
+ configurations. For example, if you are running on Linux and you
+ configure like this:
+
+ $ cd tools
+ $ ./configure.sh board/configuration
+ $ cd ..
+
+ The you can use the following command to both (1) make sure that the
+ configuration is up to date, AND (2) the configuration is set up
+ correctly for Linux:
+
+ $ tools/sethost.sh -l
+
+ Or, if you are on a Windows/Cygwin 64-bit platform:
+
+ $ tools/sethost.sh -w
+
+ Other options are available from the help option built into the
+ script. You can see all options with:
+
+ $ tools/sethost.sh -h
+
Comparing Two Configurations
----------------------------
@@ -948,9 +981,13 @@ Native Windows Build
--------------------
The beginnings of a Windows native build are in place but still not often
- used as of this writing. The windows native build logic initiated
- if CONFIG_WINDOWS_NATIVE=y is defined in the NuttX configuration file:
+ used as of this writing. The build was functional but because of lack of
+ use may find some issues to be resolved with this build configuration.
+ The windows native build logic initiated if CONFIG_WINDOWS_NATIVE=y is
+ defined in the NuttX configuration file:
+
+
This build:
- Uses all Windows style paths
@@ -1213,7 +1250,7 @@ nuttx/
| |- arm/
| | `- src
| | `- lpc214x/README.txt
- | |- sh/
+ | |- renesas/
| | |- include/
| | | `-README.txt
| | |- src/
diff --git a/ReleaseNotes b/ReleaseNotes
index 27710f0c6b3..66e1c712c1e 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -9063,7 +9063,7 @@ detailed bugfix information):
for mq_setattr() and mq_getattr(). This is necessary in protected
and kernel builds because in those cases the message queue
structure is protected and cannot be accessed directly from user
- mode code. Noted by Jouko Holopainen.
+ mode code.
* File Systems/Block Drivers/MTD:
diff --git a/TODO b/TODO
index 9d3309122dc..5372b0aec50 100644
--- a/TODO
+++ b/TODO
@@ -219,7 +219,7 @@ o Task/Scheduler (sched/)
Description: Task control information is retained in simple lists. This
is completely appropriate for small embedded systems where
the number of tasks, N, is relatively small. Most list
- operations are O(N). This could become as issue if N gets
+ operations are O(N). This could become an issue if N gets
very large.
In that case, these simple lists should be replaced with
@@ -819,7 +819,7 @@ o Binary loaders (binfmt/)
"Read-Only Data in RAM" at
http://nuttx.org/Documentation/NuttXNxFlat.html#limitations).
- The newer 4.6.3compiler generated PC relative relocations to the strings:
+ The newer 4.6.3 compiler generated PC relative relocations to the strings:
.L2:
.word .LC0-(.LPIC0+4)
@@ -927,8 +927,7 @@ o Network (net/, drivers/net)
CONFIG_NET_NOINTS). This is really a very bad use of CPU
resources; All of the network stack processing should be
modified to use a work queue (and, all use of CONFIG_NET_NOINTS=n
- should be eliminated). This applies to almost all Ethernet
- drivers:
+ should be eliminated). This applies to many Ethernet drivers:
ARCHITECTURE CONFIG_NET_NOINTS? ADDRESS FILTER SUPPORT?
C5471 NO NO
@@ -1340,6 +1339,8 @@ o Libraries (libc/)
UPDATE: 2015-09-01: A fix for the noted problems with asin()
has been applied.
+ 2016-07-30: Numerous fixes and performance improvements from
+ David Alessio.
Status: Open
Priority: Low for casual users but clearly high if you need care about
@@ -1735,7 +1736,7 @@ o ARM (arch/arm/)
upon return. This could be improved as well: If there is no
context switch, then the static registers need not be restored
because they will not be modified by the called C code.
- (see arch/sh/src/sh1/sh1_vector.S for example)
+ (see arch/renesas/src/sh1/sh1_vector.S for example)
Status: Open
Priority: Low
diff --git a/arch/Kconfig b/arch/Kconfig
index fa5bf48edaa..319419bb2d1 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -45,7 +45,7 @@ config ARCH_RGMP
RTOS and GPOS on Multi-Processor (RGMP) architecture. See
http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
-config ARCH_SH
+config ARCH_RENESAS
bool "Renesas"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
@@ -83,23 +83,23 @@ endchoice
config ARCH
string
- default "arm" if ARCH_ARM
- default "avr" if ARCH_AVR
- default "hc" if ARCH_HC
- default "mips" if ARCH_MIPS
- default "rgmp" if ARCH_RGMP
- default "sh" if ARCH_SH
- default "sim" if ARCH_SIM
- default "x86" if ARCH_X86
- default "z16" if ARCH_Z16
- default "z80" if ARCH_Z80
+ default "arm" if ARCH_ARM
+ default "avr" if ARCH_AVR
+ default "hc" if ARCH_HC
+ default "mips" if ARCH_MIPS
+ default "rgmp" if ARCH_RGMP
+ default "renesas" if ARCH_RENESAS
+ default "sim" if ARCH_SIM
+ default "x86" if ARCH_X86
+ default "z16" if ARCH_Z16
+ default "z80" if ARCH_Z80
source arch/arm/Kconfig
source arch/avr/Kconfig
source arch/hc/Kconfig
source arch/mips/Kconfig
source arch/rgmp/Kconfig
-source arch/sh/Kconfig
+source arch/renesas/Kconfig
source arch/sim/Kconfig
source arch/x86/Kconfig
source arch/z16/Kconfig
diff --git a/arch/README.txt b/arch/README.txt
index 114f2f6f1e7..bd49fb31a7c 100644
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -150,11 +150,13 @@ arch/arm - ARM-based micro-controllers
Architecture Support
arch/arm/include and arch/arm/src/common
arch/arm/src/arm and arch/arm/include/arm
+ arch/arm/src/armv7-a and arch/arm/include/armv6-m
arch/arm/src/armv7-a and arch/arm/include/armv7-a
arch/arm/src/armv7-m and arch/arm/include/armv7-m
- arch/arm/src/armv7-r and arch/arm/include/armv7-4
+ arch/arm/src/armv7-r and arch/arm/include/armv7-r
MCU support
+ arch/arm/include/a1x and arch/arm/src/a1x
arch/arm/include/c5471 and arch/arm/src/c5471
arch/arm/include/calypso and arch/arm/src/calypso
arch/arm/include/dm320 and arch/arm/src/dm320
@@ -210,6 +212,16 @@ arch/mips
arch/mips/include/pic32mx and arch/mips/src/pic32mx
arch/mips/include/pic32mz and arch/mips/src/pic32mz
+arch/renesas - Support for Renesas and legacy Hitachi microcontrollers.
+ This include SuperH and M16C.
+
+ Architecture Support
+ arch/renesas/include and arch/renesas/src/common
+
+ MCU support
+ arch/renesas/include/m16c and arch/renesas/src/m16c
+ arch/renesas/include/sh1 and arch/renesas/src/sh1
+
arch/rgmp
RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
@@ -221,15 +233,6 @@ arch/rgmp
See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
information about RGMP.
-arch/sh - SuperH and related Hitachi/Renesas microcontrollers
-
- Architecture Support
- arch/sh/include and arch/sh/src/common
-
- MCU support
- arch/sh/include/m16c and arch/sh/src/m16c
- arch/sh/include/sh1 and arch/sh/src/sh1
-
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 87282302762..63af8acafc9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -51,6 +51,7 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32
bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
+ select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@@ -206,14 +207,15 @@ config ARCH_CHIP_SAM34
config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
- select ARMV7M_HAVE_STACKCHECK
select ARCH_HAVE_I2CRESET
+ select ARCH_HAVE_SPI_CS_CONTROL
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
+ select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
@@ -221,10 +223,12 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_TIMEKEEPING
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M3/4).
@@ -232,12 +236,13 @@ config ARCH_CHIP_STM32
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M7).
@@ -245,13 +250,14 @@ config ARCH_CHIP_STM32F7
config ARCH_CHIP_STM32L4
bool "STMicro STM32 L4"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M4).
diff --git a/arch/arm/include/calypso/clock.h b/arch/arm/include/calypso/clock.h
index abcfde1d449..a10a607a5d2 100644
--- a/arch/arm/include/calypso/clock.h
+++ b/arch/arm/include/calypso/clock.h
@@ -1,5 +1,5 @@
-#ifndef _CALYPSO_CLK_H
-#define _CALYPSO_CLK_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
#include
@@ -64,4 +64,4 @@ void calypso_debugunit(int enable);
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
-#endif /* _CALYPSO_CLK_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */
diff --git a/arch/arm/include/calypso/debug.h b/arch/arm/include/calypso/debug.h
index 8c7b9aabfbd..95969467757 100644
--- a/arch/arm/include/calypso/debug.h
+++ b/arch/arm/include/calypso/debug.h
@@ -1,5 +1,5 @@
-#ifndef _DEBUG_H
-#define _DEBUG_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@@ -28,4 +28,4 @@
#define printd(x, args ...)
#endif
-#endif /* _DEBUG_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */
diff --git a/arch/arm/include/calypso/defines.h b/arch/arm/include/calypso/defines.h
index 3c8732f92f8..4f29560c833 100644
--- a/arch/arm/include/calypso/defines.h
+++ b/arch/arm/include/calypso/defines.h
@@ -1,6 +1,5 @@
-
-#ifndef _DEFINES_H
-#define _DEFINES_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
#define __attribute_const__ __attribute__((__const__))
@@ -15,4 +14,4 @@
/* force placement in zero-waitstate memory */
#define __ramtext __section(".ramtext")
-#endif /* !_DEFINES_H */
+#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */
diff --git a/arch/arm/include/calypso/irq.h b/arch/arm/include/calypso/irq.h
index baea3de5a3f..0dda3f312fe 100644
--- a/arch/arm/include/calypso/irq.h
+++ b/arch/arm/include/calypso/irq.h
@@ -41,8 +41,8 @@
#error "This file should never be included directly! Use "
#endif
-#ifndef _CALYPSO_IRQ_H
-#define _CALYPSO_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
#ifndef __ASSEMBLY__
@@ -78,4 +78,4 @@ enum irq_nr {
#define IRQ_SYSTIMER IRQ_TIMER2
-#endif /* _CALYPSO_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */
diff --git a/arch/arm/include/calypso/memory.h b/arch/arm/include/calypso/memory.h
index b0a0490cec1..a4ce1e890ee 100644
--- a/arch/arm/include/calypso/memory.h
+++ b/arch/arm/include/calypso/memory.h
@@ -1,5 +1,5 @@
-#ifndef _MEMORY_H
-#define _MEMORY_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
@@ -25,4 +25,4 @@
#define readw(a) __arch_getw(a)
#define readl(a) __arch_getl(a)
-#endif /* _MEMORY_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */
diff --git a/arch/arm/include/calypso/timer.h b/arch/arm/include/calypso/timer.h
index 694e4ebc92e..93a1bd14925 100644
--- a/arch/arm/include/calypso/timer.h
+++ b/arch/arm/include/calypso/timer.h
@@ -1,5 +1,5 @@
-#ifndef _CAL_TIMER_H
-#define _CAL_TIMER_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
/* Enable or Disable a timer */
void hwtimer_enable(int num, int on);
@@ -22,4 +22,4 @@ void wdog_reset(void);
/* power up the timers */
void hwtimer_init(void);
-#endif /* _CAL_TIMER_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */
diff --git a/arch/arm/include/calypso/uwire.h b/arch/arm/include/calypso/uwire.h
index 19a277bccb5..0ca6c376ca7 100644
--- a/arch/arm/include/calypso/uwire.h
+++ b/arch/arm/include/calypso/uwire.h
@@ -1,5 +1,5 @@
-#ifndef _CALYPSO_UWIRE_H
-#define _CALYPSO_UWIRE_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
void uwire_init(void);
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
#endif
diff --git a/arch/arm/include/lpc214x/irq.h b/arch/arm/include/lpc214x/irq.h
index a4737c38d4b..852dd0c6495 100644
--- a/arch/arm/include/lpc214x/irq.h
+++ b/arch/arm/include/lpc214x/irq.h
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_LPC214X_IRQ_H
-#define __ARCH_LPC214X_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
/****************************************************************************
* Included Files
@@ -127,5 +127,5 @@ void up_detach_vector(int vector);
#endif
#endif
-#endif /* __ARCH_LPC214X_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC214X_IRQ_H */
diff --git a/arch/arm/include/lpc2378/irq.h b/arch/arm/include/lpc2378/irq.h
index 18ef58604b7..8fa2067fc97 100644
--- a/arch/arm/include/lpc2378/irq.h
+++ b/arch/arm/include/lpc2378/irq.h
@@ -43,8 +43,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_LPC2378_IRQ_H
-#define __ARCH_LPC2378_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
/****************************************************************************
* Included Files
@@ -149,4 +149,4 @@ void up_detach_vector(int vector);
#endif
#endif
-#endif /* __ARCH_LPC2378_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC2378_IRQ_H */
diff --git a/arch/arm/src/c5471/chip.h b/arch/arm/src/c5471/chip.h
index 580ae075dcd..e1f40e58d3e 100644
--- a/arch/arm/src/c5471/chip.h
+++ b/arch/arm/src/c5471/chip.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * c5471/chip.h
+ * arch/arm/src/c5471/chip.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __C5471_CHIP_H
-#define __C5471_CHIP_H
+#ifndef __ARCH_ARM_SRC_C5471_CHIP_H
+#define __ARCH_ARM_SRC_C5471_CHIP_H
/****************************************************************************
* Included Files
@@ -368,4 +368,4 @@
* Public Function Prototypes
****************************************************************************/
-#endif /* __C5471_CHIP_H */
+#endif /* __ARCH_ARM_SRC_C5471_CHIP_H */
diff --git a/arch/arm/src/calypso/chip.h b/arch/arm/src/calypso/chip.h
index 824fdce8935..bea381cc385 100644
--- a/arch/arm/src/calypso/chip.h
+++ b/arch/arm/src/calypso/chip.h
@@ -37,8 +37,8 @@
*
****************************************************************************/
-#ifndef __CALYPSO_CHIP_H
-#define __CALYPSO_CHIP_H
+#ifndef __ARCH_ARM_SRC_CALYPSO_CHIP_H
+#define __ARCH_ARM_SRC_CALYPSO_CHIP_H
/****************************************************************************
* Included Files
@@ -208,4 +208,4 @@
* Public Function Prototypes
****************************************************************************/
-#endif /* __CALYPSO_CHIP_H */
+#endif /* __ARCH_ARM_SRC_CALYPSO_CHIP_H */
diff --git a/arch/arm/src/dm320/chip.h b/arch/arm/src/dm320/chip.h
index 73e53b68317..20c722ab6a1 100644
--- a/arch/arm/src/dm320/chip.h
+++ b/arch/arm/src/dm320/chip.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_CHIP_H
-#define __DM320_CHIP_H
+#ifndef __ARCH_ARM_SRC_DM320_CHIP_H
+#define __ARCH_ARM_SRC_DM320_CHIP_H
/************************************************************************************
* Included Files
@@ -58,4 +58,4 @@
* Inline Functions
************************************************************************************/
-#endif /* __DM320_CHIP_H */
+#endif /* __ARCH_ARM_SRC_DM320_CHIP_H */
diff --git a/arch/arm/src/dm320/dm320_emif.h b/arch/arm/src/dm320/dm320_emif.h
index 653e20fe0d5..72d4e8947dc 100644
--- a/arch/arm/src/dm320/dm320_emif.h
+++ b/arch/arm/src/dm320/dm320_emif.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_DM320_EMIF_H
-#define __DM320_DM320_EMIF_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_EMIF_H
+#define __ARCH_ARM_SRC_DM320_DM320_EMIF_H
/************************************************************************************
* Included Files
@@ -105,4 +105,4 @@
#endif
-#endif /* __DM320_DM320_EMIF_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_EMIF_H */
diff --git a/arch/arm/src/dm320/dm320_gio.h b/arch/arm/src/dm320/dm320_gio.h
index 136e96118ce..5c0fdc73c3b 100644
--- a/arch/arm/src/dm320/dm320_gio.h
+++ b/arch/arm/src/dm320/dm320_gio.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_DM320GIO_H
-#define __DM320_DM320GIO_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_GIO_H
+#define __ARCH_ARM_SRC_DM320_DM320_GIO_H
/************************************************************************************
* Included Files
diff --git a/arch/arm/src/dm320/dm320_intc.h b/arch/arm/src/dm320/dm320_intc.h
index f05febb2f95..57bc5c1f346 100644
--- a/arch/arm/src/dm320/dm320_intc.h
+++ b/arch/arm/src/dm320/dm320_intc.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_DM320_INTC_H
-#define __DM320_DM320_INTC_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_INTC_H
+#define __ARCH_ARM_SRC_DM320_DM320_INTC_H
/************************************************************************************
* Included Files
@@ -98,4 +98,4 @@
#endif
-#endif /* __DM320_DM320_INTC_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_INTC_H */
diff --git a/arch/arm/src/dm320/dm320_memorymap.h b/arch/arm/src/dm320/dm320_memorymap.h
index 67923b15074..a5db5963615 100644
--- a/arch/arm/src/dm320/dm320_memorymap.h
+++ b/arch/arm/src/dm320/dm320_memorymap.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_MEMORYMAP_H
-#define __DM320_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
+#define __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
/************************************************************************************
* Included Files
@@ -261,4 +261,4 @@
#endif
-#endif /* __DM320_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H */
diff --git a/arch/arm/src/dm320/dm320_timer.h b/arch/arm/src/dm320/dm320_timer.h
index 2ef40790673..5b1830b98c7 100644
--- a/arch/arm/src/dm320/dm320_timer.h
+++ b/arch/arm/src/dm320/dm320_timer.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_TIMER_H
-#define __DM320_TIMER_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_TIMER_H
+#define __ARCH_ARM_SRC_DM320_DM320_TIMER_H
/************************************************************************************
* Included Files
@@ -105,4 +105,4 @@
#endif
-#endif /* __DM320_TIMER_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_TIMER_H */
diff --git a/arch/arm/src/dm320/dm320_uart.h b/arch/arm/src/dm320/dm320_uart.h
index d6684894120..af9c1df91f8 100644
--- a/arch/arm/src/dm320/dm320_uart.h
+++ b/arch/arm/src/dm320/dm320_uart.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_UART_H
-#define __DM320_UART_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_UART_H
+#define __ARCH_ARM_SRC_DM320_DM320_UART_H
/************************************************************************************
* Included Files
@@ -173,4 +173,4 @@
* Inline Functions
************************************************************************************/
-#endif /* __DM320_UART_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_UART_H */
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index c4dbb3b282d..0bf2c31a86a 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -185,6 +185,10 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
uint32_t frequency);
static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(struct spi_dev_s *dev, int nbits);
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev,
+ spi_hwfeatures_t features);
+#endif
static uint8_t spi_status(struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(struct spi_dev_s *dev, enum spi_dev_e devid,
@@ -218,7 +222,7 @@ static const struct spi_ops_s g_spiops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0,
+ .hwfeatures = spi_hwfeatures,
#endif
.status = spi_status,
#ifdef CONFIG_SPI_CMDDATA
@@ -976,47 +980,16 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
const struct efm32_spiconfig_s *config;
uint32_t regval;
uint32_t setting;
- bool lsbfirst;
spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && priv->config);
config = priv->config;
- /* Bit order is encoded by the sign of nbits */
+ /* Has the number of bits changed? */
- if (nbits < 0)
+ if (nbits != priv->nbits)
{
- /* LSB first */
-
- lsbfirst = true;
- nbits = -nbits;
- }
- else
- {
- /* MSH first */
-
- lsbfirst = false;
- }
-
- /* Has the number of bits or the bit order changed? */
-
- if (nbits != priv->nbits || lsbfirst != priv->lsbfirst)
- {
- /* Set the new bit order */
-
- regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
- if (lsbfirst)
- {
- regval &= ~USART_CTRL_MSBF;
- }
- else
- {
- regval |= USART_CTRL_MSBF;
- }
-
- spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
-
/* Select the new number of bits */
switch (nbits)
@@ -1086,11 +1059,78 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
* faster
*/
- priv->nbits = nbits;
- priv->lsbfirst = lsbfirst;
+ priv->nbits = nbits;
}
}
+/****************************************************************************
+ * Name: spi_hwfeatures
+ *
+ * Description:
+ * Set hardware-specific feature flags.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * features - H/W feature flags
+ *
+ * Returned Value:
+ * Zero (OK) if the selected H/W features are enabled; A negated errno
+ * value if any H/W feature is not supportable.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
+{
+#ifdef CONFIG_SPI_BITORDER
+ struct efm32_spidev_s *priv = (struct efm32_spidev_s *)dev;
+ const struct efm32_spiconfig_s *config;
+ uint32_t regval;
+ bool lsbfirst;
+
+ spiinfo("features=%08x\n", features);
+
+ DEBUGASSERT(priv && priv->config);
+ config = priv->config;
+
+ /* Bit order is encoded by the sign of nbits */
+
+ lsbfirst = ((features & HWFEAT_LSBFIRST) != 0);
+
+ /* Has the number of bits or the bit order changed? */
+
+ if (lsbfirst != priv->lsbfirst)
+ {
+ /* Set the new bit order */
+
+ regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
+ if (lsbfirst)
+ {
+ regval &= ~USART_CTRL_MSBF;
+ }
+ else
+ {
+ regval |= USART_CTRL_MSBF;
+ }
+
+ spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
+
+ /* Save the selection so the subsequence re-configurations will be
+ * faster
+ */
+
+ priv->lsbfirst = lsbfirst;
+ }
+
+ /* Other H/W features are not supported */
+
+ return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
+#else
+ return -ENOSYS;
+#endif
+}
+#endif
+
/****************************************************************************
* Name: spi_status
*
diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig
index 853de44c7db..17923818b5a 100644
--- a/arch/arm/src/kinetis/Kconfig
+++ b/arch/arm/src/kinetis/Kconfig
@@ -37,94 +37,130 @@ config ARCH_CHIP_MK20DX128VLH5
config ARCH_CHIP_MK20DX64VLH7
bool "MK20DX64VLH7"
select ARCH_FAMILY_K20
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK20DX128VLH7
bool "MK20DX128VLH7"
select ARCH_FAMILY_K20
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK20DX256VLH7
bool "MK20DX256VLH7"
select ARCH_FAMILY_K20
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40N512VLQ100
bool "MK40N512VLQ100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40N512VMD100
bool "MK40N512VMD100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X128VLQ100
bool "MK40X128VLQ100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X128VMD100
bool "MK40X128VMD100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X256VLQ100
bool "MK40X256VLQ100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X256VMD100
bool "MK40X256VMD100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK60N256VLQ100
bool "MK60N256VLQ100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK60N256VMD100
bool "MK60N256VMD100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VLL100
bool "MK60N512VLL100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VLQ100
bool "MK60N512VLQ100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VMD100
bool "MK60N512VMD100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60X256VLQ100
bool "MK60X256VLQ100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60X256VMD100
bool "MK60X256VMD100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FN1M0VLL12
bool "MK64FN1M0VLL12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VLL12
bool "MK64FX512VLL12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VDC12
bool "MK64FX512VDC12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FN1M0VDC12
bool "MK64FN1M0VDC12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VLQ12
bool "MK64FX512VLQ12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VMD12
bool "MK64FX512VMD12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FN1M0VMD12
bool "MK64FN1M0VMD12"
select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
endchoice
@@ -148,6 +184,14 @@ config ARCH_FAMILY_K64
menu "Kinetis Peripheral Support"
+config KINETIS_HAVE_I2C1
+ bool
+ default n
+
+config KINETIS_HAVE_I2C2
+ bool
+ default n
+
config KINETIS_TRACE
bool "Trace"
default n
@@ -255,12 +299,23 @@ config KINETIS_SPI2
config KINETIS_I2C0
bool "I2C0"
default n
+ select I2C
---help---
Support I2C0
config KINETIS_I2C1
bool "I2C1"
default n
+ select I2C
+ depends on KINETIS_HAVE_I2C1
+ ---help---
+ Support I2C1
+
+config KINETIS_I2C2
+ bool "I2C2"
+ default n
+ select I2C
+ depends on KINETIS_HAVE_I2C2
---help---
Support I2C1
@@ -418,6 +473,9 @@ config KINETIS_PIT
endmenu
+menu "Kinetis FTM PWM Configuration"
+ depends on KINETIS_FTM0 || KINETIS_FTM1 || KINETIS_FTM2
+
config KINETIS_FTM0_PWM
bool "FTM0 PWM"
default n
@@ -481,6 +539,8 @@ config KINETIS_FTM2_CHANNEL
If FTM2 is enabled for PWM usage, you also need specifies the timer output
channel {0,..,1}
+endmenu # Kinetis FTM PWM Configuration
+
menu "Kinetis GPIO Interrupt Configuration"
config KINETIS_GPIOIRQ
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index 9d4ea5083ab..bb7f54d87bb 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/kinetis/Make.defs
#
-# Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2011, 2013-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -131,6 +131,14 @@ ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += kinetis_pwm.c
endif
+ifeq ($(CONFIG_I2C),y)
+CHIP_CSRCS += kinetis_i2c.c
+endif
+
+ifeq ($(CONFIG_RTC),y)
+CHIP_CSRCS += kinetis_rtc.c
+endif
+
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_KINETIS_ENET),y)
CHIP_CSRCS += kinetis_enet.c
diff --git a/arch/arm/src/kinetis/chip/kinetis_i2c.h b/arch/arm/src/kinetis/chip/kinetis_i2c.h
index 94d071727b3..71f7624a46b 100644
--- a/arch/arm/src/kinetis/chip/kinetis_i2c.h
+++ b/arch/arm/src/kinetis/chip/kinetis_i2c.h
@@ -78,31 +78,35 @@
#define KINETIS_I2C0_SLTH (KINETIS_I2C0_BASE+KINETIS_I2C_SLTH_OFFSET)
#define KINETIS_I2C0_SLTL (KINETIS_I2C0_BASE+KINETIS_I2C_SLTL_OFFSET)
-#define KINETIS_I2C1_A1 (KINETIS_I2C1_BASE+KINETIS_I2C_A1_OFFSET)
-#define KINETIS_I2C1_F (KINETIS_I2C1_BASE+KINETIS_I2C_F_OFFSET)
-#define KINETIS_I2C1_C1 (KINETIS_I2C1_BASE+KINETIS_I2C_C1_OFFSET)
-#define KINETIS_I2C1_S (KINETIS_I2C1_BASE+KINETIS_I2C_S_OFFSET)
-#define KINETIS_I2C1_D (KINETIS_I2C1_BASE+KINETIS_I2C_D_OFFSET)
-#define KINETIS_I2C1_C2 (KINETIS_I2C1_BASE+KINETIS_I2C_C2_OFFSET)
-#define KINETIS_I2C1_FLT (KINETIS_I2C1_BASE+KINETIS_I2C_FLT_OFFSET)
-#define KINETIS_I2C1_RA (KINETIS_I2C1_BASE+KINETIS_I2C_RA_OFFSET)
-#define KINETIS_I2C1_SMB (KINETIS_I2C1_BASE+KINETIS_I2C_SMB_OFFSET)
-#define KINETIS_I2C1_A2 (KINETIS_I2C1_BASE+KINETIS_I2C_A2_OFFSET)
-#define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET)
-#define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET)
+#ifdef CONFIG_KINETIS_HAVE_I2C1
+# define KINETIS_I2C1_A1 (KINETIS_I2C1_BASE+KINETIS_I2C_A1_OFFSET)
+# define KINETIS_I2C1_F (KINETIS_I2C1_BASE+KINETIS_I2C_F_OFFSET)
+# define KINETIS_I2C1_C1 (KINETIS_I2C1_BASE+KINETIS_I2C_C1_OFFSET)
+# define KINETIS_I2C1_S (KINETIS_I2C1_BASE+KINETIS_I2C_S_OFFSET)
+# define KINETIS_I2C1_D (KINETIS_I2C1_BASE+KINETIS_I2C_D_OFFSET)
+# define KINETIS_I2C1_C2 (KINETIS_I2C1_BASE+KINETIS_I2C_C2_OFFSET)
+# define KINETIS_I2C1_FLT (KINETIS_I2C1_BASE+KINETIS_I2C_FLT_OFFSET)
+# define KINETIS_I2C1_RA (KINETIS_I2C1_BASE+KINETIS_I2C_RA_OFFSET)
+# define KINETIS_I2C1_SMB (KINETIS_I2C1_BASE+KINETIS_I2C_SMB_OFFSET)
+# define KINETIS_I2C1_A2 (KINETIS_I2C1_BASE+KINETIS_I2C_A2_OFFSET)
+# define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET)
+# define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET)
+#endif
-#define KINETIS_I2C2_A1 (KINETIS_I2C2_BASE+KINETIS_I2C_A1_OFFSET)
-#define KINETIS_I2C2_F (KINETIS_I2C2_BASE+KINETIS_I2C_F_OFFSET)
-#define KINETIS_I2C2_C1 (KINETIS_I2C2_BASE+KINETIS_I2C_C1_OFFSET)
-#define KINETIS_I2C2_S (KINETIS_I2C2_BASE+KINETIS_I2C_S_OFFSET)
-#define KINETIS_I2C2_D (KINETIS_I2C2_BASE+KINETIS_I2C_D_OFFSET)
-#define KINETIS_I2C2_C2 (KINETIS_I2C2_BASE+KINETIS_I2C_C2_OFFSET)
-#define KINETIS_I2C2_FLT (KINETIS_I2C2_BASE+KINETIS_I2C_FLT_OFFSET)
-#define KINETIS_I2C2_RA (KINETIS_I2C2_BASE+KINETIS_I2C_RA_OFFSET)
-#define KINETIS_I2C2_SMB (KINETIS_I2C2_BASE+KINETIS_I2C_SMB_OFFSET)
-#define KINETIS_I2C2_A2 (KINETIS_I2C2_BASE+KINETIS_I2C_A2_OFFSET)
-#define KINETIS_I2C2_SLTH (KINETIS_I2C2_BASE+KINETIS_I2C_SLTH_OFFSET)
-#define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET)
+#ifdef CONFIG_KINETIS_HAVE_I2C2
+# define KINETIS_I2C2_A1 (KINETIS_I2C2_BASE+KINETIS_I2C_A1_OFFSET)
+# define KINETIS_I2C2_F (KINETIS_I2C2_BASE+KINETIS_I2C_F_OFFSET)
+# define KINETIS_I2C2_C1 (KINETIS_I2C2_BASE+KINETIS_I2C_C1_OFFSET)
+# define KINETIS_I2C2_S (KINETIS_I2C2_BASE+KINETIS_I2C_S_OFFSET)
+# define KINETIS_I2C2_D (KINETIS_I2C2_BASE+KINETIS_I2C_D_OFFSET)
+# define KINETIS_I2C2_C2 (KINETIS_I2C2_BASE+KINETIS_I2C_C2_OFFSET)
+# define KINETIS_I2C2_FLT (KINETIS_I2C2_BASE+KINETIS_I2C_FLT_OFFSET)
+# define KINETIS_I2C2_RA (KINETIS_I2C2_BASE+KINETIS_I2C_RA_OFFSET)
+# define KINETIS_I2C2_SMB (KINETIS_I2C2_BASE+KINETIS_I2C_SMB_OFFSET)
+# define KINETIS_I2C2_A2 (KINETIS_I2C2_BASE+KINETIS_I2C_A2_OFFSET)
+# define KINETIS_I2C2_SLTH (KINETIS_I2C2_BASE+KINETIS_I2C_SLTH_OFFSET)
+# define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET)
+#endif
/* Register Bit Definitions *****************************************************************/
@@ -115,12 +119,90 @@
#define I2C_F_ICR_SHIFT (0) /* Bits 0-5: Clock rate */
#define I2C_F_ICR_MASK (0x3f << I2C_F_ICR_SHIFT)
+# define I2C_F_ICR(n) ((uint8_t)(n) << I2C_F_ICR_SHIFT)
#define I2C_F_MULT_SHIFT (6) /* Bits 6-7: Multiplier factor */
#define I2C_F_MULT_MASK (3 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_1 (0 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT)
+/* From Table 51-54. I2C divider and hold values. Duplicate divider values differ in hold
+ * times. Refer to the Table 51-54. in the K64 Sub-Family Reference Manual.
+ */
+
+#define I2C_F_DIV20 ((uint8_t)0x00)
+#define I2C_F_DIV22 ((uint8_t)0x01)
+#define I2C_F_DIV24 ((uint8_t)0x02)
+#define I2C_F_DIV26 ((uint8_t)0x03)
+#define I2C_F_DIV28 ((uint8_t)0x04)
+#define I2C_F_DIV30 ((uint8_t)0x05)
+#define I2C_F_DIV34 ((uint8_t)0x06)
+#define I2C_F_DIV36 ((uint8_t)0x0a)
+#define I2C_F_DIV40_1 ((uint8_t)0x07)
+#define I2C_F_DIV41 ((uint8_t)0x08)
+
+#define I2C_F_DIV32 ((uint8_t)0x09)
+#define I2C_F_DIV36 ((uint8_t)0x0a)
+#define I2C_F_DIV40_2 ((uint8_t)0x0b)
+#define I2C_F_DIV44 ((uint8_t)0x0c)
+#define I2C_F_DIV48_1 ((uint8_t)0x0d)
+#define I2C_F_DIV56_1 ((uint8_t)0x0e)
+#define I2C_F_DIV68 ((uint8_t)0x0f)
+
+#define I2C_F_DIV48_2 ((uint8_t)0x10)
+#define I2C_F_DIV56_2 ((uint8_t)0x11)
+#define I2C_F_DIV64 ((uint8_t)0x12)
+#define I2C_F_DIV72 ((uint8_t)0x13)
+#define I2C_F_DIV80_1 ((uint8_t)0x14)
+#define I2C_F_DIV88 ((uint8_t)0x15)
+#define I2C_F_DIV104 ((uint8_t)0x16)
+#define I2C_F_DIV128_1 ((uint8_t)0x17)
+
+#define I2C_F_DIV80_2 ((uint8_t)0x18)
+#define I2C_F_DIV96 ((uint8_t)0x19)
+#define I2C_F_DIV112 ((uint8_t)0x1a)
+#define I2C_F_DIV128_2 ((uint8_t)0x1b)
+#define I2C_F_DIV144 ((uint8_t)0x1c)
+#define I2C_F_DIV160_1 ((uint8_t)0x1d)
+#define I2C_F_DIV192_1 ((uint8_t)0x1e)
+#define I2C_F_DIV240 ((uint8_t)0x1f)
+
+#define I2C_F_DIV160_2 ((uint8_t)0x20)
+#define I2C_F_DIV192_2 ((uint8_t)0x1e)
+#define I2C_F_DIV224 ((uint8_t)0x22)
+#define I2C_F_DIV256 ((uint8_t)0x23)
+#define I2C_F_DIV288 ((uint8_t)0x24)
+#define I2C_F_DIV320_1 ((uint8_t)0x25)
+#define I2C_F_DIV384_1 ((uint8_t)0x26)
+#define I2C_F_DIV480 ((uint8_t)0x27)
+
+#define I2C_F_DIV320_2 ((uint8_t)0x28)
+#define I2C_F_DIV384_2 ((uint8_t)0x29)
+#define I2C_F_DIV448 ((uint8_t)0x2a)
+#define I2C_F_DIV512 ((uint8_t)0x2b)
+#define I2C_F_DIV576 ((uint8_t)0x2c)
+#define I2C_F_DIV640_1 ((uint8_t)0x2d)
+#define I2C_F_DIV768_1 ((uint8_t)0x2e)
+#define I2C_F_DIV960 ((uint8_t)0x2f)
+
+#define I2C_F_DIV640_2 ((uint8_t)0x30)
+#define I2C_F_DIV768_3 ((uint8_t)0x31)
+#define I2C_F_DIV896 ((uint8_t)0x32)
+#define I2C_F_DIV1024 ((uint8_t)0x33)
+#define I2C_F_DIV1152 ((uint8_t)0x34)
+#define I2C_F_DIV1280_1 ((uint8_t)0x35)
+#define I2C_F_DIV1536_1 ((uint8_t)0x36)
+#define I2C_F_DIV1920 ((uint8_t)0x37)
+
+#define I2C_F_DIV1280_2 ((uint8_t)0x38)
+#define I2C_F_DIV1536_2 ((uint8_t)0x39)
+#define I2C_F_DIV1792 ((uint8_t)0x3a)
+#define I2C_F_DIV2048 ((uint8_t)0x3b)
+#define I2C_F_DIV2304 ((uint8_t)0x3c)
+#define I2C_F_DIV2560 ((uint8_t)0x3d)
+#define I2C_F_DIV3072 ((uint8_t)0x3e)
+#define I2C_F_DIV3840 ((uint8_t)0x3f)
+
/* I2C Control Register 1 (8-bit) */
#define I2C_C1_DMAEN (1 << 0) /* Bit 0: DMA enable */
@@ -149,6 +231,7 @@
#define I2C_C2_AD_SHIFT (0) /* Bits 0-2: Slave address */
#define I2C_C2_AD_MASK (7 << I2C_C2_AD_SHIFT)
+# define I2C_C2_AD(n) ((uint8_t)(n) << I2C_C2_AD_SHIFT)
#define I2C_C2_RMEN (1 << 3) /* Bit 3: Range address matching enable */
#define I2C_C2_SBRC (1 << 4) /* Bit 4: Slave baud rate control */
#define I2C_C2_HDRS (1 << 5) /* Bit 5: High drive select */
@@ -156,9 +239,23 @@
#define I2C_C2_GCAEN (1 << 7) /* Bit 7: General call address enable */
/* I2C Programmable Input Glitch Filter register (8-bit) */
+
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
+# define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
+# define I2C_FLT_MASK (31 << I2C_FLT_SHIFT)
+# define I2C_FLT(n) ((uint8_t)(n) << I2C_FLT_SHIFT)
/* Bits 5-7: Reserved */
-#define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
-#define I2C_FLT_MASK (31 << I2C_FLT_SHIFT)
+#endif
+
+#ifdef KINETIS_K64
+# define I2C_FLT_SHIFT (0) /* Bits 0-3: I2C programmable filter factor */
+# define I2C_FLT_MASK (15 << I2C_FLT_SHIFT)
+# define I2C_FLT(n) ((uint8_t)(n) << I2C_FLT_SHIFT)
+# define I2C_FLT_STARTF (1 << 4) /* I2C bus start detect flag */
+# define I2C_FLT_SSIE (1 << 5) /* I2C bus stop or start interrupt enable */
+# define I2C_FLT_STOPF (1 << 6) /* I2C bus stop detect flag */
+# define I2C_FLT_SHEN (1 << 7) /* Stop hold enable */
+#endif
/* I2C Range Address register (8-bit) */
/* Bit 0: Reserved */
diff --git a/arch/arm/src/kinetis/chip/kinetis_rtc.h b/arch/arm/src/kinetis/chip/kinetis_rtc.h
index d00c02a6974..948c6ce8771 100644
--- a/arch/arm/src/kinetis/chip/kinetis_rtc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_rtc.h
@@ -59,7 +59,7 @@
#define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */
#define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */
#define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */
-#if defined(KINETIS_K40) || defined(KINETIS_K64)
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */
#endif
#ifdef KINETIS_K60
@@ -77,7 +77,7 @@
#define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET)
#define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET)
#define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET)
-#if defined(KINETIS_K40) || defined(KINETIS_K64)
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET)
#endif
#ifdef KINETIS_K60
@@ -135,13 +135,13 @@
#define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */
#define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */
#define RTC_LR_SRL (1 << 5) /* Bit 5: Status Register Lock */
-#ifdef KINETIS_K40
+#if defined(KINETIS_K20) || defined(KINETIS_K40)
# define RTC_LR_LRL (1 << 6) /* Bit 6: Lock Register Lock (K40) */
#endif
/* Bits 7-31: Reserved */
/* RTC Interrupt Enable Register (32-bits, K40) */
-#if defined(KINETIS_K40) || defined(KINETIS_K64)
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */
# define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */
# define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */
diff --git a/arch/arm/src/kinetis/kinetis_alarm.h b/arch/arm/src/kinetis/kinetis_alarm.h
new file mode 100644
index 00000000000..751cfd8cf05
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_alarm.h
@@ -0,0 +1,113 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_alarm.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_ALARM_H
+#define __ARCH_ARM_SRC_KINETIS_ALARM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_RTC_ALARM
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* The form of an alarm callback */
+
+typedef CODE void (*alarmcb_t)(void);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: kinetis_rtc_setalarm
+ *
+ * Description:
+ * Set up an alarm.
+ *
+ * Input Parameters:
+ * tp - the time to set the alarm
+ * callback - the function to call when the alarm expires.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+struct timespec;
+int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
+
+/****************************************************************************
+ * Name: kinetis_rtc_cancelalarm
+ *
+ * Description:
+ * Cancel a pending alarm alarm
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int kinetis_rtc_cancelalarm(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_RTC_ALARM */
+#endif /* __ARCH_ARM_SRC_KINETIS_ALARM_H */
diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c
new file mode 100644
index 00000000000..1713bdbbb1d
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_i2c.c
@@ -0,0 +1,1151 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_i2c.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "kinetis_config.h"
+#include "chip.h"
+#include "chip/kinetis_i2c.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_pinmux.h"
+#include "kinetis.h"
+#include "kinetis_i2c.h"
+
+#if defined(CONFIG_KINETIS_I2C0) || defined(CONFIG_KINETIS_I2C1) || \
+ defined(CONFIG_KINETIS_I2C2)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define I2C_TIMEOUT (20*1000/CONFIG_USEC_PER_TICK) /* 20 mS */
+
+#define I2C_DEFAULT_FREQUENCY 400000
+
+#define STATE_OK 0
+#define STATE_ARBITRATION_ERROR 1
+#define STATE_TIMEOUT 2
+#define STATE_NAK 3
+
+/* TODO:
+ * - revisar tamanio de todos los registros (getreg/putreg)
+ */
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* I2C device state structure */
+
+struct kinetis_i2cdev_s
+{
+ struct i2c_master_s dev; /* Generic I2C device */
+ uintptr_t base; /* Base address of registers */
+ uint32_t basefreq; /* Branch frequency */
+ uint32_t frequency; /* Current I2C frequency */
+ uint16_t irqid; /* IRQ for this device */
+ uint16_t nmsg; /* Number of transfer remaining */
+ uint16_t wrcnt; /* number of bytes sent to tx fifo */
+ uint16_t rdcnt; /* number of bytes read from rx fifo */
+ volatile uint8_t state; /* State of state machine */
+ bool restart; /* Should next transfer restart or not */
+ sem_t mutex; /* Only one thread can access at a time */
+ sem_t wait; /* Place to wait for state machine completion */
+ WDOG_ID timeout; /* watchdog to timeout when bus hung */
+ struct i2c_msg_s *msgs; /* Remaining transfers - first one is in
+ * progress */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register access */
+
+static uint8_t kinetis_i2c_getreg(struct kinetis_i2cdev_s *priv,
+ uint8_t offset);
+static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv,
+ uint8_t value, uint8_t offset);
+
+/* I2C helpers */
+
+static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
+ uint32_t frequency);
+static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv);
+static void kinetis_i2c_stop(struct kinetis_i2cdev_s *priv);
+static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv);
+#ifdef CONFIG_KINETIS_I2C0
+static int kinetis_i2c0_interrupt(int irq, void *context);
+#endif
+#ifdef CONFIG_KINETIS_I2C1
+static int kinetis_i2c1_interrupt(int irq, void *context);
+#endif
+#ifdef CONFIG_KINETIS_I2C2
+static int kinetis_i2c2_interrupt(int irq, void *context);
+#endif
+static void kinetis_i2c_timeout(int argc, uint32_t arg, ...);
+static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
+ uint32_t frequency);
+
+/* I2C lower half driver methods */
+
+static int kinetis_i2c_transfer(struct i2c_master_s *dev,
+ struct i2c_msg_s *msgs, int count);
+#ifdef CONFIG_I2C_RESET
+static int kinetis_i2c_reset(struct i2c_master_s *dev);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* I2C lower half driver operations */
+
+static const struct i2c_ops_s g_i2c_ops =
+{
+ .transfer = kinetis_i2c_transfer
+#ifdef CONFIG_I2C_RESET
+ ,.reset = kinetis_i2c_reset
+#endif
+};
+
+/* I2C device state instances */
+
+#ifdef CONFIG_KINETIS_I2C0
+static struct kinetis_i2cdev_s g_i2c0_dev;
+#endif
+#ifdef CONFIG_KINETIS_I2C1
+static struct kinetis_i2cdev_s g_i2c1_dev;
+#endif
+#ifdef CONFIG_KINETIS_I2C2
+static struct kinetis_i2cdev_s g_i2c2_dev;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_i2c_getreg
+ *
+ * Description:
+ * Get a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static uint8_t kinetis_i2c_getreg(struct kinetis_i2cdev_s *priv,
+ uint8_t offset)
+{
+ return getreg8(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_putreg
+ *
+ * Description:
+ * Put a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv, uint8_t offset,
+ uint8_t value)
+{
+ putreg8(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_setfrequency
+ *
+ * Description:
+ * Set the frequency for the next transfer
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
+ uint32_t frequency)
+{
+ i2cinfo("frequency=%lu\n", (unsigned long)frequency);
+
+ if (frequency == priv->frequency)
+ {
+ return;
+ }
+
+#if BOARD_BUS_FREQ == 120000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV1152, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV288, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV128, KINETIS_I2C_F_OFFSET); /* 0.94 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 108000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV1024, KINETIS_I2C_F_OFFSET); /* 105 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV256, KINETIS_I2C_F_OFFSET); /* 422 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV112, KINETIS_I2C_F_OFFSET); /* 0.96 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 96000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV960, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV240, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV96, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 90000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV896, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV224, KINETIS_I2C_F_OFFSET); /* 402 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV88, KINETIS_I2C_F_OFFSET); /* 1.02 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 80000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV768, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV192, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV80, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 72000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV640, KINETIS_I2C_F_OFFSET); /* 112 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV192, KINETIS_I2C_F_OFFSET); /* 375 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV72, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 64000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV640, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV160, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 60000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV576, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV144, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 938 kHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 56000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV512, KINETIS_I2C_F_OFFSET); /* 109 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV144, KINETIS_I2C_F_OFFSET); /* 389 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV56_1, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 54000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV512, KINETIS_I2C_F_OFFSET); /* 105 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV128, KINETIS_I2C_F_OFFSET); /* 422 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV56, KINETIS_I2C_F_OFFSET); /* 0.96 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 48000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV480, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV112, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV48_1, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 40000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV384_2, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV96, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV40_2, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(3), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 36000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV320_2, KINETIS_I2C_F_OFFSET); /* 113 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV96, KINETIS_I2C_F_OFFSET); /* 375 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV36, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(3), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 24000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV240, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 375 kHz */
+ }
+ else
+ {161
+ kinetis_i2c_putreg(priv, I2C_F_DIV24, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(2), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 16000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV160_2, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV40_1, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 800 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 8000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV80_1, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 4000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV40_1, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 200 kHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 2000000
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#else
+# error "F_BUS must be 120, 108, 96, 9, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 16, 8, 4 or 2 MHz"
+#endif
+
+ priv->frequency = frequency;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_start
+ *
+ * Description:
+ * Initiate I2C transfer (START/RSTART + address)
+ *
+ ****************************************************************************/
+
+static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv)
+{
+ struct i2c_msg_s *msg;
+
+ i2cinfo("START msg=%p\n", priv->msgs);
+ msg = priv->msgs;
+
+ /* Now take control of the bus */
+
+ if (kinetis_i2c_getreg(priv, KINETIS_I2C_C1_OFFSET) & I2C_C1_MST)
+ {
+ /* We are already the bus master, so send a repeated start */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST |
+ I2C_C1_RSTA | I2C_C1_TX, KINETIS_I2C_C1_OFFSET);
+ }
+ else
+ {
+ /* We are not currently the bus master, so wait for bus ready */
+
+ while (kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET) & I2C_S_BUSY);
+
+ /* Become the bus master in transmit mode (send start) */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST |
+ I2C_C1_TX, KINETIS_I2C_C1_OFFSET);
+ }
+
+ if (I2C_M_READ & msg->flags) /* DEBUG: should happen always */
+ {
+ /* Wait until start condition establishes control of the bus */
+
+ while (1)
+ {
+ if (kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET) & I2C_S_BUSY)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Initiate actual transfer (send address) */
+
+ kinetis_i2c_putreg(priv, (I2C_M_READ & msg->flags) == I2C_M_READ ?
+ I2C_READADDR8(msg->addr) : I2C_WRITEADDR8(msg->addr),
+ KINETIS_I2C_D_OFFSET);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_stop
+ *
+ * Description:
+ * Perform a I2C transfer stop
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_stop(struct kinetis_i2cdev_s *priv)
+{
+ i2cinfo("STOP msg=%p\n", priv->msgs);
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE,
+ KINETIS_I2C_C1_OFFSET);
+ sem_post(&priv->wait);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_timeout
+ *
+ * Description:
+ * Watchdog timer for timeout of I2C operation
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_timeout(int argc, uint32_t arg, ...)
+{
+ struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)arg;
+
+ DEBUGASSERT(priv != NULL);
+ i2cinfo("Timeout msg=%p\n", priv->msgs);
+
+ irqstate_t flags = enter_critical_section();
+ priv->state = STATE_TIMEOUT;
+ sem_post(&priv->wait);
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_nextmsg
+ *
+ * Description:
+ * Setup for the next message.
+ *
+ ****************************************************************************/
+
+void kinetis_i2c_nextmsg(struct kinetis_i2cdev_s *priv)
+{
+ priv->nmsg--;
+ i2cinfo("nmsg=%u\n", priv->nmsg);
+
+ if (priv->nmsg > 0)
+ {
+ priv->msgs++;
+ i2cinfo("msg=%p\n", priv->msgs);
+
+ priv->wrcnt = 0;
+ priv->rdcnt = 0;
+
+ if (priv->restart)
+ {
+ sem_post(&priv->wait);
+ }
+ }
+ else
+ {
+ kinetis_i2c_stop(priv);
+ }
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_interrupt
+ *
+ * Description:
+ * The I2C common interrupt handler
+ *
+ ****************************************************************************/
+
+static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv)
+{
+ struct i2c_msg_s *msg;
+ uint32_t state;
+ int regval;
+ int dummy;
+ UNUSED(dummy);
+
+ /* Get current state */
+
+ state = kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET);
+ msg = priv->msgs;
+
+ /* Arbitration lost */
+
+ if (state & I2C_S_ARBL)
+ {
+ kinetis_i2c_putreg(priv, I2C_S_IICIF | I2C_S_ARBL,
+ KINETIS_I2C_S_OFFSET);
+ priv->state = STATE_ARBITRATION_ERROR;
+ kinetis_i2c_stop(priv);
+ }
+ else
+ {
+ /* Clear interrupt */
+
+ kinetis_i2c_putreg(priv, I2C_S_IICIF, KINETIS_I2C_S_OFFSET);
+ regval = kinetis_i2c_getreg(priv, KINETIS_I2C_C1_OFFSET);
+
+ /* TX mode */
+
+ if (regval & I2C_C1_TX)
+ {
+ /* Last write was not acknowledged */
+
+ if (state & I2C_S_RXAK)
+ {
+ priv->state = STATE_NAK; /* Set error flag */
+ kinetis_i2c_stop(priv); /* Send STOP */
+ }
+ else
+ {
+ /* Actually intending to write */
+
+ if ((I2C_M_READ & msg->flags) == 0)
+ {
+ /* Wrote everything */
+
+ if (priv->wrcnt == msg->length)
+ {
+ /* Continue with next message */
+
+ kinetis_i2c_nextmsg(priv);
+
+ if (!priv->restart)
+ {
+ /* Initiate transfer of following message */
+
+ kinetis_i2c_putreg(priv,
+ priv->msgs->buffer[priv->wrcnt],
+ KINETIS_I2C_D_OFFSET);
+ priv->wrcnt++;
+
+ sem_post(&priv->wait);
+ }
+ }
+ else
+ {
+ /* Put next byte */
+
+ kinetis_i2c_putreg(priv, msg->buffer[priv->wrcnt],
+ KINETIS_I2C_D_OFFSET);
+ priv->wrcnt++;
+ }
+ }
+
+ /* Actually intending to read (address was just sent) */
+
+ else
+ {
+ if (msg->length == 1 && priv->restart)
+ {
+ /* Go to RX mode, do not send ACK */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TXAK,
+ KINETIS_I2C_C1_OFFSET);
+ }
+ else
+ {
+ /* Go to RX mode */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST, KINETIS_I2C_C1_OFFSET);
+ }
+
+ /* TODO: handle zero-length reads */
+ /* Dummy read to initiate reception */
+
+ dummy = kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ }
+ }
+ }
+
+ /* RX: mode */
+
+ else
+ {
+ /* If last receiving byte */
+
+ if (priv->rdcnt == (msg->length - 1))
+ {
+ if (priv->restart)
+ {
+ /* Go to TX mode before last read, otherwise a new read is
+ * triggered.
+ */
+
+ /* Go to TX mode */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TX,
+ KINETIS_I2C_C1_OFFSET);
+ }
+ else if ((priv->msgs + 1)->length == 1)
+ {
+ /* We will continue reception on next message.
+ * if next message is length == 1, this is actually the
+ * 2nd to last byte, so do not send ACK.
+ */
+
+ /* Do not ACK any more */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TXAK,
+ KINETIS_I2C_C1_OFFSET);
+ }
+
+ msg->buffer[priv->rdcnt] =
+ kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ priv->rdcnt++;
+
+ kinetis_i2c_nextmsg(priv);
+ }
+
+ /* Second to last receiving byte */
+
+ else if (priv->rdcnt == (msg->length - 2))
+ {
+ if (priv->restart)
+ {
+ /* Do not ACK any more */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TXAK, KINETIS_I2C_C1_OFFSET);
+ }
+
+ msg->buffer[priv->rdcnt] =
+ kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ priv->rdcnt++;
+ }
+ else
+ {
+ msg->buffer[priv->rdcnt] =
+ kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ priv->rdcnt++;
+ }
+ }
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2cN_interrupt
+ *
+ * Description:
+ * The I2CN interrupt handlers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_KINETIS_I2C0
+static int kinetis_i2c0_interrupt(int irq, void *context)
+{
+ i2cinfo("I2C0 Interrupt...\n");
+ return kinetis_i2c_interrupt(&g_i2c0_dev);
+}
+#endif
+
+#ifdef CONFIG_KINETIS_I2C1
+static int kinetis_i2c1_interrupt(int irq, void *context)
+{
+ i2cinfo("I2C1 Interrupt...\n");
+ return kinetis_i2c_interrupt(&g_i2c1_dev);
+}
+#endif
+
+#ifdef CONFIG_KINETIS_I2C2
+static int kinetis_i2c2_interrupt(int irq, void *context)
+{
+ i2cinfo("I2C2 Interrupt...\n");
+ return kinetis_i2c_interrupt(&g_i2c2_dev);
+}
+#endif
+
+/****************************************************************************
+ * Name: kinetis_i2c_transfer
+ *
+ * Description:
+ * Perform a sequence of I2C transfers
+ *
+ ****************************************************************************/
+
+static int kinetis_i2c_transfer(struct i2c_master_s *dev,
+ struct i2c_msg_s *msgs, int count)
+{
+ struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)dev;
+ int msg_n;
+
+ i2cinfo("msgs=%p count=%d\n", msgs, count);
+ DEBUGASSERT(dev != NULL && msgs != NULL && (unsigned)count <= UINT16_MAX);
+
+ /* Get exclusive access to the I2C bus */
+
+ sem_wait(&priv->mutex);
+
+ /* Set up for the transfer */
+
+ msg_n = 0;
+ priv->msgs = msgs;
+ priv->nmsg = count;
+ priv->state = STATE_OK;
+ priv->wrcnt = 0;
+ priv->rdcnt = 0;
+
+ /* Configure the I2C frequency. REVISIT: Note that the frequency is set
+ * only on the first message. This could be extended to support
+ * different transfer frequencies for each message segment.
+ */
+
+ kinetis_i2c_setfrequency(priv, msgs->frequency);
+
+ /* Clear the status flags */
+
+ kinetis_i2c_putreg(priv, I2C_S_IICIF | I2C_S_ARBL, KINETIS_I2C_S_OFFSET);
+
+ /* Process every message */
+
+ while (priv->nmsg > 0 && priv->state == STATE_OK)
+ {
+ priv->restart = true;
+
+ /* Process NORESTART flag */
+
+ if (priv->nmsg > 1)
+ {
+ struct i2c_msg_s* nextmsg = (priv->msgs + 1);
+
+ /* If there is a following message with "norestart" flag of
+ * the same type as the current one, we can avoid the restart
+ */
+
+ if ((nextmsg->flags & I2C_M_NORESTART) &&
+ nextmsg->addr == priv->msgs->addr &&
+ nextmsg->frequency == priv->msgs->frequency &&
+ (nextmsg->flags & I2C_M_READ) == (priv->msgs->flags & I2C_M_READ))
+ {
+ /* "no restart" can be performed */
+
+ priv->restart = false;
+ }
+ }
+
+ /* Only send start when required (we are trusting the flags setting to
+ * be correctly used here).
+ */
+
+ if (!(priv->msgs->flags & I2C_M_NORESTART))
+ {
+ /* Initiate the transfer, in case restart is required */
+
+ kinetis_i2c_start(priv);
+ }
+
+ /* Wait for transfer complete */
+
+ wd_start(priv->timeout, I2C_TIMEOUT, kinetis_i2c_timeout, 1,
+ (uint32_t) priv);
+ sem_wait(&priv->wait);
+
+ wd_cancel(priv->timeout);
+
+ msg_n++;
+ }
+
+ /* Disable interrupts */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN, KINETIS_I2C_C1_OFFSET);
+
+ /* Release access to I2C bus */
+
+ sem_post(&priv->mutex);
+
+ if (priv->state != STATE_OK)
+ {
+ return -EIO;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/************************************************************************************
+ * Name: kinetis_i2c_reset
+ *
+ * Description:
+ * Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_RESET
+static int kinetis_i2c_reset(struct i2c_master_s *dev)
+{
+ i2cinfo("No reset...\n");
+ return OK;
+}
+#endif /* CONFIG_I2C_RESET */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_i2cbus_initialize
+ *
+ * Description:
+ * Initialise an I2C device
+ *
+ ****************************************************************************/
+
+struct i2c_master_s *kinetis_i2cbus_initialize(int port)
+{
+ struct kinetis_i2cdev_s *priv;
+ xcpt_t handler;
+
+ i2cinfo("port=%d\n", port);
+
+ if (port > 1)
+ {
+ i2cerr("ERROR: Kinetis I2C Only suppors ports 0 and 1\n");
+ return NULL;
+ }
+
+ irqstate_t flags;
+ uint32_t regval;
+
+ flags = enter_critical_section();
+
+#ifdef CONFIG_KINETIS_I2C0
+ if (port == 0)
+ {
+ priv = &g_i2c0_dev;
+ priv->base = KINETIS_I2C0_BASE;
+ priv->irqid = KINETIS_IRQ_I2C0;
+ priv->basefreq = BOARD_BUS_FREQ;
+
+ handler = kinetis_i2c0_interrupt;
+
+ /* Enable clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_I2C0;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+ /* Disable while configuring */
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ /* Configure pins */
+
+ kinetis_pinconfig(PIN_I2C0_SCL);
+ kinetis_pinconfig(PIN_I2C0_SDA);
+ }
+ else
+#endif
+#ifdef CONFIG_KINETIS_I2C1
+ if (port == 1)
+ {
+ priv = &g_i2c1_dev;
+ priv->base = KINETIS_I2C1_BASE;
+ priv->irqid = KINETIS_IRQ_I2C1;
+ priv->basefreq = BOARD_BUS_FREQ;
+
+ handler = kinetis_i2c1_interrupt;
+
+ /* Enable clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_I2C1;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+ /* Disable while configuring */
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ /* Configure pins */
+
+ kinetis_pinconfig(PIN_I2C1_SCL);
+ kinetis_pinconfig(PIN_I2C1_SDA);
+ }
+ else
+#endif
+#ifdef CONFIG_KINETIS_I2C2
+ if (port == 2)
+ {
+ priv = &g_i2c2_dev;
+ priv->base = KINETIS_I2C2_BASE;
+ priv->irqid = KINETIS_IRQ_I2C2;
+ priv->basefreq = BOARD_BUS_FREQ;
+
+ handler = kinetis_i2c2_interrupt;
+
+ /* Enable clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_I2C2;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+ /* Disable while configuring */
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ /* Configure pins */
+
+ kinetis_pinconfig(PIN_I2C2_SCL);
+ kinetis_pinconfig(PIN_I2C2_SDA);
+ }
+ else
+#endif
+ {
+ leave_critical_section(flags);
+ i2cerr("ERROR: Unsupport I2C bus: %d\n", port);
+ return NULL;
+ }
+
+ /* Set the default I2C frequency */
+
+ kinetis_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY);
+
+ /* Enable */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN, KINETIS_I2C_C1_OFFSET);
+
+ /* High-drive select (TODO: why)? */
+
+ regval = kinetis_i2c_getreg(priv, KINETIS_I2C_C2_OFFSET);
+ regval |= I2C_C2_HDRS;
+ kinetis_i2c_putreg(priv, regval, KINETIS_I2C_C2_OFFSET);
+
+ leave_critical_section(flags);
+
+ sem_init(&priv->mutex, 0, 1);
+ sem_init(&priv->wait, 0, 0);
+
+ /* Allocate a watchdog timer */
+
+ priv->timeout = wd_create();
+ DEBUGASSERT(priv->timeout != 0);
+
+ /* Attach Interrupt Handler */
+
+ irq_attach(priv->irqid, handler);
+
+ /* Enable Interrupt Handler */
+
+ up_enable_irq(priv->irqid);
+
+ /* Install our operations */
+
+ priv->dev.ops = &g_i2c_ops;
+ return &priv->dev;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2cbus_uninitialize
+ *
+ * Description:
+ * Uninitialise an I2C device
+ *
+ ****************************************************************************/
+
+int kinetis_i2cbus_uninitialize(struct i2c_master_s *dev)
+{
+ struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)dev;
+
+ DEBUGASSERT(priv != NULL);
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ up_disable_irq(priv->irqid);
+ irq_detach(priv->irqid);
+ return OK;
+}
+
+#endif /* CONFIG_KINETIS_I2C0 || CONFIG_KINETIS_I2C1 || CONFIG_KINETIS_I2C2 */
diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/kinetis_i2c.h
new file mode 100644
index 00000000000..098e4d39add
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_i2c.h
@@ -0,0 +1,87 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_i2c.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include "chip/kinetis_i2c.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_i2cbus_initialize
+ *
+ * Description:
+ * Initialize the selected I2C port. And return a unique instance of struct
+ * struct i2c_master_s. This function may be called to obtain multiple
+ * instances of the interface, each of which may be set up with a
+ * different frequency and slave address.
+ *
+ * Input Parameter:
+ * Port number (for hardware that has multiple I2C interfaces)
+ *
+ * Returned Value:
+ * Valid I2C device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct i2c_master_s *kinetis_i2cbus_initialize(int port);
+
+/****************************************************************************
+ * Name: kinetis_i2cbus_uninitialize
+ *
+ * Description:
+ * De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameter:
+ * Device structure as returned by the lpc43_i2cbus_initialize()
+ *
+ * Returned Value:
+ * OK on success, ERROR when internal reference count mismatch or dev
+ * points to invalid hardware device.
+ *
+ ****************************************************************************/
+
+int kinetis_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H */
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
index d4ccc74090c..4eea85bd420 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -58,7 +58,7 @@
#include "chip.h"
#include "kinetis.h"
-#include "chip/kinetis_pwm.h"
+#include "kinetis_pwm.h"
#include "chip/kinetis_gpio.h"
#include "chip/kinetis_ftm.h"
#include "chip/kinetis_sim.h"
diff --git a/arch/arm/src/kinetis/kinetis_rtc.c b/arch/arm/src/kinetis/kinetis_rtc.c
new file mode 100644
index 00000000000..ca0f4848d19
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_rtc.c
@@ -0,0 +1,373 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_rtc.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "up_arch.h"
+
+#include "kinetis_config.h"
+#include "chip.h"
+#include "chip/kinetis_rtc.h"
+#include "chip/kinetis_sim.h"
+#include "kinetis.h"
+#include "kinetis_alarm.h"
+
+#if defined(CONFIG_RTC)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static alarmcb_t g_alarmcb;
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile bool g_rtc_enabled = false;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_rtc_interrupt
+ *
+ * Description:
+ * RTC interrupt service routine
+ *
+ * Input Parameters:
+ * irq - The IRQ number that generated the interrupt
+ * context - Architecture specific register save information.
+ *
+ * Returned Value:
+ * Zero (OK) on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_ALARM)
+static int kinetis_rtc_interrupt(int irq, void *context)
+{
+ if (g_alarmcb != NULL)
+ {
+ /* Alarm callback */
+
+ g_alarmcb();
+ g_alarmcb = NULL;
+ }
+
+ /* Clear pending flags, disable alarm */
+
+ putreg32(0, KINETIS_RTC_TAR); /* unset alarm (resets flags) */
+ putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */
+
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_rtc_initialize
+ *
+ * Description:
+ * Initialize the hardware RTC per the selected configuration. This
+ * function is called once during the OS initialization sequence
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_initialize(void)
+{
+ int regval;
+
+ /* Enable RTC module */
+
+ regval = getreg32(KINETIS_SIM_SCGC6);
+ regval |= SIM_SCGC6_RTC;
+ putreg32(regval, KINETIS_SIM_SCGC6);
+
+ /* Disable counters (just in case) */
+
+ putreg32(0, KINETIS_RTC_SR);
+
+ /* Enable oscilator */
+ /* capacitance values from teensyduino */
+
+ putreg32(RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE, KINETIS_RTC_CR);
+
+ /* TODO: delay some time (1024 cycles? would be 30ms) */
+
+ /* Disable interrupts */
+
+ putreg32(0, KINETIS_RTC_IER);
+
+ /* Reset flags requires writing the seconds register, the following line
+ * avoids altering any stored time value.
+ */
+
+ putreg32(getreg32(KINETIS_RTC_TSR), KINETIS_RTC_TSR);
+
+#if defined(CONFIG_RTC_ALARM)
+ /* Enable alarm interrupts. REVISIT: This will not work. up_rtc_initialize()
+ * is called very early in initialization BEFORE the interrupt system will be
+ * enabled. All interrupts will disabled later when the interrupt system is
+ * disabled. This must be done later when the alarm is first set.
+ */
+
+ irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt);
+ up_enable_irq(KINETIS_IRQ_RTC);
+#endif
+
+ /* Enable counters */
+
+ putreg32(RTC_SR_TCE, KINETIS_RTC_SR);
+
+ /* Mark RTC enabled */
+
+ g_rtc_enabled = true;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_rtc_time
+ *
+ * Description:
+ * Get the current time in seconds. This is similar to the standard
+ * time() function. This interface is only required if the low-resolution
+ * RTC/counter hardware implementation selected. It is only used by the
+ * RTOS during initialization to set up the system time when CONFIG_RTC is
+ * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * The current time in seconds
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_RTC_HIRES
+time_t up_rtc_time(void)
+{
+ return getreg32(KINETIS_RTC_TSR);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_rtc_gettime
+ *
+ * Description:
+ * Get the current time from the high resolution RTC clock/counter. This
+ * interface is only supported by the high-resolution RTC/counter hardware
+ * implementation. It is used to replace the system timer.
+ *
+ * Input Parameters:
+ * tp - The location to return the high resolution time value.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_HIRES
+int up_rtc_gettime(FAR struct timespec *tp)
+{
+ irqstate_t flags;
+ uint32_t seconds, prescaler, prescaler2;
+
+ /* Get prescaler and seconds register. this is in a loop which ensures that
+ * registers will be re-read if during the reads the prescaler has
+ * wrapped-around.
+ */
+
+ flags = enter_critical_section();
+ do
+ {
+ prescaler = getreg32(KINETIS_RTC_TPR);
+ seconds = getreg32(KINETIS_RTC_TSR);
+ prescaler2 = getreg32(KINETIS_RTC_TPR);
+ }
+ while (prescaler > prescaler2);
+
+ leave_critical_section(flags);
+
+ /* Build seconds + nanoseconds from seconds and prescaler register */
+
+ tp->tv_sec = seconds;
+ tp->tv_nsec = prescaler * (1000000000 / CONFIG_RTC_FREQUENCY);
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_rtc_settime
+ *
+ * Description:
+ * Set the RTC to the provided time. All RTC implementations must be able
+ * to set their time based on a standard timespec.
+ *
+ * Input Parameters:
+ * tp - the time to use
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_settime(FAR const struct timespec *tp)
+{
+ irqstate_t flags;
+ uint32_t seconds, prescaler;
+
+ seconds = tp->tv_sec;
+ prescaler = tp->tv_nsec * (CONFIG_RTC_FREQUENCY / 1000000000);
+
+ flags = enter_critical_section();
+
+ putreg32(0, KINETIS_RTC_SR); /* Disable counter */
+
+ putreg32(prescaler, KINETIS_RTC_TPR); /* Always write prescaler first */
+ putreg32(seconds, KINETIS_RTC_TSR);
+
+ putreg32(RTC_SR_TCE, KINETIS_RTC_SR); /* Re-enable counter */
+
+ leave_critical_section(flags);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: kinetis_rtc_setalarm
+ *
+ * Description:
+ * Set up an alarm.
+ *
+ * Input Parameters:
+ * tp - the time to set the alarm
+ * callback - the function to call when the alarm expires.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
+{
+ /* Is there already something waiting on the ALARM? */
+
+ if (g_alarmcb == NULL)
+ {
+ /* No.. Save the callback function pointer */
+
+ g_alarmcb = callback;
+
+ /* Enable and set RTC alarm */
+
+ putreg32(tp->tv_sec, KINETIS_RTC_TAR); /* Set alarm (also resets
+ * flags) */
+ putreg32(RTC_IER_TAIE, KINETIS_RTC_IER); /* Enable alarm interrupt */
+
+ return OK;
+ }
+ else
+ {
+ return -EBUSY;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: kinetis_rtc_cancelalarm
+ *
+ * Description:
+ * Cancel a pending alarm alarm
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+int kinetis_rtc_cancelalarm(void)
+{
+ if (g_alarmcb != NULL)
+ {
+ /* Cancel the global callback function */
+
+ g_alarmcb = NULL;
+
+ /* Unset the alarm */
+
+ putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */
+
+ return OK;
+ }
+ else
+ {
+ return -ENODATA;
+ }
+}
+#endif
+
+#endif /* KINETIS_RTC */
diff --git a/arch/arm/src/kl/kl_pwm.h b/arch/arm/src/kl/kl_pwm.h
index f9afbcd7800..5b64e40967b 100644
--- a/arch/arm/src/kl/kl_pwm.h
+++ b/arch/arm/src/kl/kl_pwm.h
@@ -90,13 +90,13 @@
# elif CONFIG_KL_TPM0_CHANNEL == 1
# define PWM_TPM0_PINCFG GPIO_TPM0_CH1OUT
# elif CONFIG_KL_TPM0_CHANNEL == 2
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH2OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH2OUT
# elif CONFIG_KL_TPM0_CHANNEL == 3
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH3OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH3OUT
# elif CONFIG_KL_TPM0_CHANNEL == 4
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH4OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH4OUT
# elif CONFIG_KL_TPM0_CHANNEL == 5
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH5OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH5OUT
# else
# error "Unsupported value of CONFIG_KL_TPM1_CHANNEL"
# endif
diff --git a/arch/arm/src/lpc214x/chip.h b/arch/arm/src/lpc214x/chip.h
index c0af01c4475..1e7c8b219bc 100644
--- a/arch/arm/src/lpc214x/chip.h
+++ b/arch/arm/src/lpc214x/chip.h
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef __LPC214X_CHIP_H
-#define __LPC214X_CHIP_H
+#ifndef __ARCH_ARM_SRC_LPC214X_CHIP_H
+#define __ARCH_ARM_SRC_LPC214X_CHIP_H
/****************************************************************************************************
* Included Files
@@ -346,4 +346,4 @@
* Public Function Prototypes
****************************************************************************************************/
-#endif /* __LPC214X_CHIP_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_CHIP_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_apb.h b/arch/arm/src/lpc214x/lpc214x_apb.h
index e76fa5754a6..93f9ebdf7ae 100644
--- a/arch/arm/src/lpc214x/lpc214x_apb.h
+++ b/arch/arm/src/lpc214x/lpc214x_apb.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_APB_H
-#define _ARCH_ARM_SRC_LPC214X_APB_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
/************************************************************************************
* Included Files
@@ -69,4 +69,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_APB_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_i2c.h b/arch/arm/src/lpc214x/lpc214x_i2c.h
index 35fcc00f7ea..d12f1ff4eec 100644
--- a/arch/arm/src/lpc214x/lpc214x_i2c.h
+++ b/arch/arm/src/lpc214x/lpc214x_i2c.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_I2C_H
-#define _ARCH_ARM_SRC_LPC214X_I2C_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
/************************************************************************************
* Included Files
@@ -138,4 +138,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_I2C_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_pinsel.h b/arch/arm/src/lpc214x/lpc214x_pinsel.h
index 21c6c2f9db5..0cb2c58f9bf 100644
--- a/arch/arm/src/lpc214x/lpc214x_pinsel.h
+++ b/arch/arm/src/lpc214x/lpc214x_pinsel.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_PINSEL_H
-#define _ARCH_ARM_SRC_LPC214X_PINSEL_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
/************************************************************************************
* Included Files
@@ -256,4 +256,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_PINSEL_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_pll.h b/arch/arm/src/lpc214x/lpc214x_pll.h
index 4e19bcdc11c..f8f9a25ad8e 100644
--- a/arch/arm/src/lpc214x/lpc214x_pll.h
+++ b/arch/arm/src/lpc214x/lpc214x_pll.h
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_PLL_H
-#define _ARCH_ARM_SRC_LPC214X_PLL_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
/****************************************************************************************************
* Included Files
@@ -102,4 +102,4 @@
* Public Function Prototypes
****************************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_PLL_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_power.h b/arch/arm/src/lpc214x/lpc214x_power.h
index 699af8d5905..09d89c92cea 100644
--- a/arch/arm/src/lpc214x/lpc214x_power.h
+++ b/arch/arm/src/lpc214x/lpc214x_power.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_POWER_H
-#define _ARCH_ARM_SRC_LPC214X_POWER_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
/************************************************************************************
* Included Files
@@ -87,4 +87,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_POWER_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_spi.h b/arch/arm/src/lpc214x/lpc214x_spi.h
index 97e2fc7a58f..69c94d89c0f 100644
--- a/arch/arm/src/lpc214x/lpc214x_spi.h
+++ b/arch/arm/src/lpc214x/lpc214x_spi.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_SPI_H
-#define _ARCH_ARM_SRC_LPC214X_SPI_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
/************************************************************************************
* Included Files
@@ -181,4 +181,4 @@ struct spi_dev_s; /* Forward reference */
FAR struct spi_dev_s *lpc214x_spibus_initialize(int port);
-#endif /* _ARCH_ARM_SRC_LPC214X_SPI_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_timer.h b/arch/arm/src/lpc214x/lpc214x_timer.h
index 224e608f3e9..df0287d4495 100644
--- a/arch/arm/src/lpc214x/lpc214x_timer.h
+++ b/arch/arm/src/lpc214x/lpc214x_timer.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __LPC214X_TIMER_H
-#define __LPC214X_TIMER_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
/************************************************************************************
* Included Files
@@ -149,4 +149,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __LPC214X_TIMER_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_uart.h b/arch/arm/src/lpc214x/lpc214x_uart.h
index c4c90c16692..3c85c3a065a 100644
--- a/arch/arm/src/lpc214x/lpc214x_uart.h
+++ b/arch/arm/src/lpc214x/lpc214x_uart.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __LPC214X_UART_H
-#define __LPC214X_UART_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
/************************************************************************************
* Included Files
@@ -139,4 +139,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __LPC214X_UART_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_vic.h b/arch/arm/src/lpc214x/lpc214x_vic.h
index 89a5f7b13f8..4f3b821a841 100644
--- a/arch/arm/src/lpc214x/lpc214x_vic.h
+++ b/arch/arm/src/lpc214x/lpc214x_vic.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __LPC214X_VIC_H
-#define __LPC214X_VIC_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
/************************************************************************************
* Included Files
@@ -67,4 +67,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __LPC214X_VIC_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H */
diff --git a/arch/arm/src/lpc2378/chip.h b/arch/arm/src/lpc2378/chip.h
index b8b8b70c85a..1f213eaeabd 100644
--- a/arch/arm/src/lpc2378/chip.h
+++ b/arch/arm/src/lpc2378/chip.h
@@ -38,8 +38,8 @@
*
****************************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC2378_CHIP_H
-#define _ARCH_ARM_SRC_LPC2378_CHIP_H
+#ifndef __ARCH_ARM_SRC_LPC2378_CHIP_H
+#define __ARCH_ARM_SRC_LPC2378_CHIP_H
/****************************************************************************************************
* Included Files
@@ -1003,4 +1003,4 @@ are for LPC24xx only. */
* Public Function Prototypes
****************************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC2378_CHIP_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_CHIP_H */
diff --git a/arch/arm/src/lpc2378/lpc2378.h b/arch/arm/src/lpc2378/lpc2378.h
index 0c7fccede91..1e40b228d0d 100644
--- a/arch/arm/src/lpc2378/lpc2378.h
+++ b/arch/arm/src/lpc2378/lpc2378.h
@@ -38,8 +38,8 @@
*
****************************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC2378_INTERNAL_H
-#define _ARCH_ARM_SRC_LPC2378_INTERNAL_H
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_H
/****************************************************************************************************
* Included Files
@@ -67,4 +67,4 @@ void lpc2378_statledon(void);
#endif
-#endif /* _ARCH_ARM_SRC_LPC2378_INTERNAL_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_H */
diff --git a/arch/arm/src/lpc2378/lpc23xx_gpio.h b/arch/arm/src/lpc2378/lpc23xx_gpio.h
index fc920be4e96..b8be6966095 100644
--- a/arch/arm/src/lpc2378/lpc23xx_gpio.h
+++ b/arch/arm/src/lpc2378/lpc23xx_gpio.h
@@ -38,8 +38,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
-#define _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
/************************************************************************************
* Included Files
@@ -68,4 +68,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
diff --git a/arch/arm/src/lpc2378/lpc23xx_pinsel.h b/arch/arm/src/lpc2378/lpc23xx_pinsel.h
index 69ad1b74904..be34810fdc9 100644
--- a/arch/arm/src/lpc2378/lpc23xx_pinsel.h
+++ b/arch/arm/src/lpc2378/lpc23xx_pinsel.h
@@ -38,8 +38,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC23XX_PINSEL_H
-#define _ARCH_ARM_SRC_LPC23XX_PINSEL_H
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
/************************************************************************************
* Included Files
@@ -789,4 +789,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC23XX_PINSEL_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H */
diff --git a/arch/arm/src/lpc43xx/lpc43_adc.c b/arch/arm/src/lpc43xx/lpc43_adc.c
index 4286451f11e..2a9db4297d9 100644
--- a/arch/arm/src/lpc43xx/lpc43_adc.c
+++ b/arch/arm/src/lpc43xx/lpc43_adc.c
@@ -59,7 +59,6 @@
#include
#include
-#include
#include
#include
#include
@@ -80,6 +79,12 @@
#include "lpc43_pinconfig.h"
+/* board.h should be included last because it depends on the previous
+ * inclusions and may need to modify other definitions.
+ */
+
+#include
+
#if defined(CONFIG_LPC43_ADC0) /* TODO ADC1 */
/****************************************************************************
diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c
index 56e03bbea03..82ec6d690ef 100644
--- a/arch/arm/src/lpc43xx/lpc43_serial.c
+++ b/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -170,7 +170,7 @@ static struct up_dev_s g_uart0priv =
.bits = CONFIG_USART0_BITS,
.stopbits2 = CONFIG_USART0_2STOP,
#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -205,7 +205,7 @@ static struct up_dev_s g_uart1priv =
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
#if defined(CONFIG_UART1_RS485MODE) && defined(CONFIG_UART1_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -240,7 +240,7 @@ static struct up_dev_s g_uart2priv =
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -275,7 +275,7 @@ static struct up_dev_s g_uart3priv =
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index 8e764dff40e..1f1f423e857 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -1060,7 +1060,6 @@ config SAM34_TC5_TIOB
config SAM34_ONESHOT
bool "TC one-shot wrapper"
- depends on SAM34_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs
index 48c751799ce..dab10fb45e1 100644
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@@ -199,7 +199,7 @@ ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
ifeq ($(CONFIG_SAM34_TC),y)
CHIP_CSRCS += sam4cm_tc.c
ifeq ($(CONFIG_SAM34_ONESHOT),y)
-CHIP_CSRCS += sam4cm_oneshot.c
+CHIP_CSRCS += sam4cm_oneshot.c sam4cm_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAM34_FREERUN),y)
CHIP_CSRCS += sam4cm_freerun.c
diff --git a/arch/arm/src/sam34/sam4cm_freerun.c b/arch/arm/src/sam34/sam4cm_freerun.c
index a26578e99ac..4b09e1d5e66 100644
--- a/arch/arm/src/sam34/sam4cm_freerun.c
+++ b/arch/arm/src/sam34/sam4cm_freerun.c
@@ -59,7 +59,7 @@
#include "sam4cm_freerun.h"
-#ifdef CONFIG_SAM34_ONESHOT
+#ifdef CONFIG_SAM34_FREERUN
/****************************************************************************
* Private Functions
@@ -316,4 +316,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
-#endif /* CONFIG_SAM34_ONESHOT */
+#endif /* CONFIG_SAM34_FREERUN */
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c
index a7505b5a72e..0bf92d1fea0 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.c
+++ b/arch/arm/src/sam34/sam4cm_oneshot.c
@@ -111,7 +111,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
+#ifdef CONFIG_SAM34_FREERUN
oneshot->start_count = 0;
+#endif
oneshot_handler(oneshot_arg);
}
@@ -212,7 +214,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
+#ifdef CONFIG_SAM34_FREERUN
oneshot->start_count = 0;
+#endif
+
return OK;
}
@@ -251,8 +256,10 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts)
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@@ -309,6 +316,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
+#ifdef CONFIG_SAM34_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@@ -327,7 +335,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* vanishes at least if compiled with no optimisation.
*/
- oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ if (freerun != NULL)
+ {
+ oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ }
+#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@@ -363,8 +375,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts)
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@@ -405,16 +417,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
+#ifdef CONFIG_SAM34_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
- if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
+ if (count > 0 && freerun != NULL &&
+ sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
+#endif
/* Now we can disable the interrupt and stop the timer. */
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.h b/arch/arm/src/sam34/sam4cm_oneshot.h
index d7dc7a18ee0..d46b67b4211 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.h
+++ b/arch/arm/src/sam34/sam4cm_oneshot.h
@@ -46,7 +46,6 @@
#include
#include "sam4cm_tc.h"
-#include "sam4cm_freerun.h"
#ifdef CONFIG_SAM34_ONESHOT
@@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
+#ifdef CONFIG_SAM34_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
+#endif
};
/****************************************************************************
@@ -130,6 +131,14 @@ extern "C"
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ ****************************************************************************/
+
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
@@ -144,7 +153,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@@ -155,8 +165,11 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@@ -173,7 +186,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@@ -185,8 +199,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
new file mode 100644
index 00000000000..cdab331d93a
--- /dev/null
+++ b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
@@ -0,0 +1,345 @@
+/****************************************************************************
+ * arch/arm/src/sam/sam_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "sam_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct sam_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct sam_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg);
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = sam_max_delay,
+ .start = sam_start,
+ .cancel = sam_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when sam_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * sam_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: sam_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = sam_oneshot_start(&priv->oneshot, NULL,
+ sam_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct sam_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained SAM oneshot timer */
+
+ ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
\ No newline at end of file
diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c
index 89461c58369..5fda366fe00 100644
--- a/arch/arm/src/sam34/sam_gpio.c
+++ b/arch/arm/src/sam34/sam_gpio.c
@@ -54,6 +54,7 @@
#include "chip.h"
#include "sam_gpio.h"
+#include "sam_periphclks.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -96,7 +97,7 @@ static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset)
* Name: sam_gpiopin
*
* Description:
- * Returun the base address of the GPIO register set
+ * Return the base address of the GPIO register set
*
****************************************************************************/
@@ -105,6 +106,67 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
+/****************************************************************************
+ * Name: sam_gpio_enableclk
+ *
+ * Description:
+ * Enable clocking on the PIO port. Port clocking is required in the
+ * following cases:
+ *
+ * - In order to read values in input pins from the port
+ * - If the port supports interrupting pins
+ * - If glitch filtering is enabled
+ * - If necessary to read the input value on an open drain output (this
+ * may be done in TWI logic to detect hangs on the I2C bus).
+ * - If necessary to read the input value on peripheral pins.
+ *
+ ****************************************************************************/
+
+static inline int sam_gpio_enableclk(gpio_pinset_t cfgset)
+{
+ /* Enable the peripheral clock for the GPIO's port controller. */
+
+ switch (cfgset & GPIO_PORT_MASK)
+ {
+ case GPIO_PORT_PIOA:
+ sam_pioa_enableclk();
+ break;
+
+ case GPIO_PORT_PIOB:
+ sam_piob_enableclk();
+ break;
+
+#ifdef GPIO_PORT_PIOC
+ case GPIO_PORT_PIOC:
+ sam_pioc_enableclk();
+ break;
+#endif
+
+#ifdef GPIO_PORT_PIOD
+ case GPIO_PORT_PIOD:
+ sam_piod_enableclk();
+ break;
+#endif
+
+#ifdef GPIO_PORT_PIOE
+ case GPIO_PORT_PIOE:
+ sam_pioe_enableclk();
+ break;
+#endif
+
+#ifdef GPIO_PORT_PIOF
+ case GPIO_PORT_PIOF:
+ sam_piof_enableclk();
+ break;
+#endif
+
+ default:
+ return -EINVAL;
+ }
+
+ return OK;
+}
+
/****************************************************************************
* Name: sam_configinput
*
@@ -171,6 +233,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
{
regval &= ~pin;
}
+
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
@@ -184,7 +247,12 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
* another, new API... perhaps sam_configfilter()
*/
- return OK;
+ /* Enable the peripheral clock for the GPIO's port controller.
+ * A GPIO input value is only sampled if the peripheral clock for its
+ * controller is enabled.
+ */
+
+ return sam_gpio_enableclk(cfgset);
}
/****************************************************************************
diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c
index cf3d70b1613..62075d9a765 100644
--- a/arch/arm/src/sam34/sam_wdt.c
+++ b/arch/arm/src/sam34/sam_wdt.c
@@ -554,7 +554,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval |= WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
- up_enable_irq(STM32_IRQ_WWDG);
+ up_enable_irq(SAM_IRQ_WWDG);
}
else
{
@@ -563,7 +563,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval &= ~WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
- up_disable_irq(STM32_IRQ_WWDG);
+ up_disable_irq(SAM_IRQ_WWDG);
}
leave_critical_section(flags);
diff --git a/arch/arm/src/sam34/sam_wdt.h b/arch/arm/src/sam34/sam_wdt.h
index 234f4e25204..77a1fbab40e 100644
--- a/arch/arm/src/sam34/sam_wdt.h
+++ b/arch/arm/src/sam34/sam_wdt.h
@@ -95,4 +95,4 @@ void sam_wdtinitialize(FAR const char *devpath);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
-#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */
+#endif /* __ARCH_ARM_SRC_SAM34_WDT_H */
diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index 11aa7179f1f..121ee991ecc 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -3866,7 +3866,6 @@ endif # SAMA5_TC2
config SAMA5_ONESHOT
bool "TC one-shot wrapper"
- depends on SAMA5_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs
index cfe0d0a3dea..ff812107305 100644
--- a/arch/arm/src/sama5/Make.defs
+++ b/arch/arm/src/sama5/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# arch/arm/sama5/Make.defs
#
-# Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+# Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -292,7 +292,7 @@ endif
ifeq ($(CONFIG_SAMA5_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMA5_ONESHOT),y)
-CHIP_CSRCS += sam_oneshot.c
+CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAMA5_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
diff --git a/arch/arm/src/sama5/sam_freerun.c b/arch/arm/src/sama5/sam_freerun.c
index 8870988ce60..088cb10a6e8 100644
--- a/arch/arm/src/sama5/sam_freerun.c
+++ b/arch/arm/src/sama5/sam_freerun.c
@@ -60,27 +60,12 @@
#include "sam_freerun.h"
-#ifdef CONFIG_SAMA5_ONESHOT
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifdef CONFIG_SAMA5_FREERUN
/****************************************************************************
* Private Functions
****************************************************************************/
+
/****************************************************************************
* Name: sam_freerun_handler
*
@@ -333,4 +318,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
-#endif /* CONFIG_SAMA5_ONESHOT */
+#endif /* CONFIG_SAMA5_FREERUN */
diff --git a/arch/arm/src/sama5/sam_oneshot.c b/arch/arm/src/sama5/sam_oneshot.c
index 5f011ea2874..b8836069823 100644
--- a/arch/arm/src/sama5/sam_oneshot.c
+++ b/arch/arm/src/sama5/sam_oneshot.c
@@ -63,22 +63,6 @@
#ifdef CONFIG_SAMA5_ONESHOT
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -128,7 +112,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
+#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
+#endif
oneshot_handler(oneshot_arg);
}
@@ -229,7 +215,36 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
+#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Return the maximum delay supported by the one shot timer (in
+ * microseconds).
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * sam_oneshot_initialize();
+ * usec The location in which to return the maximum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
+{
+ DEBUGASSERT(oneshot != NULL && usec != NULL);
+ *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
@@ -253,8 +268,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts)
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@@ -311,6 +328,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
+#ifdef CONFIG_SAMA5_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@@ -329,7 +347,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* vanishes at least if compiled with no optimisation.
*/
- oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ if (freerun != NULL)
+ {
+ oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ }
+#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@@ -365,8 +387,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts)
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@@ -407,16 +429,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
+#ifdef CONFIG_SAMA5_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
- if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
+ if (count > 0 && freerun != NULL &&
+ sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
+#endif
/* Now we can disable the interrupt and stop the timer. */
diff --git a/arch/arm/src/sama5/sam_oneshot.h b/arch/arm/src/sama5/sam_oneshot.h
index 0443fcd693d..15431882fc0 100644
--- a/arch/arm/src/sama5/sam_oneshot.h
+++ b/arch/arm/src/sama5/sam_oneshot.h
@@ -46,7 +46,6 @@
#include
#include "sam_tc.h"
-#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
@@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
+#ifdef CONFIG_SAMA5_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
+#endif
};
/****************************************************************************
@@ -130,6 +131,27 @@ extern "C"
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Return the maximum delay supported by the one shot timer (in
+ * microseconds).
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * sam_oneshot_initialize();
+ * usec The location in which to return the maximum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
+
/****************************************************************************
* Name: sam_oneshot_start
*
@@ -142,7 +164,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@@ -153,8 +176,11 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@@ -171,7 +197,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@@ -183,8 +210,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/src/sama5/sam_oneshot_lowerhalf.c b/arch/arm/src/sama5/sam_oneshot_lowerhalf.c
new file mode 100644
index 00000000000..e9737ea167d
--- /dev/null
+++ b/arch/arm/src/sama5/sam_oneshot_lowerhalf.c
@@ -0,0 +1,347 @@
+/****************************************************************************
+ * arch/arm/src/sam/sam_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "sam_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct sam_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct sam_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg);
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = sam_max_delay,
+ .start = sam_start,
+ .cancel = sam_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when sam_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * sam_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: sam_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = sam_oneshot_start(&priv->oneshot, NULL,
+ sam_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct sam_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained SAM oneshot timer */
+
+ ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig
index 9507e0c59c8..fc4f5135076 100644
--- a/arch/arm/src/samv7/Kconfig
+++ b/arch/arm/src/samv7/Kconfig
@@ -102,7 +102,7 @@ config ARCH_CHIP_SAME70Q
default n
select ARCH_CHIP_SAME70
select SAMV7_HAVE_MCAN1
- select SAMV7_HAVE_DAC1
+ select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_EBI
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SDRAMC
@@ -119,7 +119,7 @@ config ARCH_CHIP_SAME70N
default n
select ARCH_CHIP_SAME70
select SAMV7_HAVE_MCAN1
- select SAMV7_HAVE_DAC1
+ select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SPI0
select SAMV7_HAVE_TWIHS2
@@ -152,7 +152,7 @@ config ARCH_CHIP_SAMV71Q
default n
select ARCH_CHIP_SAMV71
select SAMV7_HAVE_MCAN1
- select SAMV7_HAVE_DAC1
+ select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_EBI
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SDRAMC
@@ -169,7 +169,7 @@ config ARCH_CHIP_SAMV71N
default n
select ARCH_CHIP_SAMV71
select SAMV7_HAVE_MCAN1
- select SAMV7_HAVE_DAC1
+ select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SPI0
select SAMV7_HAVE_TWIHS2
@@ -196,6 +196,10 @@ config SAMV7_HAVE_MCAN1
bool
default n
+config SAMV7_DAC
+ bool
+ default n
+
config SAMV7_HAVE_DAC1
bool
default n
@@ -334,10 +338,12 @@ config SAMV7_MCAN1
config SAMV7_DAC0
bool "Digital To Analog Converter 0 (DAC0)"
default n
+ select SAMV7_DAC
config SAMV7_DAC1
bool "Digital To Analog Converter 1 (DAC1)"
default n
+ select SAMV7_DAC
depends on SAMV7_HAVE_DAC1
config SAMV7_EBI
@@ -1600,7 +1606,6 @@ endif # SAMV7_TC3
config SAMV7_ONESHOT
bool "TC one-shot wrapper"
- depends on SAMV7_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
@@ -1658,6 +1663,62 @@ config SAMV7_TC_REGDEBUG
endmenu # Timer/counter Configuration
endif # SAMV7_HAVE_TC
+menu "DAC device driver configuration"
+ depends on SAMV7_DAC
+
+config SAMV7_DAC_PRESCAL
+ int "DAC MCK prescaler"
+ default 7
+ range 0 15
+ ---help---
+ Define PRESCALER (Peripheral Clock to DAC Clock Ratio)
+
+ 0 -> 2 periods of DAC Clock
+ 1 -> 3 periods of DAC Clock
+ 2 -> 4 periods of DAC Clock
+ 3 -> 5 periods of DAC Clock
+ 4 -> 6 periods of DAC Clock
+ 5 -> 7 periods of DAC Clock
+ 6 -> 8 periods of DAC Clock
+ 7 -> 9 periods of DAC Clock
+ 8 -> 10 periods of DAC Clock
+ 9 -> 11 periods of DAC Clock
+ 10 -> 12 periods of DAC Clock
+ 11 -> 13 periods of DAC Clock
+ 12 -> 14 periods of DAC Clock
+ 13 -> 15 periods of DAC Clock
+ 14 -> 16 periods of DAC Clock
+ 15 -> 17 periods of DAC Clock
+
+config SAMV7_DAC_TRIGGER
+ bool "DAC trigger mode"
+ default n
+ ---help---
+ Enable DAC trigger mode
+
+if SAMV7_DAC_TRIGGER
+
+config SAMV7_DAC_TRIGGER_FREQUENCY
+ int "DAC trigger frequency"
+ default 1000
+ ---help---
+ Define DAC trigger frequency
+
+config SAMV7_DAC_TRIGGER_SELECT
+ int "DAC trigger source"
+ default 3
+ range 1 3
+ ---help---
+ Define DAC trigger source. Snly support for TC0, TC1, TC2 output is
+ currently implemented:
+
+ 1 -> TC0
+ 2 -> TC1
+ 3 -> TC2
+
+endif # SAMV7_DAC_TRIGGER
+endmenu # DAC device driver configuration
+
menu "HSMCI device driver options"
depends on SAMV7_HSMCI
diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs
index fbd88a6e7f4..dfe56491f96 100644
--- a/arch/arm/src/samv7/Make.defs
+++ b/arch/arm/src/samv7/Make.defs
@@ -181,7 +181,7 @@ endif
ifeq ($(CONFIG_SAMV7_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMV7_ONESHOT),y)
-CHIP_CSRCS += sam_oneshot.c
+CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAMV7_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
@@ -214,3 +214,7 @@ endif
ifeq ($(CONFIG_SAMV7_PROGMEM),y)
CHIP_CSRCS += sam_progmem.c
endif
+
+ifeq ($(CONFIG_SAMV7_DAC),y)
+CHIP_CSRCS += sam_dac.c
+endif
diff --git a/arch/arm/src/samv7/chip/sam_dacc.h b/arch/arm/src/samv7/chip/sam_dacc.h
new file mode 100644
index 00000000000..a40b0d09e5a
--- /dev/null
+++ b/arch/arm/src/samv7/chip/sam_dacc.h
@@ -0,0 +1,226 @@
+/****************************************************************************************
+ * arch/arm/src/samv7/chip/sam_dacc.h
+ * Digital-to-Analog Converter Controller (DACC) for the SAMV7
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H
+#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* DACC register offsets *****************************************************************/
+
+#define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */
+#define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */
+#define SAM_DACC_TRIGR_OFFSET 0x0008 /* Trigger Register */
+#define SAM_DACC_CHER_OFFSET 0x0010 /* Channel Enable Register */
+#define SAM_DACC_CHDR_OFFSET 0x0014 /* Channel Disable Register */
+#define SAM_DACC_CHSR_OFFSET 0x0018 /* Channel Status Register */
+#define SAM_DACC_CDR0_OFFSET 0x001c /* Conversion Data Register 0 */
+#define SAM_DACC_CDR1_OFFSET 0x0020 /* Conversion Data Register 1 */
+#define SAM_DACC_IER_OFFSET 0x0024 /* Interrupt Enable Register */
+#define SAM_DACC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
+#define SAM_DACC_IMR_OFFSET 0x002c /* Interrupt Mask Register */
+#define SAM_DACC_ISR_OFFSET 0x0030 /* Interrupt Status Register */
+#define SAM_DACC_ACR_OFFSET 0x0094 /* Analog Current Register */
+#define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */
+#define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */
+
+/* DACC register addresses **************************************************************/
+
+#define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET)
+#define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET)
+#define SAM_DACC_TRIGR (SAM_DACC_BASE+SAM_DACC_TRIGR_OFFSET)
+#define SAM_DACC_CHER (SAM_DACC_BASE+SAM_DACC_CHER_OFFSET)
+#define SAM_DACC_CHDR (SAM_DACC_BASE+SAM_DACC_CHDR_OFFSET)
+#define SAM_DACC_CHSR (SAM_DACC_BASE+SAM_DACC_CHSR_OFFSET)
+#define SAM_DACC_CDR0 (SAM_DACC_BASE+SAM_DACC_CDR0_OFFSET)
+#define SAM_DACC_CDR1 (SAM_DACC_BASE+SAM_DACC_CDR1_OFFSET)
+#define SAM_DACC_IER (SAM_DACC_BASE+SAM_DACC_IER_OFFSET)
+#define SAM_DACC_IDR (SAM_DACC_BASE+SAM_DACC_IDR_OFFSET)
+#define SAM_DACC_IMR (SAM_DACC_BASE+SAM_DACC_IMR_OFFSET)
+#define SAM_DACC_ISR (SAM_DACC_BASE+SAM_DACC_ISR_OFFSET)
+#define SAM_DACC_ACR (SAM_DACC_BASE+SAM_DACC_ACR_OFFSET)
+#define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET)
+#define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET)
+
+/* DACC register bit definitions ********************************************************/
+
+/* Control Register */
+
+#define DACC_CR_SWRST (1 << 0) /* Bit 0: Software reset */
+
+/* Mode Register */
+
+#define DACC_MR_MAXS0 (1 << 0) /* Max Speed Mode for Channel 0 */
+# define DACC_MR_MAXS0_TRIG_EVENT (0 << 0) /* External trigger mode or Free-running mode enabled */
+# define DACC_MR_MAXS0_MAXIMUM (1 << 0) /* Max speed mode enabled */
+#define DACC_MR_MAXS1 (1 << 1) /* Max Speed Mode for Channel 1 */
+# define DACC_MR_MAXS1_TRIG_EVENT (0 << 1) /* External trigger mode or Free-running mode enabled */
+# define DACC_MR_MAXS1_MAXIMUM (1 << 1) /* Max speed mode enabled */
+#define DACC_MR_WORD (1 << 4) /* Word Transfer Mode */
+# define DACC_MR_WORD_DISABLED (0 << 4) /* One data to convert is written to the FIFO per access to DACC */
+# define DACC_MR_WORD_ENABLED (1 << 4) /* Two data to convert are written to the FIFO per access to DACC */
+#define DACC_MR_ZERO (1 << 5) /* Must always be written to 0 */
+#define DACC_MR_DIFF (1 << 23) /* Differential Mode */
+# define DACC_MR_DIFF_DISABLED (0 << 23) /* DAC0 and DAC1 are single-ended outputs */
+# define DACC_MR_DIFF_ENABLED (1 << 23) /* DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */
+#define DACC_MR_PRESCALER_SHIFT (24)
+#define DACC_MR_PRESCALER_MASK (0xfu << DACC_MR_PRESCALER_SHIFT) /* Peripheral Clock to DAC Clock Ratio */
+#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_MASK & ((value) << DACC_MR_PRESCALER_SHIFT)))
+# define DACC_MR_PRESCALER_2 (0 << DACC_MR_PRESCALER_SHIFT) /* 2 periods of DAC Clock */
+# define DACC_MR_PRESCALER_3 (1 << DACC_MR_PRESCALER_SHIFT) /* 3 periods of DAC Clock */
+# define DACC_MR_PRESCALER_4 (2 << DACC_MR_PRESCALER_SHIFT) /* 4 periods of DAC Clock */
+# define DACC_MR_PRESCALER_5 (3 << DACC_MR_PRESCALER_SHIFT) /* 5 periods of DAC Clock */
+# define DACC_MR_PRESCALER_6 (4 << DACC_MR_PRESCALER_SHIFT) /* 6 periods of DAC Clock */
+# define DACC_MR_PRESCALER_7 (5 << DACC_MR_PRESCALER_SHIFT) /* 7 periods of DAC Clock */
+# define DACC_MR_PRESCALER_8 (6 << DACC_MR_PRESCALER_SHIFT) /* 8 periods of DAC Clock */
+# define DACC_MR_PRESCALER_9 (7 << DACC_MR_PRESCALER_SHIFT) /* 9 periods of DAC Clock */
+# define DACC_MR_PRESCALER_10 (8 << DACC_MR_PRESCALER_SHIFT) /* 10 periods of DAC Clock */
+# define DACC_MR_PRESCALER_11 (9 << DACC_MR_PRESCALER_SHIFT) /* 11 periods of DAC Clock */
+# define DACC_MR_PRESCALER_12 (10 << DACC_MR_PRESCALER_SHIFT) /* 12 periods of DAC Clock */
+# define DACC_MR_PRESCALER_13 (11 << DACC_MR_PRESCALER_SHIFT) /* 13 periods of DAC Clock */
+# define DACC_MR_PRESCALER_14 (12 << DACC_MR_PRESCALER_SHIFT) /* 14 periods of DAC Clock */
+# define DACC_MR_PRESCALER_15 (13 << DACC_MR_PRESCALER_SHIFT) /* 15 periods of DAC Clock */
+# define DACC_MR_PRESCALER_16 (14 << DACC_MR_PRESCALER_SHIFT) /* 16 periods of DAC Clock */
+# define DACC_MR_PRESCALER_17 (15 << DACC_MR_PRESCALER_SHIFT) /* 17 periods of DAC Clock */
+
+/* Trigger Register */
+
+#define DACC_TRIGR_TRGEN0 (1 << 0) /* Trigger Enable of Channel 0 */
+# define DACC_TRIGR_TRGEN0_DIS (0 << 0) /* External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
+# define DACC_TRIGR_TRGEN0_EN (1 << 0) /* External trigger mode enabled. */
+#define DACC_TRIGR_TRGEN1 (1 << 1) /* Trigger Enable of Channel 1 */
+# define DACC_TRIGR_TRGEN1_DIS (0 << 1) /* External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
+# define DACC_TRIGR_TRGEN1_EN (1 << 1) /* External trigger mode enabled. */
+#define DACC_TRIGR_TRGSEL0_SHIFT (4)
+#define DACC_TRIGR_TRGSEL0_MASK (0x7u << DACC_TRIGR_TRGSEL0_SHIFT) /* Trigger Selection of Channel 0 */
+#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_MASK & ((value) << DACC_TRIGR_TRGSEL0_SHIFT)))
+# define DACC_TRIGR_TRGSEL0_DATRG (0 << 4) /* DATRG output */
+# define DACC_TRIGR_TRGSEL0_TC0 (1 << 4) /* TC0 output */
+# define DACC_TRIGR_TRGSEL0_TC1 (2 << 4) /* TC1 output */
+# define DACC_TRIGR_TRGSEL0_TC2 (3 << 4) /* TC2 output */
+# define DACC_TRIGR_TRGSEL0_PWM0EV0 (4 << 4) /* PWM0 event 0 */
+# define DACC_TRIGR_TRGSEL0_PWM0EV1 (5 << 4) /* PWM0 event 1 */
+# define DACC_TRIGR_TRGSEL0_PWM1EV0 (6 << 4) /* PWM1 event 0 */
+# define DACC_TRIGR_TRGSEL0_PWM1EV1 (7 << 4) /* PWM1 event 1 */
+#define DACC_TRIGR_TRGSEL1_SHIFT (8)
+#define DACC_TRIGR_TRGSEL1_MASK (0x7u << DACC_TRIGR_TRGSEL1_SHIFT) /* Trigger Selection of Channel 1 */
+#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_MASK & ((value) << DACC_TRIGR_TRGSEL1_SHIFT)))
+# define DACC_TRIGR_TRGSEL1_DATRG (0 << 8) /* DATRG output */
+# define DACC_TRIGR_TRGSEL1_TC0 (1 << 8) /* TC0 output */
+# define DACC_TRIGR_TRGSEL1_TC1 (2 << 8) /* TC1 output */
+# define DACC_TRIGR_TRGSEL1_TC2 (3 << 8) /* TC2 output */
+# define DACC_TRIGR_TRGSEL1_PWM0EV0 (4 << 8) /* PWM0 event 0 */
+# define DACC_TRIGR_TRGSEL1_PWM0EV1 (5 << 8) /* PWM0 event 1 */
+# define DACC_TRIGR_TRGSEL1_PWM1EV0 (6 << 8) /* PWM1 event 0 */
+# define DACC_TRIGR_TRGSEL1_PWM1EV1 (7 << 8) /* PWM1 event 1 */
+#define DACC_TRIGR_OSR0_SHIFT (16)
+#define DACC_TRIGR_OSR0_MASK (0x7u << DACC_TRIGR_OSR0_SHIFT) /* Over Sampling Ratio of Channel 0 */
+#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_MASK & ((value) << DACC_TRIGR_OSR0_SHIFT)))
+# define DACC_TRIGR_OSR0_OSR_1 (0 << 16) /* OSR = 1 */
+# define DACC_TRIGR_OSR0_OSR_2 (1 << 16) /* OSR = 2 */
+# define DACC_TRIGR_OSR0_OSR_4 (2 << 16) /* OSR = 4 */
+# define DACC_TRIGR_OSR0_OSR_8 (3 << 16) /* OSR = 8 */
+# define DACC_TRIGR_OSR0_OSR_16 (4 << 16) /* OSR = 16 */
+# define DACC_TRIGR_OSR0_OSR_32 (5 << 16) /* OSR = 32 */
+#define DACC_TRIGR_OSR1_SHIFT (20)
+#define DACC_TRIGR_OSR1_MASK (0x7u << DACC_TRIGR_OSR1_SHIFT) /* Over Sampling Ratio of Channel 1 */
+#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_MASK & ((value) << DACC_TRIGR_OSR1_SHIFT)))
+# define DACC_TRIGR_OSR1_OSR_1 (0 << 20) /* OSR = 1 */
+# define DACC_TRIGR_OSR1_OSR_2 (1 << 20) /* OSR = 2 */
+# define DACC_TRIGR_OSR1_OSR_4 (2 << 20) /* OSR = 4 */
+# define DACC_TRIGR_OSR1_OSR_8 (3 << 20) /* OSR = 8 */
+# define DACC_TRIGR_OSR1_OSR_16 (4 << 20) /* OSR = 16 */
+# define DACC_TRIGR_OSR1_OSR_32 (5 << 20) /* OSR = 32 */
+
+/* Channel Enable, Channel Disable, and Channel Status Registers */
+
+#define DACC_CH0 (1 << 0) /* Channel 0 */
+#define DACC_CH1 (1 << 1) /* Channel 1 */
+#define DACC_CHSR_DACRDY0 (1 << 8) /* DAC Ready Flag */
+#define DACC_CHSR_DACRDY1 (1 << 9) /* DAC Ready Flag */
+
+/* Conversion Data Register -- 32-bit data */
+
+#define DACC_CDR_DATA0_SHIFT (0)
+#define DACC_CDR_DATA0_MASK (0xffffu << DACC_CDR_DATA0_SHIFT) /* Data to Convert for channel 0 */
+#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_MASK & ((value) << DACC_CDR_DATA0_SHIFT)))
+#define DACC_CDR_DATA1_SHIFT (16)
+#define DACC_CDR_DATA1_MASK (0xffffu << DACC_CDR_DATA1_SHIFT) /* Data to Convert for channel 1 */
+#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_MASK & ((value) << DACC_CDR_DATA1_SHIFT)))
+
+/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
+
+#define DACC_INT_TXRDY0 (1 << 0) /* Transmit Ready Interrupt of channel 0 */
+#define DACC_INT_TXRDY1 (1 << 1) /* Transmit Ready Interrupt of channel 1 */
+#define DACC_INT_EOC0 (1 << 4) /* End of Conversion Interrupt of channel 0 */
+#define DACC_INT_EOC1 (1 << 5) /* End of Conversion Interrupt of channel 1 */
+#define DACC_INT_ALL (0xffffffffu) /* All interrupts */
+
+/* Analog Current Register */
+
+#define DACC_ACR_IBCTLCH0_SHIFT (0)
+#define DACC_ACR_IBCTLCH0_MASK (0x3u << DACC_ACR_IBCTLCH0_SHIFT) /* Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_MASK & ((value) << DACC_ACR_IBCTLCH0_SHIFT)))
+#define DACC_ACR_IBCTLCH1_SHIFT (2)
+#define DACC_ACR_IBCTLCH1_MASK (0x3u << DACC_ACR_IBCTLCH1_SHIFT) /* Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_MASK & ((value) << DACC_ACR_IBCTLCH1_SHIFT)))
+
+/* Write Protect Mode register */
+
+#define DACC_WPMR_WPEN (1 << 0) /* Write Protection Enable */
+#define DACC_WPMR_WPKEY_SHIFT (8)
+#define DACC_WPMR_WPKEY_MASK (0xffffffu << DACC_WPMR_WPKEY_SHIFT) /* Write Protect Key */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_MASK & ((value) << DACC_WPMR_WPKEY_SHIFT)))
+# define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /* Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0. */
+
+/* Write Protect Status register */
+
+#define DACC_WPSR_WPVS (1 << 0) /* Write Protection Violation Status */
+#define DACC_WPSR_WPVSRC_SHIFT (8)
+#define DACC_WPSR_WPVSRC_MASK (0xffu << DACC_WPSR_WPVSRC_SHIFT) /* Write Protection Violation Source */
+
+#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H */
diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c
new file mode 100644
index 00000000000..598201ce390
--- /dev/null
+++ b/arch/arm/src/samv7/sam_dac.c
@@ -0,0 +1,658 @@
+/************************************************************************************
+ * arch/arm/src/samv7/sam_dac.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+#include "up_internal.h"
+#include "up_arch.h"
+#include "cache.h"
+
+#include "chip/sam_dacc.h"
+#include "chip/sam_pmc.h"
+#include "chip/sam_pinmap.h"
+
+#include "sam_gpio.h"
+#include "sam_xdmac.h"
+#include "sam_periphclks.h"
+#include "sam_tc.h"
+#include "sam_dac.h"
+
+#if defined(CONFIG_SAMV7_DAC0) || defined(CONFIG_SAMV7_DAC1)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Get TC channel number from Trigger Selection value */
+
+#define SAMV7_DAC_TC_CHANNEL (CONFIG_SAMV7_DAC_TRIGGER_SELECT - 1)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure represents the internal state of a single SAMV7 DAC module */
+
+struct sam_dac_s
+{
+ uint8_t initialized : 1; /* True, the DAC block has been initialized */
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+ TC_HANDLE tc; /* Timer handle */
+#endif
+};
+
+/* This structure represents the internal state of one SAMV7 DAC channel */
+
+struct sam_chan_s
+{
+ uint8_t inuse : 1; /* True, the driver is in use and not available */
+ uint8_t intf; /* DAC zero-based interface number (0 or 1) */
+ uint32_t dro; /* Conversion Data Register */
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+ uint32_t reg_dacc_trigr_clear; /* channel DACC_TRIGR register clear bits */
+ uint32_t reg_dacc_trigr_set; /* channel DACC_TRIGR register set bits */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Interrupt handler */
+
+static int dac_interrupt(int irq, FAR void *context);
+
+/* DAC methods */
+
+static void dac_reset(FAR struct dac_dev_s *dev);
+static int dac_setup(FAR struct dac_dev_s *dev);
+static void dac_shutdown(FAR struct dac_dev_s *dev);
+static void dac_txint(FAR struct dac_dev_s *dev, bool enable);
+static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg);
+static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
+
+/* Initialization */
+
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required,
+ int channel);
+static void dac_timer_free(struct sam_dac_s *priv);
+#endif
+static int dac_channel_init(FAR struct sam_chan_s *chan);
+static int dac_module_init(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct dac_ops_s g_dacops =
+{
+ .ao_reset = dac_reset,
+ .ao_setup = dac_setup,
+ .ao_shutdown = dac_shutdown,
+ .ao_txint = dac_txint,
+ .ao_send = dac_send,
+ .ao_ioctl = dac_ioctl,
+};
+
+#ifdef CONFIG_SAMV7_DAC0
+static struct sam_chan_s g_dac1priv =
+{
+ .intf = 0,
+ .dro = SAM_DACC_CDR0,
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+ .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL0_MASK,
+ .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL0(CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN0,
+#endif
+};
+
+static struct dac_dev_s g_dac1dev =
+{
+ .ad_ops = &g_dacops,
+ .ad_priv = &g_dac1priv,
+};
+#endif
+
+#ifdef CONFIG_SAMV7_DAC1
+static struct sam_chan_s g_dac2priv =
+{
+ .intf = 1,
+ .dro = SAM_DACC_CDR1,
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+ .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL1_MASK,
+ .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL1(CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN1,
+#endif
+};
+
+static struct dac_dev_s g_dac2dev =
+{
+ .ad_ops = &g_dacops,
+ .ad_priv = &g_dac2priv,
+};
+#endif
+
+static struct sam_dac_s g_dacmodule;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dac_interrupt
+ *
+ * Description:
+ * DAC interrupt handler.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * OK
+ *
+ ****************************************************************************/
+
+static int dac_interrupt(int irq, FAR void *context)
+{
+#ifdef CONFIG_SAMV7_DAC1
+ uint32_t status;
+
+ status = getreg32(SAM_DACC_ISR) & getreg32(SAM_DACC_IMR);
+ if (status & DACC_INT_TXRDY1)
+ {
+ dac_txdone(&g_dac2dev);
+ }
+
+ if (status & DACC_INT_TXRDY0)
+#endif
+ {
+ dac_txdone(&g_dac1dev);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: dac_reset
+ *
+ * Description:
+ * Reset the DAC channel. Called early to initialize the hardware. This
+ * is called, before dac_setup() and on error conditions.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void dac_reset(FAR struct dac_dev_s *dev)
+{
+ irqstate_t flags;
+
+ /* Reset only the selected DAC channel; the other DAC channel must remain
+ * functional.
+ */
+
+ flags = enter_critical_section();
+
+#warning "Missing logic"
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: dac_setup
+ *
+ * Description:
+ * Configure the DAC. This method is called the first time that the DAC
+ * device is opened. This will occur when the port is first opened.
+ * This setup includes configuring and attaching DAC interrupts. Interrupts
+ * are all disabled upon return.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int dac_setup(FAR struct dac_dev_s *dev)
+{
+#warning "Missing logic"
+ return OK;
+}
+
+/****************************************************************************
+ * Name: dac_shutdown
+ *
+ * Description:
+ * Disable the DAC. This method is called when the DAC device is closed.
+ * This method reverses the operation the setup method.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void dac_shutdown(FAR struct dac_dev_s *dev)
+{
+#warning "Missing logic"
+}
+
+/****************************************************************************
+ * Name: dac_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void dac_txint(FAR struct dac_dev_s *dev, bool enable)
+{
+ FAR struct sam_chan_s *chan;
+
+ chan = dev->ad_priv;
+ if (enable)
+ {
+ putreg32(DACC_INT_TXRDY0 << chan->intf, SAM_DACC_IER);
+ }
+ else
+ {
+ putreg32(DACC_INT_TXRDY0 << chan->intf, SAM_DACC_IDR);
+ }
+}
+
+/****************************************************************************
+ * Name: dac_send
+ *
+ * Description:
+ * Set the DAC output.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
+{
+ FAR struct sam_chan_s *chan = dev->ad_priv;
+
+ /* Interrupt based transfer */
+
+ putreg16(msg->am_data >> 16, chan->dro);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: dac_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
+{
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: dac_timer_init
+ *
+ * Description:
+ * Configure a timer to periodically trigger conversion. Only channels TC0,
+ * TC1, TC2 can be used with DAC.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required,
+ int channel)
+{
+ uint32_t mode;
+ uint32_t regval;
+ uint32_t freq_actual;
+
+ ainfo("required frequency=%ld [Hz], channel=%d\n",
+ (long)freq_required, channel);
+
+ DEBUGASSERT(priv && (freq_required > 0) && (channel >= 0 && channel <= 2));
+
+ /* Set the timer/counter waveform mode the the clock input. Use smallest
+ * MCK divisor of 8 to have highest clock resolution thus smallest frequency
+ * error. With 32 bit counter the lowest possible frequency of 1 Hz is easily
+ * supported.
+ */
+
+ /* TODO Add support for TC_CMR_TCCLKS_PCK6 to reduce frequency error */
+
+ mode = (TC_CMR_TCCLKS_MCK8 | /* Use MCK/8 clock signal */
+ TC_CMR_WAVSEL_UPRC | /* UP mode w/ trigger on RC Compare */
+ TC_CMR_WAVE | /* Wave mode */
+ TC_CMR_ACPA_CLEAR | /* RA Compare Effect on TIOA: Clear */
+ TC_CMR_ACPC_SET); /* RC Compare Effect on TIOA: Set */
+
+ /* Now allocate and configure the channel */
+
+ priv->tc = sam_tc_allocate(channel, mode);
+ if (!priv->tc)
+ {
+ aerr("ERROR: Failed to allocate channel %d mode %08x\n", channel, mode);
+ return -EINVAL;
+ }
+
+ /* Calculate the actual counter value from this divider and the tc input
+ * frequency.
+ */
+
+ regval = BOARD_MCK_FREQUENCY / 8 / freq_required;
+ DEBUGASSERT(regval > 0); /* Will check for integer underflow */
+
+ /* Set up TC_RA and TC_RC. The frequency is determined by RA and RC:
+ * TIOA is cleared on RA match; TIOA is set on RC match.
+ */
+
+ sam_tc_setregister(priv->tc, TC_REGA, regval >> 1);
+ sam_tc_setregister(priv->tc, TC_REGC, regval);
+
+ freq_actual = BOARD_MCK_FREQUENCY / 8 / regval;
+ ainfo("configured frequency=%ld [Hz]\n", (long)freq_actual);
+
+ /* And start the timer */
+
+ sam_tc_start(priv->tc);
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: dac_timer_free
+ *
+ * Description:
+ * Free the timer resource
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+static void dac_timer_free(struct sam_dac_s *priv)
+{
+ /* Is a timer allocated? */
+
+ ainfo("tc=%p\n", priv->tc);
+
+ if (priv->tc)
+ {
+ /* Yes.. stop it and free it */
+
+ sam_tc_stop(priv->tc);
+ sam_tc_free(priv->tc);
+ priv->tc = NULL;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: dac_channel_init
+ *
+ * Description:
+ * Initialize the DAC channel.
+ *
+ * Input Parameters:
+ * chan - A reference to the DAC channel state data
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int dac_channel_init(FAR struct sam_chan_s *chan)
+{
+ /* Is the selected channel already in-use? */
+
+ if (chan->inuse)
+ {
+ /* Yes.. then return EBUSY */
+
+ return -EBUSY;
+ }
+
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+ /* Configure trigger mode operation */
+
+ ainfo("Enabled trigger mode for DAC%d\n", chan->intf);
+
+ modifyreg32(SAM_DACC_TRIGR,
+ chan->reg_dacc_trigr_clear,
+ chan->reg_dacc_trigr_set);
+#endif
+
+ /* Enable DAC Channel */
+
+ putreg32(1 << chan->intf, SAM_DACC_CHER);
+
+ /* Mark the DAC channel "in-use" */
+
+ chan->inuse = 1;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: dac_module_init
+ *
+ * Description:
+ * Initialize the DAC. All ioctl calls will be routed through this method.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int dac_module_init(void)
+{
+ uint32_t regval;
+ int ret;
+
+ /* Has the DAC block already been initialized? */
+
+ if (g_dacmodule.initialized)
+ {
+ /* Yes.. then return success We only have to do this once */
+
+ return OK;
+ }
+
+ ainfo("Initializing...\n");
+
+ /* Disable DAC peripheral clock */
+
+ sam_dacc_disableclk();
+
+ /* Configure DAC pins */
+
+#ifdef CONFIG_SAMV7_DAC0
+ sam_configgpio(GPIO_DAC0);
+#endif
+#ifdef CONFIG_SAMV7_DAC1
+ sam_configgpio(GPIO_DAC1);
+#endif
+
+ /* Enable the DAC peripheral clock */
+
+ sam_dacc_enableclk();
+
+ /* Reset the DAC controller */
+
+ putreg32(DACC_CR_SWRST, SAM_DACC_CR);
+
+ /* Set the MCK clock prescaler: PRESCAL = (MCK / DACClock) - 2 */
+
+ regval = DACC_MR_PRESCALER(CONFIG_SAMV7_DAC_PRESCAL);
+ putreg32(regval, SAM_DACC_MR);
+
+ /* Configure trigger mode operation */
+
+#ifdef CONFIG_SAMV7_DAC_TRIGGER
+ ret = dac_timer_init(&g_dacmodule,
+ CONFIG_SAMV7_DAC_TRIGGER_FREQUENCY,
+ SAMV7_DAC_TC_CHANNEL);
+ if (ret < 0)
+ {
+ aerr("ERROR: Failed to initialize the timer: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ /* Configure interrupts */
+
+ ret = irq_attach(SAM_IRQ_DACC, dac_interrupt);
+ if (ret < 0)
+ {
+ aerr("irq_attach failed: %d\n", ret);
+ return ret;
+ }
+
+ ainfo("Enable the DAC interrupt: irq=%d\n", SAM_IRQ_DACC);
+ up_enable_irq(SAM_IRQ_DACC);
+
+ /* Mark the DAC module as initialized */
+
+ g_dacmodule.initialized = 1;
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_dac_initialize
+ *
+ * Description:
+ * Initialize the DAC.
+ *
+ * Input Parameters:
+ * intf - The DAC interface number.
+ *
+ * Returned Value:
+ * Valid DAC device structure reference on success, NULL on failure.
+ *
+ ****************************************************************************/
+
+FAR struct dac_dev_s *sam_dac_initialize(int intf)
+{
+ FAR struct dac_dev_s *dev;
+ FAR struct sam_chan_s *chan;
+ int ret;
+
+#ifdef CONFIG_SAMV7_DAC0
+ if (intf == 0)
+ {
+ ainfo("DAC1 Selected\n");
+ dev = &g_dac1dev;
+ }
+ else
+#endif
+#ifdef CONFIG_SAMV7_DAC1
+ if (intf == 1)
+ {
+ ainfo("DAC2 Selected\n");
+ dev = &g_dac2dev;
+ }
+ else
+#endif
+ {
+ aerr("ERROR: No such DAC interface: %d\n", intf);
+ errno = ENODEV;
+ return NULL;
+ }
+
+ /* Initialize the DAC peripheral module */
+
+ ret = dac_module_init();
+ if (ret < 0)
+ {
+ aerr("ERROR: Failed to initialize the DAC peripheral module: %d\n", ret);
+ errno = -ret;
+ return NULL;
+ }
+
+ /* Configure the selected DAC channel */
+
+ chan = dev->ad_priv;
+ ret = dac_channel_init(chan);
+ if (ret < 0)
+ {
+ aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret);
+ errno = -ret;
+ return NULL;
+ }
+
+ return dev;
+}
+
+#endif /* CONFIG_SAMV7_DAC0 || CONFIG_SAMV7_DAC1 */
diff --git a/arch/arm/src/samv7/sam_dac.h b/arch/arm/src/samv7/sam_dac.h
new file mode 100644
index 00000000000..616d25b486c
--- /dev/null
+++ b/arch/arm/src/samv7/sam_dac.h
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/arm/src/samv7/sam_dac.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_SAM_DAC_H
+#define __ARCH_ARM_SRC_SAMV7_SAM_DAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include "chip/sam_dacc.h"
+
+#if defined(CONFIG_SAMV7_DAC0) || defined(CONFIG_SAMV7_DAC1)
+
+/****************************************************************************
+ * Pre-processor definitions
+ ****************************************************************************/
+/* Default configuration settings may be overridden in the board configuration
+ * file.
+ */
+
+#if !defined(CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE)
+# define CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE 8
+#elif CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE > 65535
+# warning "CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE value does not fit into uint16_t, limiting it to 65535"
+# undef CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE
+# define CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE (65535)
+#endif
+
+#if !defined(CONFIG_SAMV7_DAC_TRIGGER_FREQUENCY)
+# define CONFIG_SAMV7_DAC_TRIGGER_FREQUENCY 8000
+#endif
+
+/* PRESCAL = (MCK / DACClock) - 2
+ *
+ * Given:
+ * MCK = 150MHz
+ * DACClock = 16MHz
+ * Then:
+ * PRESCAL = 7
+ */
+
+#if !defined(CONFIG_SAMV7_DAC_PRESCAL)
+#define CONFIG_SAMV7_DAC_PRESCAL (7)
+#elif CONFIG_SAMV7_DAC_PRESCAL > 15
+# warning "Maximum valid CONFIG_SAMV7_DAC_PRESCAL value is 15"
+#endif
+
+#if !defined(CONFIG_SAMV7_DAC_TRIGGER_SELECT)
+#define CONFIG_SAMV7_DAC_TRIGGER_SELECT (3)
+#elif CONFIG_SAMV7_DAC_TRIGGER_SELECT < 1 || CONFIG_SAMV7_DAC_TRIGGER_SELECT > 3
+# warning "Only CONFIG_SAMV7_DAC_TRIGGER_SELECT == [1-3] is supported"
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: sam_dac_initialize
+ *
+ * Description:
+ * Initialize the DAC
+ *
+ * Input Parameters:
+ * intf - The DAC interface number.
+ *
+ * Returned Value:
+ * Valid DAC device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct dac_dev_s;
+FAR struct dac_dev_s *sam_dac_initialize(int intf);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CONFIG_SAMV7_DAC0 || CONFIG_SAMV7_DAC1 */
+#endif /* __ARCH_ARM_SRC_SAMV7_SAM_DAC_H */
diff --git a/arch/arm/src/samv7/sam_freerun.c b/arch/arm/src/samv7/sam_freerun.c
index b3fbfbf6dfc..4db95112182 100644
--- a/arch/arm/src/samv7/sam_freerun.c
+++ b/arch/arm/src/samv7/sam_freerun.c
@@ -61,7 +61,7 @@
#include "sam_freerun.h"
-#ifdef CONFIG_SAMV7_ONESHOT
+#ifdef CONFIG_SAMV7_FREERUN
/****************************************************************************
* Private Functions
@@ -319,4 +319,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
-#endif /* CONFIG_SAMV7_ONESHOT */
+#endif /* CONFIG_SAMV7_FREERUN */
diff --git a/arch/arm/src/samv7/sam_oneshot.c b/arch/arm/src/samv7/sam_oneshot.c
index 4ee2467a61e..9a20ec17a76 100644
--- a/arch/arm/src/samv7/sam_oneshot.c
+++ b/arch/arm/src/samv7/sam_oneshot.c
@@ -64,22 +64,6 @@
#ifdef CONFIG_SAMV7_ONESHOT
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -129,7 +113,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
+#ifdef CONFIG_SAMV7_FREERUN
oneshot->start_count = 0;
+#endif
oneshot_handler(oneshot_arg);
}
@@ -230,7 +216,36 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
+#ifdef CONFIG_SAMV7_FREERUN
oneshot->start_count = 0;
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Return the maximum delay supported by the one shot timer (in
+ * microseconds).
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * sam_oneshot_initialize();
+ * usec The location in which to return the maximum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
+{
+ DEBUGASSERT(oneshot != NULL && usec != NULL);
+ *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
@@ -254,8 +269,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts)
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@@ -285,7 +302,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
- /* Get the timer counter frequency and determine the number of counts need to achieve the requested delay.
+ /* Get the timer counter frequency and determine the number of counts
+ * needed to achieve the requested delay.
*
* frequency = ticks / second
* ticks = seconds * frequency
@@ -312,6 +330,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
+#ifdef CONFIG_SAMV7_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@@ -325,12 +344,16 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* the counter value of the freerun timer/counter is stored at each start
* of the oneshot timer/counter.
*
- * The function up_timer_gettime() could also be used for this but it takes
- * too long. If up_timer_gettime() is called within this function the problem
- * vanishes at least if compiled with no optimisation.
+ * The function up_timer_gettime() could also be used for this but it
+ * takes too long. If up_timer_gettime() is called within this function
+ * the problem vanishes at least if compiled with no optimisation.
*/
- oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ if (freerun != NULL)
+ {
+ oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ }
+#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@@ -347,8 +370,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
- * NOTE: This function may execute at a high rate with no timer running (as
- * when pre-emption is enabled and disabled).
+ * NOTE: This function may execute at a high rate with no timer running
+ * (as when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
@@ -366,8 +389,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts)
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@@ -408,16 +431,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
+#ifdef CONFIG_SAMV7_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
- if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
+ if (count > 0 && freerun != NULL &&
+ sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
+#endif
/* Now we can disable the interrupt and stop the timer. */
@@ -491,32 +517,4 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
return OK;
}
-/****************************************************************************
- * Name: sam_oneshot_max_delay
- *
- * Description:
- * Return the maximum delay supported by the one shot timer (in
- * microseconds).
- *
- * Input Parameters:
- * oneshot Caller allocated instance of the oneshot state structure. This
- * structure must have been previously initialized via a call to
- * sam_oneshot_initialize();
- * usec The location in which to return the maximum delay.
- *
- * Returned Value:
- * Zero (OK) is returned on success; a negated errno value is returned
- * on failure.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
-int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
-{
- DEBUGASSERT(oneshot && usec);
- *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
- return OK;
-}
-#endif
-
#endif /* CONFIG_SAMV7_ONESHOT */
diff --git a/arch/arm/src/samv7/sam_oneshot.h b/arch/arm/src/samv7/sam_oneshot.h
index 6c4e42337f1..276698c7dda 100644
--- a/arch/arm/src/samv7/sam_oneshot.h
+++ b/arch/arm/src/samv7/sam_oneshot.h
@@ -46,7 +46,6 @@
#include
#include "sam_tc.h"
-#include "sam_freerun.h"
#ifdef CONFIG_SAMV7_ONESHOT
@@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
+#ifdef CONFIG_SAMV7_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
+#endif
};
/****************************************************************************
@@ -149,9 +150,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
-#endif
/****************************************************************************
* Name: sam_oneshot_start
@@ -165,7 +164,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@@ -176,8 +176,11 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@@ -194,7 +197,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@@ -206,8 +210,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/src/samv7/sam_oneshot_lowerhalf.c b/arch/arm/src/samv7/sam_oneshot_lowerhalf.c
new file mode 100644
index 00000000000..e6154850eb3
--- /dev/null
+++ b/arch/arm/src/samv7/sam_oneshot_lowerhalf.c
@@ -0,0 +1,345 @@
+/****************************************************************************
+ * arch/arm/src/sam/sam_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "sam_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct sam_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct sam_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct sam_oneshot_s oneshot; /* SAMV7-specific oneshot state */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg);
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = sam_max_delay,
+ .start = sam_start,
+ .cancel = sam_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when sam_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * sam_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: sam_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = sam_oneshot_start(&priv->oneshot, NULL,
+ sam_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct sam_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained SAM oneshot timer */
+
+ ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
\ No newline at end of file
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index df176330991..06c18b70f13 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -1221,6 +1221,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
{
+#ifdef CONFIG_SPI_CS_CONTROL
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
uint32_t regval;
@@ -1280,7 +1281,10 @@ static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
spi->escape_lastxfer = false;
}
- return 0;
+ return ((features & ~HWFEAT_FORCE_CS_CONTROL_MASK) == 0) ? OK : -ENOSYS;
+#else
+ return -ENOSYS;
+#endif
}
#endif
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 3b7a1cf8cc8..f914f760e19 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -1398,6 +1398,8 @@ config STM32_STM32F37XX
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
+ select STM32_HAVE_SPI2
+ select STM32_HAVE_SPI3
select STM32_HAVE_USART3
config STM32_STM32F40XX
@@ -2074,7 +2076,7 @@ config STM32_SPI6
config STM32_SYSCFG
bool "SYSCFG"
default y
- depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX
+ depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX || STM32_CONNECTIVITYLINE
config STM32_TIM1
bool "TIM1"
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index aef4ef08155..f08a904d67e 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/stm32/Make.defs
#
-# Copyright (C) 2009, 2011-2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -125,7 +125,7 @@ CHIP_CSRCS += stm32_tickless.c
endif
ifeq ($(CONFIG_STM32_ONESHOT),y)
-CHIP_CSRCS += stm32_oneshot.c
+CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_STM32_FREERUN),y)
diff --git a/arch/arm/src/stm32/chip/stm32_otghs.h b/arch/arm/src/stm32/chip/stm32_otghs.h
index 42b44222621..95b4772a37a 100644
--- a/arch/arm/src/stm32/chip/stm32_otghs.h
+++ b/arch/arm/src/stm32/chip/stm32_otghs.h
@@ -59,8 +59,6 @@
#define OTGHS_PID_MDATA (3) /* Non-control */
#define OTGHS_PID_SETUP (3) /* Control */
-/* If OTGHS2 is defined (FS mode of the HS module), then remap the OTGHS base address */
-
/* Register Offsets *********************************************************************************/
/* Core global control and status registers */
diff --git a/arch/arm/src/stm32/chip/stm32_spi.h b/arch/arm/src/stm32/chip/stm32_spi.h
index bdbabab3346..3e0a086b63c 100644
--- a/arch/arm/src/stm32/chip/stm32_spi.h
+++ b/arch/arm/src/stm32/chip/stm32_spi.h
@@ -66,7 +66,7 @@
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
#endif
@@ -92,7 +92,7 @@
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@@ -107,7 +107,7 @@
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@@ -135,7 +135,11 @@
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
-#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
+#else
+# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
+#endif
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
@@ -148,7 +152,7 @@
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#endif
@@ -156,22 +160,23 @@
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
-#ifdef CONFIG_STM32_STM32F30XX
-#define SPI_CR1_DS_SHIFT (8) /* Bits 8-11: Data size */
-#define SPI_CR1_DS_MASK (15 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_4BIT (3 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_5BIT (4 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_6BIT (5 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_7BIT (6 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_8BIT (7 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_9BIT (8 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_10BIT (9 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_11BIT (10 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_12BIT (11 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_13BIT (12 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_14BIT (13 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_15BIT (14 << SPI_CR1_DS_SHIFT)
-# define SPI_CR1_DS_16BIT (15 << SPI_CR1_DS_SHIFT)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
+#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS(n) ((uint32_t)((n) - 1) << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
@@ -183,7 +188,7 @@
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */
# define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */
#endif
@@ -194,29 +199,29 @@
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
-# define SPI_SR_TIFRFE (1 << 8) /* Bit 8: TI frame format error */
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
+# define SPI_SR_FRE (1 << 8) /* Bit 8: TI frame format error */
#endif
-#ifdef CONFIG_STM32_STM32F30XX
-#define SPI_CR1_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
-#define SPI_CR1_FRLVL_MASK (3 << SPI_CR1_FRLVL_SHIFT)
-# define SPI_CR1_FRLVL_EMPTY (0 << SPI_CR1_FRLVL_SHIFT) /* FIFO empty */
-# define SPI_CR1_FRLVL_QUARTER (1 << SPI_CR1_FRLVL_SHIFT) /* 1/4 FIFO */
-# define SPI_CR1_FRLVL_HALF (2 << SPI_CR1_FRLVL_SHIFT) /* 1/2 FIFO */
-# define SPI_CR1_FRLVL_FULL (3 << SPI_CR1_FRLVL_SHIFT) /* FIFO full */
-#define SPI_CR1_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
-#define SPI_CR1_FTLVL_MASK (3 << SPI_CR1_FTLVL_SHIFT)
-# define SPI_CR1_FTLVL_EMPTY (0 << SPI_CR1_FTLVL_SHIFT) /* FIFO empty */
-# define SPI_CR1_FTLVL_QUARTER (1 << SPI_CR1_FTLVL_SHIFT) /* 1/4 FIFO */
-# define SPI_CR1_FTLVL_HALF (2 << SPI_CR1_FTLVL_SHIFT) /* 1/2 FIFO */
-# define SPI_CR1_FTLVL_FULL (3 << SPI_CR1_FTLVL_SHIFT) /* FIFO full */
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
+#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
+# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
+# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
+# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
+# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
+#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
+#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
+# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
+# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
+# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
+# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#endif
/* I2S configuration register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
# define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
@@ -244,7 +249,7 @@
/* I2S prescaler register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32F40XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
@@ -252,4 +257,3 @@
#endif
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H */
-
diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
index 35b2ad8156c..4318b9d9cf7 100644
--- a/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
@@ -148,26 +148,37 @@
#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */
#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */
#define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT)
-# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */
-# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */
+#ifndef CONFIG_STM32_CONNECTIVITYLINE
+# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */
+# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */
+#endif
# define RCC_CFGR_PLLMUL_CLKx4 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL input clock x 4 */
# define RCC_CFGR_PLLMUL_CLKx5 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL input clock x 5 */
# define RCC_CFGR_PLLMUL_CLKx6 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL input clock x 6 */
# define RCC_CFGR_PLLMUL_CLKx7 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL input clock x 7 */
# define RCC_CFGR_PLLMUL_CLKx8 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL input clock x 8 */
# define RCC_CFGR_PLLMUL_CLKx9 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL input clock x 9 */
-# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */
-# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */
-# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
-# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
-# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
-# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
-# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
+#ifndef CONFIG_STM32_CONNECTIVITYLINE
+# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */
+# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */
+# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
+# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
+# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
+# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
+# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
+#else
+# define RCC_CFGR_PLLMUL_CLKx65 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 6.5 */
+#endif
+
#ifndef CONFIG_STM32_VALUELINE
# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB FS prescaler */
+# define RCC_CFGR_USBPREd0 (0) /* PLLCLK / 1 */
+# define RCC_CFGR_USBPREd15 (1) /* PLLCLK / 1.5 */
#endif
#ifdef CONFIG_STM32_CONNECTIVITYLINE
# define RCC_CFGR_OTGFSPRE (1 << 22) /* Bit 22: OTG FS prescaler */
+# define RCC_CFGR_OTGFSPREd2 (1) /* PLL_VCO (2x PLLCLK) / 2 */
+# define RCC_CFGR_OTGFSPREd3 (0) /* PLL_VCO (3x PLLCLK) / 3 */
#endif
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */
#define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT)
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h b/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
index 2219009ef7d..6b4ccd227dd 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
+++ b/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
@@ -113,7 +113,7 @@
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: Reserved */
-#define SYSCFG_EXTICR_PORTE (5) /* 0101: PF[x] pin */
+#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
index ff75a5d0ad9..0fdaef01398 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
@@ -413,10 +413,11 @@
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
-#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F411)
-# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
+#if defined(CONFIG_STM32_STM32F411)
+# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
#endif
#if defined(CONFIG_STM32_STM32F446)
+# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
# define GPIO_I2C2_SDA_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN12)
#endif
diff --git a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
index b0f431ab06f..8658aec0a89 100644
--- a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
+++ b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
@@ -1,10 +1,11 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
*
- * Copyright (C) 2012, 2014-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
- * Author: Gregory Nutt
- * Paul Alexander Patience
+ * Authors: Gregory Nutt
+ * Paul Alexander Patience
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -470,44 +471,38 @@
/* Core interrupt and Interrupt mask registers */
-#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */
+#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: ro Current mode of operation */
# define OTGFS_GINTSTS_DEVMODE (0)
# define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD)
-#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */
-#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */
-#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */
-#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */
-#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
-#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
+#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: rc_w1 Mode mismatch interrupt */
+#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: ro OTG interrupt */
+#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: rc_w1 Start of frame */
+#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: ro RxFIFO non-empty */
+#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: ro Non-periodic TxFIFO empty */
+#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: ro Global IN non-periodic NAK effective */
#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
- /* Bits 8-9: Reserved, must be kept at reset value */
-#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
-#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
-#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
-#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
-#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
-#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
- /* Bits 16 Reserved, must be kept at reset value */
-#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */
-#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
-#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
-#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
-#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
-#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
- /* Bit 22: Reserved, must be kept at reset value */
-#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
-# define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
-#endif
-#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
-#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
-#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
-#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
-# define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
-#endif
-#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
-#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
-#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
-#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */
+#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */
+#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: rc_w1 Early suspend */
+#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: rc_w1 USB suspend */
+#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: rc_w1 USB reset */
+#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: rc_w1 Enumeration done */
+#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: rc_w1 Isochronous OUT packet dropped interrupt */
+#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: rc_w1 End of periodic frame interrupt */
+#define OTGFS_GINT_RES16 (1 << 16) /* Bits 16 Reserved, must be kept at reset value */
+#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Reserved in GINT rw Endpoint mismatch interrupt mask */
+#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */
+#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */
+#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1Incomplete isochronous IN transfer */
+#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer */
+#define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */
+#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */
+#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */
+#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */
+#define OTGFS_GINT_RES27 (1 << 27) /* Bit 27 Reserved, must be kept at reset value */
+#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: rc_w1 Connector ID status change */
+#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: rc_w1 Disconnect detected interrupt */
+#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: rc_w1 Session request/new session detected interrupt */
+#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: rc_w1 Resume/remote wakeup detected interrupt */
/* Receive status debug read/OTG status read and pop registers (host mode) */
diff --git a/arch/arm/src/stm32/iar/stm32_vectors.S b/arch/arm/src/stm32/iar/stm32_vectors.S
index 9b2c0432ba6..cb9069dbc19 100644
--- a/arch/arm/src/stm32/iar/stm32_vectors.S
+++ b/arch/arm/src/stm32/iar/stm32_vectors.S
@@ -176,7 +176,207 @@ __vector_table:
#if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F10XX)
-# include "chip/stm32f10xxx_vectors.h"
+
+# if defined(CONFIG_STM32_VALUELINE)
+
+ DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
+ DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
+ DCD stm32_tamper /* Vector 16+2: Tamper interrupt */
+ DCD stm32_rtc /* Vector 16+3: RTC Wakeup through EXTI line interrupt */
+ DCD stm32_flash /* Vector 16+4: Flash global interrupt */
+ DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
+ DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
+ DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
+ DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
+ DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
+ DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
+ DCD stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
+ DCD stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
+ DCD stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
+ DCD stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
+ DCD stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
+ DCD stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
+ DCD stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
+ DCD stm32_adc1 /* Vector 16+18: ADC1 global interrupt */
+ DCD stm32_reserved /* Vector 16+19: Reserved 0 */
+ DCD stm32_reserved /* Vector 16+20: Reserved 1 */
+ DCD stm32_reserved /* Vector 16+21: Reserved 2 */
+ DCD stm32_reserved /* Vector 16+22: Reserved 3 */
+ DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
+ DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
+ DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
+ DCD stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
+ DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
+ DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
+ DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
+ DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
+ DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
+ DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
+ DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
+ DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
+ DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
+ DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
+ DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
+ DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
+ DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
+ DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
+ DCD stm32_rtcalr /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
+ DCD stm32_cec /* Vector 16+42: CEC global interrupt */
+ DCD stm32_tim12 /* Vector 16+43: TIM12 global interrupt */
+ DCD stm32_tim13 /* Vector 16+44: TIM13 global interrupt */
+ DCD stm32_tim14 /* Vector 16+45: TIM14 global interrupt */
+ DCD stm32_reserved /* Vector 16+46: Reserved 4 */
+ DCD stm32_reserved /* Vector 16+47: Reserved 5 */
+ DCD stm32_fsmc /* Vector 16+48: FSMC global interrupt */
+ DCD stm32_reserved /* Vector 16+49: Reserved 6 */
+ DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
+ DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
+ DCD stm32_uart4 /* Vector 16+52: USART2 global interrupt */
+ DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
+ DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt */
+ DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
+ DCD stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
+ DCD stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
+ DCD stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
+ DCD stm32_dma2ch45 /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
+ DCD stm32_dma2ch5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
+
+# elif defined(CONFIG_STM32_CONNECTIVITYLINE)
+
+ DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
+ DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
+ DCD stm32_tamper /* Vector 16+2: Tamper interrupt */
+ DCD stm32_rtc /* Vector 16+3: RTC global interrupt */
+ DCD stm32_flash /* Vector 16+4: Flash global interrupt */
+ DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
+ DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
+ DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
+ DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
+ DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
+ DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
+ DCD stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
+ DCD stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
+ DCD stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
+ DCD stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
+ DCD stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
+ DCD stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
+ DCD stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
+ DCD stm32_adc12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
+ DCD stm32_can1tx /* Vector 16+19: CAN1 TX interrupts */
+ DCD stm32_can1rx0 /* Vector 16+20: CAN1 RX0 interrupts */
+ DCD stm32_can1rx /* Vector 16+21: CAN1 RX1 interrupt */
+ DCD stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */
+ DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
+ DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt */
+ DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt */
+ DCD stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
+ DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
+ DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
+ DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
+ DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
+ DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
+ DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
+ DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
+ DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
+ DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
+ DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
+ DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
+ DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
+ DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
+ DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
+ DCD stm32_rtcalr /* Vector 16+41: RTC alarm through EXTI line interrupt */
+ DCD stm32_otgfswkup /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+ DCD stm32_reserved /* Vector 16+43: Reserved 0 */
+ DCD stm32_reserved /* Vector 16+44: Reserved 1 */
+ DCD stm32_reserved /* Vector 16+45: Reserved 2 */
+ DCD stm32_reserved /* Vector 16+46: Reserved 3 */
+ DCD stm32_reserved /* Vector 16+47: Reserved 4 */
+ DCD stm32_reserved /* Vector 16+48: Reserved 5 */
+ DCD stm32_reserved /* Vector 16+49: Reserved 6 */
+ DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
+ DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
+ DCD stm32_uart4 /* Vector 16+52: UART4 global interrupt */
+ DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
+ DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt */
+ DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
+ DCD stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
+ DCD stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
+ DCD stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
+ DCD stm32_dma2ch4 /* Vector 16+59: DMA2 Channel 4 global interrupt */
+ DCD stm32_dma2ch5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
+ DCD stm32_eth /* Vector 16+61: Ethernet global interrupt */
+ DCD stm32_ethwkup /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
+ DCD stm32_can2tx /* Vector 16+63: CAN2 TX interrupts */
+ DCD stm32_can2rx0 /* Vector 16+64: CAN2 RX0 interrupts */
+ DCD stm32_can2rx1 /* Vector 16+65: CAN2 RX1 interrupt */
+ DCD stm32_can2sce /* Vector 16+66: CAN2 SCE interrupt */
+ DCD stm32_otgfs /* Vector 16+67: USB On The Go FS global interrupt */
+
+# else /* CONFIG_STM32_CONNECTIVITYLINE */
+
+ DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
+ DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
+ DCD stm32_tamper /* Vector 16+2: Tamper interrupt */
+ DCD stm32_rtc /* Vector 16+3: RTC global interrupt */
+ DCD stm32_flash /* Vector 16+4: Flash global interrupt */
+ DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
+ DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
+ DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
+ DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
+ DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
+ DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
+ DCD stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
+ DCD stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
+ DCD stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
+ DCD stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
+ DCD stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
+ DCD stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
+ DCD stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
+ DCD stm32_adc12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
+ DCD stm32_usbhpcantx /* Vector 16+19: USB High Priority or CAN TX interrupts*/
+ DCD stm32_usblpcanrx0 /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/
+ DCD stm32_can1rx1 /* Vector 16+21: CAN1 RX1 interrupt */
+ DCD stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */
+ DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
+ DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt */
+ DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt */
+ DCD stm32_tim1rtgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
+ DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
+ DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
+ DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
+ DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
+ DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
+ DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
+ DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
+ DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
+ DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
+ DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
+ DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
+ DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
+ DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
+ DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
+ DCD stm32_rtcalr /* Vector 16+41: RTC alarm through EXTI line interrupt */
+ DCD stm32_usbwkup /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/
+ DCD stm32_tim8brk /* Vector 16+43: TIM8 Break interrupt */
+ DCD stm32_tim8up /* Vector 16+44: TIM8 Update interrupt */
+ DCD stm32_tim8trgcom /* Vector 16+45: TIM8 Trigger and Commutation interrupts */
+ DCD stm32_tim8cc /* Vector 16+46: TIM8 Capture Compare interrupt */
+ DCD stm32_adc3 /* Vector 16+47: ADC3 global interrupt */
+ DCD stm32_fsmc /* Vector 16+48: FSMC global interrupt */
+ DCD stm32_sdio /* Vector 16+49: SDIO global interrupt */
+ DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
+ DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
+ DCD stm32_uart4 /* Vector 16+52: UART4 global interrupt */
+ DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
+ DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt */
+ DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
+ DCD stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
+ DCD stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
+ DCD stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
+ DCD stm32_dma2ch45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
+
+# endif /* CONFIG_STM32_CONNECTIVITYLINE */
+
#elif defined(CONFIG_STM32_STM32F20XX)
DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
@@ -278,7 +478,7 @@ __vector_table:
* .text
************************************************************************************/
- SECTION .text:CODE:NOROOT(2)
+ SECTION .text:CODE:NOROOT(8)
handlers:
HANDLER stm32_reserved, STM32_IRQ_RESERVED /* Unexpected/reserved vector */
@@ -304,8 +504,196 @@ handlers:
#if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F10XX)
-# include "chip/stm32f10xxx_vectors.h"
+
+
+# if defined(CONFIG_STM32_VALUELINE)
+
+ HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
+ HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
+ HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */
+ HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC Wakeup through EXTI line interrupt */
+ HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
+ HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
+ HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
+ HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
+ HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
+ HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
+ HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
+ HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
+ HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
+ HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
+ HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
+ HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
+ HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
+ HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
+ HANDLER stm32_adc1, STM32_IRQ_ADC1 /* Vector 16+18: ADC1 global interrupt */
+ HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
+ HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
+ HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
+ HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
+ HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
+ HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
+ HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
+ HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
+ HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
+ HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
+ HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
+ HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
+ HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
+ HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
+ HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
+ HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
+ HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
+ HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
+ HANDLER stm32_rtcalr, STM32_IRQ_RTCALR /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
+ HANDLER stm32_cec, STM32_IRQ_CEC /* Vector 16+42: CEC global interrupt */
+ HANDLER stm32_tim12, STM32_IRQ_TIM12 /* Vector 16+43: TIM12 global interrupt */
+ HANDLER stm32_tim13, STM32_IRQ_TIM13 /* Vector 16+44: TIM13 global interrupt */
+ HANDLER stm32_tim14, STM32_IRQ_TIM14 /* Vector 16+45: TIM14 global interrupt */
+ HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */
+ HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
+ HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
+ HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: USART2 global interrupt */
+ HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
+ HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */
+ HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
+ HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
+ HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
+ HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
+ HANDLER stm32_dma2ch45, STM32_IRQ_DMA2CH45 /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
+ HANDLER stm32_dma2ch5, STM32_IRQ_DMA2CH5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
+
+# elif defined(CONFIG_STM32_CONNECTIVITYLINE)
+
+ HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
+ HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
+ HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */
+ HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC global interrupt */
+ HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
+ HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
+ HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
+ HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
+ HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
+ HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
+ HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
+ HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
+ HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
+ HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
+ HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
+ HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
+ HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
+ HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
+ HANDLER stm32_adc12, STM32_IRQ_ADC12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
+ HANDLER stm32_can1tx, STM32_IRQ_CAN1TX /* Vector 16+19: CAN1 TX interrupts */
+ HANDLER stm32_can1rx0, STM32_IRQ_CAN1RX0 /* Vector 16+20: CAN1 RX0 interrupts */
+ HANDLER stm32_can1rx, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */
+ HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */
+ HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
+ HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt */
+ HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt */
+ HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
+ HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
+ HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
+ HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
+ HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
+ HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
+ HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
+ HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
+ HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
+ HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
+ HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
+ HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
+ HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
+ HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
+ HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
+ HANDLER stm32_rtcalr, STM32_IRQ_RTCALRM /* Vector 16+41: RTC alarm through EXTI line interrupt */
+ HANDLER stm32_otgfswkup, STM32_IRQ_OTGFSWKUP /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+ HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
+ HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
+ HANDLER stm32_uart4 , STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */
+ HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
+ HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */
+ HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
+ HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
+ HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
+ HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
+ HANDLER stm32_dma2ch4, STM32_IRQ_DMA2CH4 /* Vector 16+59: DMA2 Channel 4 global interrupt */
+ HANDLER stm32_dma2ch5, STM32_IRQ_DMA2CH5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
+ HANDLER stm32_eth, STM32_IRQ_ETH /* Vector 16+61: Ethernet global interrupt */
+ HANDLER stm32_ethwkup, STM32_IRQ_ETHWKUP /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
+ HANDLER stm32_can2tx, STM32_IRQ_CAN2TX /* Vector 16+63: CAN2 TX interrupts */
+ HANDLER stm32_can2rx0, STM32_IRQ_CAN2RX0 /* Vector 16+64: CAN2 RX0 interrupts */
+ HANDLER stm32_can2rx1, STM32_IRQ_CAN2RX1 /* Vector 16+65: CAN2 RX1 interrupt */
+ HANDLER stm32_can2sce, STM32_IRQ_CAN2SCE /* Vector 16+66: CAN2 SCE interrupt */
+ HANDLER stm32_otgfs, STM32_IRQ_OTGFS /* Vector 16+67: USB On The Go FS global interrupt */
+
+# else /* CONFIG_STM32_CONNECTIVITYLINE */
+
+ HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
+ HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
+ HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */
+ HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC global interrupt */
+ HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
+ HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
+ HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
+ HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
+ HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
+ HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
+ HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
+ HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
+ HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
+ HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
+ HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
+ HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
+ HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
+ HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
+ HANDLER stm32_adc12, STM32_IRQ_ADC12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
+ HANDLER stm32_usbhpcantx, STM32_IRQ_USBHPCANTX /* Vector 16+19: USB High Priority or CAN TX interrupts*/
+ HANDLER stm32_usblpcanrx0, STM32_IRQ_USBLPCANRX0 /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/
+ HANDLER stm32_can1rx1, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */
+ HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */
+ HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
+ HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt */
+ HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt */
+ HANDLER stm32_tim1rtgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
+ HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
+ HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
+ HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
+ HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
+ HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
+ HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
+ HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
+ HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
+ HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
+ HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
+ HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
+ HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
+ HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
+ HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
+ HANDLER stm32_rtcalr, STM32_IRQ_RTCALRM /* Vector 16+41: RTC alarm through EXTI line interrupt */
+ HANDLER stm32_usbwkup, STM32_IRQ_USBWKUP /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/
+ HANDLER stm32_tim8brk, STM32_IRQ_TIM8BRK /* Vector 16+43: TIM8 Break interrupt */
+ HANDLER stm32_tim8up, STM32_IRQ_TIM8UP /* Vector 16+44: TIM8 Update interrupt */
+ HANDLER stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM /* Vector 16+45: TIM8 Trigger and Commutation interrupts */
+ HANDLER stm32_tim8cc, STM32_IRQ_TIM8CC /* Vector 16+46: TIM8 Capture Compare interrupt */
+ HANDLER stm32_adc3, STM32_IRQ_ADC3 /* Vector 16+47: ADC3 global interrupt */
+ HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */
+ HANDLER stm32_sdio, STM32_IRQ_SDIO /* Vector 16+49: SDIO global interrupt */
+ HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
+ HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
+ HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */
+ HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
+ HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */
+ HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
+ HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
+ HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
+ HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
+ HANDLER stm32_dma2ch45, STM32_IRQ_DMA2CH45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
+
+# endif /* CONFIG_STM32_CONNECTIVITYLINE */
+
#elif defined(CONFIG_STM32_STM32F20XX)
+
HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper and time stamp interrupts */
@@ -387,6 +775,7 @@ handlers:
HANDLER stm32_dcmi, STM32_IRQ_DCMI /* Vector 16+78: DCMI global interrupt */
HANDLER stm32_cryp, STM32_IRQ_CRYP /* Vector 16+79: CRYP crypto global interrupt */
HANDLER stm32_hash, STM32_IRQ_HASH /* Vector 16+80: Hash and Rng global interrupt */
+
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F37XX)
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index 31109fd8f50..2972ebaf9a6 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -1657,7 +1657,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
for (i = 0; i < priv->nchannels; i++)
{
- priv->cb->au_receive(dev, priv->current, priv->dmabuffer[priv->current]);
+ priv->cb->au_receive(dev, priv->chanlist[priv->current], priv->dmabuffer[priv->current]);
priv->current++;
if (priv->current >= priv->nchannels)
{
diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c
index 81c49340ae9..a401feca562 100644
--- a/arch/arm/src/stm32/stm32_bbsram.c
+++ b/arch/arm/src/stm32/stm32_bbsram.c
@@ -256,7 +256,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
static inline void stm32_bbsram_unlock(void)
{
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
}
/****************************************************************************
@@ -276,7 +276,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/****************************************************************************
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index bced5def661..8103477f5a9 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -704,7 +704,10 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv);
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int stm32_phyintenable(FAR struct stm32_ethmac_s *priv);
#endif
+#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \
+ defined(CONFIG_ETH0_PHY_DM9161)
static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
+#endif
static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value);
#ifdef CONFIG_ETH0_PHY_DM9161
static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv);
@@ -1687,12 +1690,6 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
continue;
}
-#ifdef CONFIG_NET_PKT
- /* When packet sockets are enabled, feed the frame into the packet tap */
-
- pkt_input(&priv->dev);
-#endif
-
/* We only accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv4
@@ -3098,6 +3095,8 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv)
*
****************************************************************************/
+#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \
+ defined(CONFIG_ETH0_PHY_DM9161)
static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value)
{
volatile uint32_t timeout;
@@ -3134,6 +3133,7 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
return -ETIMEDOUT;
}
+#endif
/****************************************************************************
* Function: stm32_phywrite
@@ -3278,7 +3278,10 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
{
+#ifdef CONFIG_STM32_AUTOGEN
volatile uint32_t timeout;
+#endif
+
uint32_t regval;
uint16_t phyval;
int ret;
diff --git a/arch/arm/src/stm32/stm32_freerun.c b/arch/arm/src/stm32/stm32_freerun.c
index 836df043ad7..38133c7c365 100644
--- a/arch/arm/src/stm32/stm32_freerun.c
+++ b/arch/arm/src/stm32/stm32_freerun.c
@@ -53,7 +53,7 @@
#ifdef CONFIG_STM32_FREERUN
/****************************************************************************
- * Private Functions
+ * Private Data
****************************************************************************/
static struct stm32_freerun_s *g_freerun;
@@ -80,6 +80,7 @@ static struct stm32_freerun_s *g_freerun;
*
****************************************************************************/
+#ifndef CONFIG_CLOCK_TIMEKEEPING
static int stm32_freerun_handler(int irq, void *context)
{
struct stm32_freerun_s *freerun = g_freerun;
@@ -90,6 +91,7 @@ static int stm32_freerun_handler(int irq, void *context)
STM32_TIM_ACKINT(freerun->tch, 0);
return OK;
}
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
/****************************************************************************
* Public Functions
@@ -140,15 +142,21 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
* success.
*/
- freerun->chan = chan;
- freerun->running = false;
- freerun->overflow = 0;
+ freerun->chan = chan;
+ freerun->running = false;
- g_freerun = freerun;
+#ifdef CONFIG_CLOCK_TIMEKEEPING
+ freerun->counter_mask = 0xffffffffull;
+#endif
+
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+ freerun->overflow = 0;
+ g_freerun = freerun;
/* Set up to receive the callback when the counter overflow occurs */
STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, 0);
+#endif
/* Set timer period */
@@ -157,8 +165,11 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
/* Start the counter */
STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP);
+
+#ifndef CONFIG_CLOCK_TIMEKEEPING
STM32_TIM_ACKINT(freerun->tch, 0);
STM32_TIM_ENABLEINT(freerun->tch, 0);
+#endif
return OK;
}
@@ -182,6 +193,8 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
*
****************************************************************************/
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+
int stm32_freerun_counter(struct stm32_freerun_s *freerun,
struct timespec *ts)
{
@@ -257,6 +270,16 @@ int stm32_freerun_counter(struct stm32_freerun_s *freerun,
return OK;
}
+#else /* CONFIG_CLOCK_TIMEKEEPING */
+
+int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter)
+{
+ *counter = (uint64_t)STM32_TIM_GETCOUNTER(freerun->tch);
+ return OK;
+}
+
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
/****************************************************************************
* Name: stm32_freerun_uninitialize
*
diff --git a/arch/arm/src/stm32/stm32_freerun.h b/arch/arm/src/stm32/stm32_freerun.h
index 08dd1786da7..bc7609666cf 100644
--- a/arch/arm/src/stm32/stm32_freerun.h
+++ b/arch/arm/src/stm32/stm32_freerun.h
@@ -64,9 +64,16 @@ struct stm32_freerun_s
{
uint8_t chan; /* The timer/counter in use */
bool running; /* True: the timer is running */
- uint32_t overflow; /* Timer counter overflow */
FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */
uint32_t frequency;
+
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+ uint32_t overflow; /* Timer counter overflow */
+#endif
+
+#ifdef CONFIG_CLOCK_TIMEKEEPING
+ uint64_t counter_mask;
+#endif
};
/****************************************************************************
@@ -127,9 +134,18 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
*
****************************************************************************/
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+
int stm32_freerun_counter(struct stm32_freerun_s *freerun,
struct timespec *ts);
+#else /* CONFIG_CLOCK_TIMEKEEPING */
+
+int stm32_freerun_counter(struct stm32_freerun_s *freerun,
+ uint64_t *counter);
+
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
/****************************************************************************
* Name: stm32_freerun_uninitialize
*
diff --git a/arch/arm/src/stm32/stm32_lse.c b/arch/arm/src/stm32/stm32_lse.c
index 18334852ba2..64e697976ea 100644
--- a/arch/arm/src/stm32/stm32_lse.c
+++ b/arch/arm/src/stm32/stm32_lse.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_lse.c
*
- * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -45,18 +45,6 @@
#include "stm32_rcc.h"
#include "stm32_waste.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -74,14 +62,12 @@
void stm32_rcc_enablelse(void)
{
- bool bkpenabled;
-
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
- bkpenabled = stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
@@ -115,8 +101,5 @@ void stm32_rcc_enablelse(void)
/* Disable backup domain access if it was disabled on entry */
- if (!bkpenabled)
- {
- (void)stm32_pwr_enablebkp(false);
- }
+ stm32_pwr_enablebkp(false);
}
diff --git a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c b/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c
new file mode 100644
index 00000000000..41426958bcf
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c
@@ -0,0 +1,345 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "stm32_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct stm32_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct stm32_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */
+ oneshot_callback_t callback; /* Internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void stm32_oneshot_handler(void *arg);
+
+static int stm32_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int stm32_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int stm32_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = stm32_max_delay,
+ .start = stm32_start,
+ .cancel = stm32_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when stm32_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void stm32_oneshot_handler(void *arg)
+{
+ FAR struct stm32_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * stm32_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: stm32_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int stm32_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct stm32_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: stm32_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int stm32_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct stm32_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = stm32_oneshot_start(&priv->oneshot,
+ stm32_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: stm32_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int stm32_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct stm32_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = stm32_oneshot_cancel(&priv->oneshot, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct stm32_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct stm32_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained STM32 oneshot timer */
+
+ ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c
index 231d091a0cc..c570e6d084f 100644
--- a/arch/arm/src/stm32/stm32_otgfsdev.c
+++ b/arch/arm/src/stm32/stm32_otgfsdev.c
@@ -1,8 +1,9 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_otgfsdev.c
*
- * Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Copyright (C) 2012-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -111,7 +112,8 @@
# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192
#endif
-#if (CONFIG_USBDEV_RXFIFO_SIZE + CONFIG_USBDEV_EP0_TXFIFO_SIZE + \
+#if (CONFIG_USBDEV_RXFIFO_SIZE + \
+ CONFIG_USBDEV_EP0_TXFIFO_SIZE + CONFIG_USBDEV_EP1_TXFIFO_SIZE + \
CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280
# error "FIFO allocations exceed FIFO memory size"
#endif
@@ -151,6 +153,26 @@
# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range"
#endif
+#define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \
+ (OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \
+ |OTGFS_GINT_RES2223 | \
+ OTGFS_GINT_RES27)
+
+#define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \
+ OTGFS_GINT_SOF | \
+ OTGFS_GINT_ESUSP | \
+ OTGFS_GINT_USBSUSP | \
+ OTGFS_GINT_USBRST | \
+ OTGFS_GINT_ENUMDNE | \
+ OTGFS_GINT_ISOODRP | \
+ OTGFS_GINT_EOPF | \
+ OTGFS_GINT_IISOIXFR | \
+ OTGFS_GINT_IISOOXFR | \
+ OTGFS_GINT_CIDSCHG | \
+ OTGFS_GINT_DISC | \
+ OTGFS_GINT_SRQ | \
+ OTGFS_GINT_WKUP)
+
/* Debug ***********************************************************************/
/* Trace error codes */
@@ -3119,154 +3141,163 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
/* Disable the Rx status queue level interrupt */
- regval = stm32_getreg(STM32_OTGFS_GINTMSK);
- regval &= ~OTGFS_GINT_RXFLVL;
- stm32_putreg(regval, STM32_OTGFS_GINTMSK);
-
- /* Get the status from the top of the FIFO */
-
- regval = stm32_getreg(STM32_OTGFS_GRXSTSP);
-
- /* Decode status fields */
-
- epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
-
- if (epphy < STM32_NENDPOINTS)
+ while(0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
{
- privep = &priv->epout[epphy];
- /* Handle the RX event according to the packet status field */
+ /* Get the status from the top of the FIFO */
- switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
- {
- /* Global OUT NAK. This indicate that the global OUT NAK bit has taken
- * effect.
- *
- * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
- * Care.
+ regval = stm32_getreg(STM32_OTGFS_GRXSTSP);
+
+ /* Decode status fields */
+
+ epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
+
+ /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP register
+ * happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
+ * All of which provide out of range indexes for epout[epphy]
*/
- case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
- {
- usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
- }
- break;
+ if (epphy < STM32_NENDPOINTS)
+ {
+ privep = &priv->epout[epphy];
- /* OUT data packet received.
- *
- * PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
- * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
- */
+ /* Handle the RX event according to the packet status field */
- case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
+ switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
- usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
- bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
- if (bcnt > 0)
- {
- stm32_epout_receive(privep, bcnt);
+ /* Global OUT NAK. This indicate that the global OUT NAK bit has taken
+ * effect.
+ *
+ * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
+ * Care.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
+ {
+ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
+ }
+ break;
+
+ /* OUT data packet received.
+ *
+ * PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
+ * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
+ {
+ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
+ bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
+ if (bcnt > 0)
+ {
+ stm32_epout_receive(privep, bcnt);
+ }
+ }
+ break;
+
+ /* OUT transfer completed. This indicates that an OUT data transfer for
+ * the specified OUT endpoint has completed. After this entry is popped
+ * from the receive FIFO, the core asserts a Transfer Completed interrupt
+ * on the specified OUT endpoint.
+ *
+ * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
+ * which the data transfer is complete, DPID = Don't Care.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
+ {
+ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
+ }
+ break;
+
+ /* SETUP transaction completed. This indicates that the Setup stage for
+ * the specified endpoint has completed and the Data stage has started.
+ * After this entry is popped from the receive FIFO, the core asserts a
+ * Setup interrupt on the specified control OUT endpoint (triggers an
+ * interrupt).
+ *
+ * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
+ * DPID = Don't Care.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
+ {
+ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
+
+ /* Now that the Setup Phase is complete if it was an OUT enable
+ * the endpoint
+ * (Doing this here prevents the loss of the first FIFO word)
+ */
+
+ if (priv->ep0state == EP0STATE_SETUP_OUT)
+ {
+
+ /* Clear NAKSTS so that we can receive the data */
+
+ regval = stm32_getreg(STM32_OTGFS_DOEPCTL0);
+ regval |= OTGFS_DOEPCTL0_CNAK;
+ stm32_putreg(regval, STM32_OTGFS_DOEPCTL0);
+
}
+ }
+ break;
+
+ /* SETUP data packet received. This indicates that a SETUP packet for the
+ * specified endpoint is now available for reading from the receive FIFO.
+ *
+ * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
+ {
+ uint16_t datlen;
+
+ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
+
+ /* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
+ * the last one overwrites the previous setup packets and only that
+ * last SETUP packet will be processed.
+ */
+
+ stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
+ USB_SIZEOF_CTRLREQ);
+
+ /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
+ * then we need to wait for the completion of the data phase to
+ * process the setup command. If it is an IN SETUP packet, then
+ * we must processing the command BEFORE we enter the DATA phase.
+ *
+ * If the data associated with the OUT SETUP packet is zero length,
+ * then, of course, we don't need to wait.
+ */
+
+ datlen = GETUINT16(priv->ctrlreq.len);
+ if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
+ {
+ /* Wait for the data phase. */
+
+ priv->ep0state = EP0STATE_SETUP_OUT;
+ }
+ else
+ {
+ /* We can process the setup data as soon as SETUP done word is
+ * popped of the RxFIFO.
+ */
+
+ priv->ep0state = EP0STATE_SETUP_READY;
+ }
+ }
+ break;
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
+ (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
+ }
+ break;
}
- break;
-
- /* OUT transfer completed. This indicates that an OUT data transfer for
- * the specified OUT endpoint has completed. After this entry is popped
- * from the receive FIFO, the core asserts a Transfer Completed interrupt
- * on the specified OUT endpoint.
- *
- * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
- * which the data transfer is complete, DPID = Don't Care.
- */
-
- case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
- {
- usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
- }
- break;
-
- /* SETUP transaction completed. This indicates that the Setup stage for
- * the specified endpoint has completed and the Data stage has started.
- * After this entry is popped from the receive FIFO, the core asserts a
- * Setup interrupt on the specified control OUT endpoint (triggers an
- * interrupt).
- *
- * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
- * DPID = Don't Care.
- */
-
- case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
- {
- usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
- }
- break;
-
- /* SETUP data packet received. This indicates that a SETUP packet for the
- * specified endpoint is now available for reading from the receive FIFO.
- *
- * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
- */
-
- case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
- {
- uint16_t datlen;
-
- usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
-
- /* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
- * the last one overwrites the previous setup packets and only that
- * last SETUP packet will be processed.
- */
-
- stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
- USB_SIZEOF_CTRLREQ);
-
- /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
- * then we need to wait for the completion of the data phase to
- * process the setup command. If it is an IN SETUP packet, then
- * we must processing the command BEFORE we enter the DATA phase.
- *
- * If the data associated with the OUT SETUP packet is zero length,
- * then, of course, we don't need to wait.
- */
-
- datlen = GETUINT16(priv->ctrlreq.len);
- if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
- {
- /* Clear NAKSTS so that we can receive the data */
-
- regval = stm32_getreg(STM32_OTGFS_DOEPCTL0);
- regval |= OTGFS_DOEPCTL0_CNAK;
- stm32_putreg(regval, STM32_OTGFS_DOEPCTL0);
-
- /* Wait for the data phase. */
-
- priv->ep0state = EP0STATE_SETUP_OUT;
- }
- else
- {
- /* We can process the setup data as soon as SETUP done word is
- * popped of the RxFIFO.
- */
-
- priv->ep0state = EP0STATE_SETUP_READY;
- }
- }
- break;
-
- default:
- {
- usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
- (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
- }
- break;
- }
+ }
}
-
- /* Enable the Rx Status Queue Level interrupt */
-
- regval = stm32_getreg(STM32_OTGFS_GINTMSK);
- regval |= OTGFS_GINT_RXFLVL;
- stm32_putreg(regval, STM32_OTGFS_GINTMSK);
}
/****************************************************************************
@@ -3289,7 +3320,7 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);
regval &= ~OTGFS_GUSBCFG_TRDT_MASK;
- regval |= OTGFS_GUSBCFG_TRDT(5);
+ regval |= OTGFS_GUSBCFG_TRDT(6);
stm32_putreg(regval, STM32_OTGFS_GUSBCFG);
}
@@ -3508,6 +3539,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
FAR struct stm32_usbdev_s *priv = &g_otgfsdev;
uint32_t regval;
+ uint32_t reserved;
usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0);
@@ -3519,14 +3551,21 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
* some interrupts (like RXFLVL) will generate additional interrupting
* events.
*/
-
for (; ; )
{
/* Get the set of pending, un-masked interrupts */
regval = stm32_getreg(STM32_OTGFS_GINTSTS);
+ reserved = (regval & OTGFS_GINT_RESERVED);
regval &= stm32_getreg(STM32_OTGFS_GINTMSK);
+ /* With out modifying the reserved bits, acknowledge all
+ * **Writable** pending irqs we will service below
+ */
+
+ stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32_OTGFS_GINTSTS);
+
+
/* Break out of the loop when there are no further pending (and
* unmasked) interrupts to be processes.
*/
@@ -3545,7 +3584,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval);
stm32_epout_interrupt(priv);
- stm32_putreg(OTGFS_GINT_OEP, STM32_OTGFS_GINTSTS);
}
/* IN endpoint interrupt. The core sets this bit to indicate that
@@ -3556,7 +3594,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval);
stm32_epin_interrupt(priv);
- stm32_putreg(OTGFS_GINT_IEP, STM32_OTGFS_GINTSTS);
}
/* Host/device mode mismatch error interrupt */
@@ -3565,7 +3602,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_MMIS) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval);
- stm32_putreg(OTGFS_GINT_MMIS, STM32_OTGFS_GINTSTS);
}
#endif
@@ -3575,7 +3611,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval);
stm32_resumeinterrupt(priv);
- stm32_putreg(OTGFS_GINT_WKUP, STM32_OTGFS_GINTSTS);
}
/* USB suspend interrupt */
@@ -3584,7 +3619,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval);
stm32_suspendinterrupt(priv);
- stm32_putreg(OTGFS_GINT_USBSUSP, STM32_OTGFS_GINTSTS);
}
/* Start of frame interrupt */
@@ -3593,7 +3627,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_SOF) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval);
- stm32_putreg(OTGFS_GINT_SOF, STM32_OTGFS_GINTSTS);
}
#endif
@@ -3605,7 +3638,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval);
stm32_rxinterrupt(priv);
- stm32_putreg(OTGFS_GINT_RXFLVL, STM32_OTGFS_GINTSTS);
}
/* USB reset interrupt */
@@ -3618,7 +3650,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
stm32_usbreset(priv);
usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0);
- stm32_putreg(OTGFS_GINT_USBRST, STM32_OTGFS_GINTSTS);
return OK;
}
@@ -3628,7 +3659,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval);
stm32_enuminterrupt(priv);
- stm32_putreg(OTGFS_GINT_ENUMDNE, STM32_OTGFS_GINTSTS);
}
/* Incomplete isochronous IN transfer interrupt. When the core finds
@@ -3642,7 +3672,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval);
stm32_isocininterrupt(priv);
- stm32_putreg(OTGFS_GINT_IISOIXFR, STM32_OTGFS_GINTSTS);
}
/* Incomplete isochronous OUT transfer. For isochronous OUT
@@ -3659,7 +3688,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval);
stm32_isocoutinterrupt(priv);
- stm32_putreg(OTGFS_GINT_IISOOXFR, STM32_OTGFS_GINTSTS);
}
#endif
@@ -3670,7 +3698,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval);
stm32_sessioninterrupt(priv);
- stm32_putreg(OTGFS_GINT_SRQ, STM32_OTGFS_GINTSTS);
}
/* OTG interrupt */
@@ -3679,7 +3706,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval);
stm32_otginterrupt(priv);
- stm32_putreg(OTGFS_GINT_OTG, STM32_OTGFS_GINTSTS);
}
#endif
}
@@ -5338,7 +5364,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Clear any pending interrupts */
- stm32_putreg(0xbfffffff, STM32_OTGFS_GINTSTS);
+ regval = stm32_getreg(STM32_OTGFS_GINTSTS);
+ regval &= OTGFS_GINT_RESERVED;
+ stm32_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS);
/* Enable the interrupts in the INTMSK */
diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c
index a32caaea517..5eda6c08ccc 100644
--- a/arch/arm/src/stm32/stm32_pwr.c
+++ b/arch/arm/src/stm32/stm32_pwr.c
@@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
- * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
* Authors: Uros Platise
* Gregory Nutt
*
@@ -40,21 +40,19 @@
************************************************************************************/
#include
-#include
#include
#include
#include
+#include
+#include
+
#include "up_arch.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32_PWR)
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
/************************************************************************************
* Private Functions
************************************************************************************/
@@ -85,46 +83,70 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
+ * NOTE: Reference counting is used in order to supported nested calls to this
+ * function. As a consequence, every call to stm32_pwr_enablebkp(true) must
+ * be followed by a matching call to stm32_pwr_enablebkp(false).
+ *
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
- * True: The backup domain was previously writable.
+ * None
*
************************************************************************************/
-bool stm32_pwr_enablebkp(bool writable)
+void stm32_pwr_enablebkp(bool writable)
{
+ static uint16_t writable_counter = 0;
+ irqstate_t flags;
uint16_t regval;
bool waswritable;
+ bool wait = false;
+
+ flags = enter_critical_section();
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
waswritable = ((regval & PWR_CR_DBP) != 0);
+ if (writable)
+ {
+ DEBUGASSERT(writable_counter < UINT16_MAX);
+ writable_counter++;
+ }
+ else if (writable_counter > 0)
+ {
+ writable_counter--;
+ }
+
/* Enable or disable the ability to write */
- if (waswritable && !writable)
+ if (waswritable && writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
- else if (!waswritable && writable)
+ else if (!waswritable && writable_counter > 0)
{
/* Enable backup domain access */
regval |= PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
+ wait = true;
+ }
+
+ leave_critical_section(flags);
+
+ if (wait)
+ {
/* Enable does not happen right away */
up_udelay(4);
}
-
- return waswritable;
}
/************************************************************************************
diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h
index 49e0657f552..344834c0678 100644
--- a/arch/arm/src/stm32/stm32_pwr.h
+++ b/arch/arm/src/stm32/stm32_pwr.h
@@ -73,15 +73,19 @@ extern "C"
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
+ * NOTE: Reference counting is used in order to supported nested calls to this
+ * function. As a consequence, every call to stm32_pwr_enablebkp(true) must
+ * be followed by a matching call to stm32_pwr_enablebkp(false).
+ *
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
- * True: The backup domain was previously writable.
+ * None
*
************************************************************************************/
-bool stm32_pwr_enablebkp(bool writable);
+void stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg
diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c
index 553f76e73df..cf3c115d639 100644
--- a/arch/arm/src/stm32/stm32_rcc.c
+++ b/arch/arm/src/stm32/stm32_rcc.c
@@ -128,7 +128,7 @@ static inline void rcc_resetbkp(void)
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC)
{
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
@@ -137,7 +137,7 @@ static inline void rcc_resetbkp(void)
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
}
#else
diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c
index da8f57db592..d27a8ddd387 100644
--- a/arch/arm/src/stm32/stm32_rtcc.c
+++ b/arch/arm/src/stm32/stm32_rtcc.c
@@ -222,7 +222,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -261,7 +261,7 @@ static inline void rtc_wprlock(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/************************************************************************************
@@ -598,7 +598,7 @@ int up_rtc_initialize(void)
regval = getreg32(RTC_MAGIC_REG);
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@@ -673,7 +673,7 @@ int up_rtc_initialize(void)
}
}
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the RTC
@@ -724,11 +724,17 @@ int up_rtc_initialize(void)
* backup data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
+
+ /* Disable write access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ */
+
+ stm32_pwr_enablebkp(false);
}
else
{
@@ -740,12 +746,6 @@ int up_rtc_initialize(void)
rtc_dumpregs("Did resume");
}
- /* Disable write access to the backup domain (RTC registers, RTC backup
- * data registers and backup SRAM).
- */
-
- (void)stm32_pwr_enablebkp(false);
-
if (ret != OK && nretry > 0)
{
rtcinfo("setup/resume ran %d times and failed with %d\n",
diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c
index 8156de0a604..137e7344a03 100644
--- a/arch/arm/src/stm32/stm32_rtcounter.c
+++ b/arch/arm/src/stm32/stm32_rtcounter.c
@@ -377,7 +377,7 @@ int up_rtc_initialize(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* Set access to the peripheral, enable the backup domain (BKP) and the lower
* power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the
@@ -428,7 +428,7 @@ int up_rtc_initialize(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
return OK;
}
@@ -605,7 +605,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
/* Enable write access to the backup domain */
flags = enter_critical_section();
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* Then write the broken out values to the RTC counter and BKP overflow register
* (hi-res mode only)
@@ -625,7 +625,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
putreg16(regvals.ovf, RTC_TIMEMSB_REG);
#endif
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
leave_critical_section(flags);
return OK;
}
diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c
index 807a13127f2..d82b6eb3cb1 100644
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
@@ -132,8 +132,8 @@
/* DMA channel configuration */
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32L15XX)
+#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \
+ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC )
# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC )
# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS )
@@ -182,7 +182,7 @@ struct stm32_spidev_s
sem_t exclsem; /* Held while chip is selected for mutual exclusion */
uint32_t frequency; /* Requested clock frequency */
uint32_t actual; /* Actual clock frequency */
- int8_t nbits; /* Width of word in bits (8 or 16) */
+ uint8_t nbits; /* Width of word in bits (4 through 16) */
uint8_t mode; /* Mode 0,1,2,3 */
};
@@ -193,8 +193,15 @@ struct stm32_spidev_s
/* Helpers */
static inline uint16_t spi_getreg(FAR struct stm32_spidev_s *priv, uint8_t offset);
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+static inline uint8_t spi_getreg8(FAR struct stm32_spidev_s *priv, uint8_t offset);
+#endif
static inline void spi_putreg(FAR struct stm32_spidev_s *priv, uint8_t offset,
uint16_t value);
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+static inline void spi_putreg8(FAR struct stm32_spidev_s *priv, uint8_t offset,
+ uint8_t value);
+#endif
static inline uint16_t spi_readword(FAR struct stm32_spidev_s *priv);
static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t byte);
static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv);
@@ -222,6 +229,10 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev,
+ spi_hwfeatures_t features);
+#endif
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd);
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords);
@@ -249,7 +260,7 @@ static const struct spi_ops_s g_sp1iops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0, /* Not supported */
+ .hwfeatures = spi_hwfeatures,
#endif
.status = stm32_spi1status,
#ifdef CONFIG_SPI_CMDDATA
@@ -292,6 +303,9 @@ static const struct spi_ops_s g_sp2iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi2status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi2cmddata,
@@ -333,6 +347,9 @@ static const struct spi_ops_s g_sp3iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi3status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi3cmddata,
@@ -374,6 +391,9 @@ static const struct spi_ops_s g_sp4iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi4status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi4cmddata,
@@ -415,6 +435,9 @@ static const struct spi_ops_s g_sp5iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi5status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi5cmddata,
@@ -456,6 +479,9 @@ static const struct spi_ops_s g_sp6iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi6status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi3cmddata,
@@ -489,10 +515,6 @@ static struct stm32_spidev_s g_spi6dev =
};
#endif
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
/************************************************************************************
* Private Functions
************************************************************************************/
@@ -517,6 +539,28 @@ static inline uint16_t spi_getreg(FAR struct stm32_spidev_s *priv, uint8_t offse
return getreg16(priv->spibase + offset);
}
+/************************************************************************************
+ * Name: spi_getreg8
+ *
+ * Description:
+ * Get the contents of the SPI register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ *
+ * Returned Value:
+ * The contents of the 16-bit register
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+static inline uint8_t spi_getreg8(FAR struct stm32_spidev_s *priv, uint8_t offset)
+{
+ return getreg8(priv->spibase + offset);
+}
+#endif
+
/************************************************************************************
* Name: spi_putreg
*
@@ -538,6 +582,30 @@ static inline void spi_putreg(FAR struct stm32_spidev_s *priv, uint8_t offset, u
putreg16(value, priv->spibase + offset);
}
+/************************************************************************************
+ * Name: spi_putreg8
+ *
+ * Description:
+ * Write an 8-bit value to the SPI register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ * value - the 16-bit value to be written
+ *
+ * Returned Value:
+ * The contents of the 16-bit register
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+static inline void spi_putreg8(FAR struct stm32_spidev_s *priv, uint8_t offset,
+ uint8_t value)
+{
+ putreg8(value, priv->spibase + offset);
+}
+#endif
+
/************************************************************************************
* Name: spi_readword
*
@@ -560,7 +628,27 @@ static inline uint16_t spi_readword(FAR struct stm32_spidev_s *priv)
/* Then return the received byte */
- return spi_getreg(priv, STM32_SPI_DR_OFFSET);
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+ /* "When the data frame size fits into one byte (less than or equal to 8 bits),
+ * data packing is used automatically when any read or write 16-bit access is
+ * performed on the SPIx_DR register. The double data frame pattern is handled
+ * in parallel in this case. At first, the SPI operates using the pattern
+ * stored in the LSB of the accessed word, then with the other half stored in
+ * the MSB.... The receiver then has to access both data frames by a single
+ * 16-bit read of SPIx_DR as a response to this single RXNE event. The RxFIFO
+ * threshold setting and the following read access must be always kept aligned
+ * at the receiver side, as data can be lost if it is not in line."
+ */
+
+ if (priv->nbits < 9)
+ {
+ return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET);
+ }
+ else
+#endif
+ {
+ return spi_getreg(priv, STM32_SPI_DR_OFFSET);
+ }
}
/************************************************************************************
@@ -584,9 +672,35 @@ static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t word)
while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0);
- /* Then send the byte */
+ /* Then send the word */
- spi_putreg(priv, STM32_SPI_DR_OFFSET, word);
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+ /* "When the data frame size fits into one byte (less than or equal to 8 bits),
+ * data packing is used automatically when any read or write 16-bit access is
+ * performed on the SPIx_DR register. The double data frame pattern is handled
+ * in parallel in this case. At first, the SPI operates using the pattern
+ * stored in the LSB of the accessed word, then with the other half stored in
+ * the MSB...
+ *
+ * "A specific problem appears if an odd number of such "fit into one byte"
+ * data frames must be handled. On the transmitter side, writing the last
+ * data frame of any odd sequence with an 8-bit access to SPIx_DR is enough.
+ * ..."
+ *
+ * REVISIT: "...The receiver has to change the Rx_FIFO threshold level for the
+ * last data frame received in the odd sequence of frames in order to generate
+ * the RXNE event."
+ */
+
+ if (priv->nbits < 9)
+ {
+ spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word);
+ }
+ else
+#endif
+ {
+ spi_putreg(priv, STM32_SPI_DR_OFFSET, word);
+ }
}
/************************************************************************************
@@ -605,7 +719,11 @@ static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t word)
static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv)
{
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+ return (priv->nbits > 8);
+#else
return ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_DFF) != 0);
+#endif
}
/************************************************************************************
@@ -878,7 +996,8 @@ static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv)
*
************************************************************************************/
-static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits)
+static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16_t setbits,
+ uint16_t clrbits)
{
uint16_t cr1;
cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET);
@@ -887,6 +1006,34 @@ static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16_t setbits, uin
spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1);
}
+/************************************************************************************
+ * Name: spi_modifycr2
+ *
+ * Description:
+ * Clear and set bits in the CR2 register
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+static void spi_modifycr2(FAR struct stm32_spidev_s *priv, uint16_t setbits,
+ uint16_t clrbits)
+{
+ uint16_t cr2;
+ cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
+ cr2 &= ~clrbits;
+ cr2 |= setbits;
+ spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2);
+}
+#endif
+
/************************************************************************************
* Name: spi_lock
*
@@ -1132,28 +1279,48 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+ /* Yes... Set CR2 appropriately */
+ /* Set the number of bits (valid range 4-16) */
+
+ if (nbits < 4 || nbits > 16)
+ {
+ spierr("ERROR: nbits out of range: %d\n", nbits);
+ return;
+ }
+
+ clrbits = SPI_CR2_DS_MASK;
+ setbits = SPI_CR2_DS(nbits);
+
+ /* If nbits is <=8, then we are in byte mode and FRXTH must be set
+ * (else, transaction will not complete).
+ */
+
+ if (nbits < 9)
+ {
+ setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
+ }
+ else
+ {
+ clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
+ }
+
+ spi_modifycr1(priv, 0, SPI_CR1_SPE);
+ spi_modifycr2(priv, setbits, clrbits);
+ spi_modifycr1(priv, SPI_CR1_SPE, 0);
+#else
/* Yes... Set CR1 appropriately */
switch (nbits)
{
- case -8:
- setbits = SPI_CR1_LSBFIRST;
- clrbits = SPI_CR1_DFF;
- break;
-
case 8:
setbits = 0;
- clrbits = SPI_CR1_DFF | SPI_CR1_LSBFIRST;
- break;
-
- case -16:
- setbits = SPI_CR1_DFF | SPI_CR1_LSBFIRST;
- clrbits = 0;
+ clrbits = SPI_CR1_DFF;
break;
case 16:
setbits = SPI_CR1_DFF;
- clrbits = SPI_CR1_LSBFIRST;
+ clrbits = 0;
break;
default:
@@ -1163,13 +1330,65 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
-
+#endif
/* Save the selection so the subsequence re-configurations will be faster */
priv->nbits = nbits;
}
}
+/****************************************************************************
+ * Name: spi_hwfeatures
+ *
+ * Description:
+ * Set hardware-specific feature flags.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * features - H/W feature flags
+ *
+ * Returned Value:
+ * Zero (OK) if the selected H/W features are enabled; A negated errno
+ * value if any H/W feature is not supportable.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
+{
+#ifdef CONFIG_SPI_BITORDER
+ FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
+ uint16_t setbits;
+ uint16_t clrbits;
+
+ spiinfo("features=%08x\n", features);
+
+ /* Transfer data LSB first? */
+
+ if ((features & HWFEAT_LSBFIRST) != 0)
+ {
+ setbits = SPI_CR1_LSBFIRST;
+ clrbits = 0;
+ }
+ else
+ {
+ setbits = 0;
+ clrbits = SPI_CR1_LSBFIRST;
+ }
+
+ spi_modifycr1(priv, 0, SPI_CR1_SPE);
+ spi_modifycr1(priv, setbits, clrbits);
+ spi_modifycr1(priv, SPI_CR1_SPE, 0);
+
+ /* Other H/W features are not supported */
+
+ return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
+#else
+ return -ENOSYS;
+#endif
+}
+#endif
+
/************************************************************************************
* Name: spi_send
*
@@ -1213,6 +1432,9 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* Description:
* Exchange a block of data on SPI without using DMA
*
+ * REVISIT: This function could be much more efficient by exploiting (1) RX and TX
+ * FIFOs and (2) the STM32 F3 data packing.
+ *
* Input Parameters:
* dev - Device-specific state data
* txbuffer - A pointer to the buffer of data to be sent
@@ -1446,6 +1668,25 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
uint16_t setbits;
uint16_t clrbits;
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+ /* Configure CR1 and CR2. Default configuration:
+ * Mode 0: CR1.CPHA=0 and CR1.CPOL=0
+ * Master: CR1.MSTR=1
+ * 8-bit: CR2.DS=7
+ * MSB tranmitted first: CR1.LSBFIRST=0
+ * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 (prevents MODF error)
+ * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) and CR1.RXONLY=0
+ */
+
+ clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST |
+ SPI_CR1_RXONLY | SPI_CR1_CRCL | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE;
+ setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
+ spi_modifycr1(priv, setbits, clrbits);
+
+ clrbits = SPI_CR2_DS_MASK;
+ setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */
+ spi_modifycr2(priv, setbits, clrbits);
+#else
/* Configure CR1. Default configuration:
* Mode 0: CPHA=0 and CPOL=0
* Master: MSTR=1
@@ -1459,6 +1700,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
SPI_CR1_RXONLY | SPI_CR1_DFF | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE;
setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
spi_modifycr1(priv, setbits, clrbits);
+#endif
priv->frequency = 0;
priv->nbits = 8;
@@ -1494,7 +1736,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
priv->txdma = stm32_dmachannel(priv->txch);
DEBUGASSERT(priv->rxdma && priv->txdma);
- spi_putreg(priv, STM32_SPI_CR2_OFFSET, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+ spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0);
#endif
/* Enable spi */
@@ -1671,7 +1913,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
else
#endif
{
- spierr("ERROR: Unsupbused SPI bus: %d\n", bus);
+ spierr("ERROR: Unsupported SPI bus: %d\n", bus);
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/stm32/stm32_tickless.c
index eadef5ce90d..82d7a593d25 100644
--- a/arch/arm/src/stm32/stm32_tickless.c
+++ b/arch/arm/src/stm32/stm32_tickless.c
@@ -272,11 +272,44 @@ void up_timer_initialize(void)
*
****************************************************************************/
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+
int up_timer_gettime(FAR struct timespec *ts)
{
return stm32_freerun_counter(&g_tickless.freerun, ts);
}
+#else
+
+int up_timer_getcounter(FAR uint64_t *cycles)
+{
+ return stm32_freerun_counter(&g_tickless.freerun, cycles);
+}
+
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
+/****************************************************************************
+ * Name: up_timer_getmask
+ *
+ * Description:
+ * To be provided
+ *
+ * Input Parameters:
+ * mask - Location to return the 64-bit mask
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_CLOCK_TIMEKEEPING
+void up_timer_getmask(FAR uint64_t *mask)
+{
+ DEBUGASSERT(mask != NULL);
+ *mask = g_tickless.freerun.counter_mask;
+}
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
/****************************************************************************
* Name: up_timer_cancel
*
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 7145243b894..cbd136d6d53 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -263,7 +263,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -302,7 +302,7 @@ static inline void rtc_wprlock(void)
* data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/****************************************************************************
@@ -892,7 +892,7 @@ int up_rtc_initialize(void)
regval = getreg32(RTC_MAGIC_REG);
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@@ -972,7 +972,7 @@ int up_rtc_initialize(void)
}
}
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the RTC
@@ -1023,11 +1023,17 @@ int up_rtc_initialize(void)
* backup data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
+
+ /* Disable write access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ */
+
+ stm32_pwr_enablebkp(false);
}
else
{
@@ -1039,12 +1045,6 @@ int up_rtc_initialize(void)
rtc_dumpregs("Did resume");
}
- /* Disable write access to the backup domain (RTC registers, RTC backup
- * data registers and backup SRAM).
- */
-
- (void)stm32_pwr_enablebkp(false);
-
if (ret != OK && nretry > 0)
{
rtcinfo("setup/resume ran %d times and failed with %d\n",
diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/chip/stm32_otg.h
index 874dd265639..aca73655523 100644
--- a/arch/arm/src/stm32f7/chip/stm32_otg.h
+++ b/arch/arm/src/stm32f7/chip/stm32_otg.h
@@ -324,21 +324,20 @@
#define OTG_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
#define OTG_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
#define OTG_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
- /* Bits 8-9: Reserved, must be kept at reset value */
+#define OTG_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */
#define OTG_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
#define OTG_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
#define OTG_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
#define OTG_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
#define OTG_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
#define OTG_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
- /* Bits 16 Reserved, must be kept at reset value */
-#define OTG_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */
+#define OTG_GINT_RES1617 (3 << 16) /* Bits 16-17 Reserved, must be kept at reset value */
#define OTG_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
#define OTG_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
#define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
- /* Bit 22: Reserved, must be kept at reset value */
+#define OTG_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */
#define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c
index 74d7721ed60..9caceb48427 100644
--- a/arch/arm/src/stm32f7/stm32_ethernet.c
+++ b/arch/arm/src/stm32f7/stm32_ethernet.c
@@ -1788,12 +1788,6 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
continue;
}
-#ifdef CONFIG_NET_PKT
- /* When packet sockets are enabled, feed the frame into the packet tap */
-
- pkt_input(&priv->dev);
-#endif
-
/* We only accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv4
diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c
index 6a776976e2d..f06175cb5bf 100644
--- a/arch/arm/src/stm32f7/stm32_otgdev.c
+++ b/arch/arm/src/stm32f7/stm32_otgdev.c
@@ -209,6 +209,29 @@
# error "FIFO allocations exceed FIFO memory size"
#endif
+#define OTG_GINT_RESERVED (OTG_GINT_RES89 | \
+ OTG_GINT_RES1617 | \
+ OTG_GINT_RES22)
+
+
+#define OTG_GINT_RC_W1 (OTG_GINT_MMIS | \
+ OTG_GINT_SOF | \
+ OTG_GINT_ESUSP | \
+ OTG_GINT_USBSUSP | \
+ OTG_GINT_USBRST | \
+ OTG_GINT_ENUMDNE | \
+ OTG_GINT_ISOODRP | \
+ OTG_GINT_EOPF | \
+ OTG_GINT_IISOIXFR | \
+ OTG_GINT_IISOOXFR | \
+ OTG_GINT_RSTDET | \
+ OTG_GINT_LPMINT | \
+ OTG_GINT_CIDSCHG | \
+ OTG_GINT_DISC | \
+ OTG_GINT_SRQ | \
+ OTG_GINT_WKUP)
+
+
/* Debug ***********************************************************************/
/* Trace error codes */
@@ -871,7 +894,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- llerr("...\n");
+ uinfo("...\n");
}
return val;
@@ -888,7 +911,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- llerr("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -900,7 +923,7 @@ static uint32_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- llerr("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -918,7 +941,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- llerr("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -3171,12 +3194,6 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
int bcnt;
int epphy;
- /* Disable the Rx status queue level interrupt */
-
- regval = stm32_getreg(STM32_OTG_GINTMSK);
- regval &= ~OTG_GINT_RXFLVL;
- stm32_putreg(regval, STM32_OTG_GINTMSK);
-
/* Get the status from the top of the FIFO */
regval = stm32_getreg(STM32_OTG_GRXSTSP);
@@ -3251,6 +3268,22 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
case OTG_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
+
+ /* Now that the Setup Phase is complete if it was an OUT enable
+ * the endpoint
+ * (Doing this here prevents the loss of the first FIFO word)
+ */
+
+ if (priv->ep0state == EP0STATE_SETUP_OUT)
+ {
+
+ /* Clear NAKSTS so that we can receive the data */
+
+ regval = stm32_getreg(STM32_OTG_DOEPCTL(0));
+ regval |= OTG_DOEPCTL0_CNAK;
+ stm32_putreg(regval, STM32_OTG_DOEPCTL(0));
+
+ }
}
break;
@@ -3286,14 +3319,6 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
- /* Clear NAKSTS so that we can receive the data */
-
- regval = stm32_getreg(STM32_OTG_DOEPCTL(0));
- regval |= OTG_DOEPCTL0_CNAK;
- stm32_putreg(regval, STM32_OTG_DOEPCTL(0));
-
- /* Wait for the data phase. */
-
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
@@ -3316,11 +3341,6 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
}
}
- /* Enable the Rx Status Queue Level interrupt */
-
- regval = stm32_getreg(STM32_OTG_GINTMSK);
- regval |= OTG_GINT_RXFLVL;
- stm32_putreg(regval, STM32_OTG_GINTMSK);
}
/****************************************************************************
@@ -3343,7 +3363,7 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTG_GUSBCFG);
regval &= ~OTG_GUSBCFG_TRDT_MASK;
- regval |= OTG_GUSBCFG_TRDT(5);
+ regval |= OTG_GUSBCFG_TRDT(6);
stm32_putreg(regval, STM32_OTG_GUSBCFG);
}
@@ -3562,6 +3582,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
FAR struct stm32_usbdev_s *priv = &g_otghsdev;
uint32_t regval;
+ uint32_t reserved;
usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0);
@@ -3579,8 +3600,15 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
/* Get the set of pending, un-masked interrupts */
regval = stm32_getreg(STM32_OTG_GINTSTS);
+ reserved = (regval & OTG_GINT_RESERVED);
regval &= stm32_getreg(STM32_OTG_GINTMSK);
+ /* With out modifying the reserved bits, acknowledge all
+ * **Writable** pending irqs we will service below
+ */
+
+ stm32_putreg(((regval | reserved) & OTG_GINT_RC_W1), STM32_OTG_GINTSTS);
+
/* Break out of the loop when there are no further pending (and
* unmasked) interrupts to be processes.
*/
@@ -3599,7 +3627,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval);
stm32_epout_interrupt(priv);
- stm32_putreg(OTG_GINT_OEP, STM32_OTG_GINTSTS);
}
/* IN endpoint interrupt. The core sets this bit to indicate that
@@ -3610,7 +3637,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval);
stm32_epin_interrupt(priv);
- stm32_putreg(OTG_GINT_IEP, STM32_OTG_GINTSTS);
}
/* Host/device mode mismatch error interrupt */
@@ -3619,7 +3645,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
if ((regval & OTG_GINT_MMIS) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval);
- stm32_putreg(OTG_GINT_MMIS, STM32_OTG_GINTSTS);
}
#endif
@@ -3629,7 +3654,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval);
stm32_resumeinterrupt(priv);
- stm32_putreg(OTG_GINT_WKUP, STM32_OTG_GINTSTS);
}
/* USB suspend interrupt */
@@ -3638,7 +3662,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval);
stm32_suspendinterrupt(priv);
- stm32_putreg(OTG_GINT_USBSUSP, STM32_OTG_GINTSTS);
}
/* Start of frame interrupt */
@@ -3647,7 +3670,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
if ((regval & OTG_GINT_SOF) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval);
- stm32_putreg(OTG_GINT_SOF, STM32_OTG_GINTSTS);
}
#endif
@@ -3659,12 +3681,11 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval);
stm32_rxinterrupt(priv);
- stm32_putreg(OTG_GINT_RXFLVL, STM32_OTG_GINTSTS);
}
/* USB reset interrupt */
- if ((regval & OTG_GINT_USBRST) != 0)
+ if ((regval & (OTG_GINT_USBRST | OTG_GINT_RSTDET)) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval);
@@ -3672,7 +3693,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
stm32_usbreset(priv);
usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0);
- stm32_putreg(OTG_GINT_USBRST, STM32_OTG_GINTSTS);
return OK;
}
@@ -3682,7 +3702,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval);
stm32_enuminterrupt(priv);
- stm32_putreg(OTG_GINT_ENUMDNE, STM32_OTG_GINTSTS);
}
/* Incomplete isochronous IN transfer interrupt. When the core finds
@@ -3696,7 +3715,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval);
stm32_isocininterrupt(priv);
- stm32_putreg(OTG_GINT_IISOIXFR, STM32_OTG_GINTSTS);
}
/* Incomplete isochronous OUT transfer. For isochronous OUT
@@ -3713,7 +3731,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval);
stm32_isocoutinterrupt(priv);
- stm32_putreg(OTG_GINT_IISOOXFR, STM32_OTG_GINTSTS);
}
#endif
@@ -3724,7 +3741,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval);
stm32_sessioninterrupt(priv);
- stm32_putreg(OTG_GINT_SRQ, STM32_OTG_GINTSTS);
}
/* OTG interrupt */
@@ -3733,7 +3749,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval);
stm32_otginterrupt(priv);
- stm32_putreg(OTG_GINT_OTG, STM32_OTG_GINTSTS);
}
#endif
}
@@ -5425,7 +5440,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Clear any pending interrupts */
- stm32_putreg(0xbfffffff, STM32_OTG_GINTSTS);
+ regval = stm32_getreg(STM32_OTG_GINTSTS);
+ regval &= OTG_GINT_RESERVED;
+ stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS);
#if defined(CONFIG_STM32F7_OTGHS)
/* Disable the ULPI Clock enable in RCC AHB1 Register. This must
diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c
index 78b5eeaf06b..4b0fceba541 100644
--- a/arch/arm/src/stm32f7/stm32_spi.c
+++ b/arch/arm/src/stm32f7/stm32_spi.c
@@ -203,6 +203,10 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev,
+ spi_hwfeatures_t features);
+#endif
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd);
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords);
@@ -230,7 +234,7 @@ static const struct spi_ops_s g_sp1iops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0, /* Not supported */
+ .hwfeatures = spi_hwfeatures,
#endif
.status = stm32_spi1status,
#ifdef CONFIG_SPI_CMDDATA
@@ -273,6 +277,9 @@ static const struct spi_ops_s g_sp2iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi2status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi2cmddata,
@@ -314,6 +321,9 @@ static const struct spi_ops_s g_sp3iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi3status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi3cmddata,
@@ -355,6 +365,9 @@ static const struct spi_ops_s g_sp4iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi4status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi4cmddata,
@@ -396,6 +409,9 @@ static const struct spi_ops_s g_sp5iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi5status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi5cmddata,
@@ -437,6 +453,9 @@ static const struct spi_ops_s g_sp6iops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32_spi6status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32_spi3cmddata,
@@ -1219,10 +1238,8 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
- uint16_t setbitscr1;
- uint16_t clrbitscr1;
- uint16_t setbitscr2;
- uint16_t clrbitscr2;
+ uint16_t setbits;
+ uint16_t clrbits;
int savbits = nbits;
spiinfo("nbits=%d\n", nbits);
@@ -1231,21 +1248,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
- /* Yes... Set CR1/2 appropriately */
- /* Negative sign means LSBFIRST, set this in CR1*/
-
- if (nbits < 0)
- {
- setbitscr1 = SPI_CR1_LSBFIRST;
- clrbitscr1 = 0;
- nbits = -nbits;
- }
- else
- {
- setbitscr1 = 0;
- clrbitscr1 = SPI_CR1_LSBFIRST;
- }
-
+ /* Yes... Set CR2 appropriately */
/* Set the number of bits (valid range 4-16) */
if (nbits < 4 || nbits > 16)
@@ -1253,8 +1256,8 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
return;
}
- clrbitscr2 = SPI_CR2_DS_MASK;
- setbitscr2 = SPI_CR2_DS_VAL(nbits);
+ clrbits = SPI_CR2_DS_MASK;
+ setbits = SPI_CR2_DS_VAL(nbits);
/* If nbits is <=8, then we are in byte mode and FRXTH shall be set
* (else, transaction will not complete).
@@ -1262,16 +1265,15 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits < 9)
{
- setbitscr2 |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
+ setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
}
else
{
- clrbitscr2 |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
+ clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
}
spi_modifycr1(priv, 0, SPI_CR1_SPE);
- spi_modifycr1(priv, setbitscr1, clrbitscr1);
- spi_modifycr2(priv, setbitscr2, clrbitscr2);
+ spi_modifycr2(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
/* Save the selection so the subsequence re-configurations will be faster */
@@ -1280,6 +1282,61 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
}
}
+/****************************************************************************
+ * Name: spi_hwfeatures
+ *
+ * Description:
+ * Set hardware-specific feature flags.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * features - H/W feature flags
+ *
+ * Returned Value:
+ * Zero (OK) if the selected H/W features are enabled; A negated errno
+ * value if any H/W feature is not supportable.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
+{
+#ifdef CONFIG_SPI_BITORDER
+ FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
+ uint16_t setbitscr1;
+ uint16_t clrbitscr1;
+ uint16_t setbitscr2;
+ uint16_t clrbitscr2;
+ int savbits = nbits;
+
+ spiinfo("features=%08x\n", features);
+
+ /* Transfer data LSB first? */
+
+ if ((features & HWFEAT_LSBFIRST) != 0)
+ {
+ setbits = SPI_CR1_LSBFIRST;
+ clrbits = 0;
+ }
+ else
+ {
+ setbits = 0;
+ clrbits = SPI_CR1_LSBFIRST;
+ }
+
+ spi_modifycr1(priv, 0, SPI_CR1_SPE);
+ spi_modifycr1(priv, setbits, clrbits);
+ spi_modifycr1(priv, SPI_CR1_SPE, 0);
+
+ /* Other H/W features are not supported */
+
+ return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
+#else
+ return -ENOSYS;
+#endif
+}
+#endif
+
/************************************************************************************
* Name: spi_send
*
diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs
index 33a5e0a5ba8..d265c2a4f51 100644
--- a/arch/arm/src/stm32l4/Make.defs
+++ b/arch/arm/src/stm32l4/Make.defs
@@ -125,7 +125,7 @@ CHIP_CSRCS += stm32l4_tickless.c
endif
ifeq ($(CONFIG_STM32L4_ONESHOT),y)
-CHIP_CSRCS += stm32l4_oneshot.c
+CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_STM32L4_FREERUN),y)
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
index 2d8d431285f..39065c05706 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
+++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
@@ -61,408 +61,408 @@
/* Register Offsets *********************************************************************************/
/* Core global control and status registers */
-#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
-#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
-#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
-#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
-#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
-#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
-#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
-#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
-#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
-#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
-#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
-#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
-#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
-#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
-#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */
-#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
-#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
-#define STM32_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */
-#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
+#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
+#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
+#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
+#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
+#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
+#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
+#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
+#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
+#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
+#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
+#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
+#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
+#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
+#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
+#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */
+#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
+#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
+#define STM32L4_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */
+#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
-#define STM32_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
-#define STM32_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */
-#define STM32_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */
-#define STM32_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */
-#define STM32_OTGFS_DIEPTXF4_OFFSET 0x0110 /* Device IN endpoint transmit FIFO4 size register */
-#define STM32_OTGFS_DIEPTXF5_OFFSET 0x0114 /* Device IN endpoint transmit FIFO5 size register */
+#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
+#define STM32L4_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */
+#define STM32L4_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */
+#define STM32L4_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */
+#define STM32L4_OTGFS_DIEPTXF4_OFFSET 0x0110 /* Device IN endpoint transmit FIFO4 size register */
+#define STM32L4_OTGFS_DIEPTXF5_OFFSET 0x0114 /* Device IN endpoint transmit FIFO5 size register */
/* Host-mode control and status registers */
-#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
-#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
-#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
-#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
-#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
-#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
-#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
+#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
+#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
+#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
+#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
+#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
+#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
+#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
-#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
-#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
-#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
-#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
-#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
+#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
+#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
+#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
+#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
+#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
-#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
-#define STM32_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */
-#define STM32_OTGFS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */
-#define STM32_OTGFS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */
-#define STM32_OTGFS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */
-#define STM32_OTGFS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */
-#define STM32_OTGFS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */
-#define STM32_OTGFS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */
-#define STM32_OTGFS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */
-#define STM32_OTGFS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */
-#define STM32_OTGFS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */
-#define STM32_OTGFS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */
-#define STM32_OTGFS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */
+#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
+#define STM32L4_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */
+#define STM32L4_OTGFS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */
+#define STM32L4_OTGFS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */
+#define STM32L4_OTGFS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */
+#define STM32L4_OTGFS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */
+#define STM32L4_OTGFS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */
+#define STM32L4_OTGFS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */
+#define STM32L4_OTGFS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */
+#define STM32L4_OTGFS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */
+#define STM32L4_OTGFS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */
+#define STM32L4_OTGFS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */
+#define STM32L4_OTGFS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */
-#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
-#define STM32_OTGFS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */
-#define STM32_OTGFS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */
-#define STM32_OTGFS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */
-#define STM32_OTGFS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */
-#define STM32_OTGFS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */
-#define STM32_OTGFS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */
-#define STM32_OTGFS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */
-#define STM32_OTGFS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */
-#define STM32_OTGFS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */
-#define STM32_OTGFS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */
-#define STM32_OTGFS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */
-#define STM32_OTGFS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */
+#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
+#define STM32L4_OTGFS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */
+#define STM32L4_OTGFS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */
+#define STM32L4_OTGFS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */
+#define STM32L4_OTGFS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */
+#define STM32L4_OTGFS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */
+#define STM32L4_OTGFS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */
+#define STM32L4_OTGFS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */
+#define STM32L4_OTGFS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */
+#define STM32L4_OTGFS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */
+#define STM32L4_OTGFS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */
+#define STM32L4_OTGFS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */
+#define STM32L4_OTGFS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */
-#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
-#define STM32_OTGFS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */
-#define STM32_OTGFS_HCINTMSK11_OFFSET 0x066c /* Host channel-11 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
+#define STM32L4_OTGFS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */
+#define STM32L4_OTGFS_HCINTMSK11_OFFSET 0x066c /* Host channel-11 interrupt mask register */
-#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
-#define STM32_OTGFS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */
-#define STM32_OTGFS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */
-#define STM32_OTGFS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */
-#define STM32_OTGFS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */
-#define STM32_OTGFS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */
-#define STM32_OTGFS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */
-#define STM32_OTGFS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */
-#define STM32_OTGFS_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */
-#define STM32_OTGFS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */
-#define STM32_OTGFS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */
-#define STM32_OTGFS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */
-#define STM32_OTGFS_HCTSIZ11_OFFSET 0x0670 /* Host channel-11 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
+#define STM32L4_OTGFS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */
+#define STM32L4_OTGFS_HCTSIZ11_OFFSET 0x0670 /* Host channel-11 interrupt register */
/* Device-mode control and status registers */
-#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
-#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
-#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
-#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
-#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
-#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
-#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
-#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
-#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
-#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
+#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
+#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
+#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
+#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
+#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
+#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
+#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
+#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
+#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
+#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
-#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
-#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
-#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
-#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
-#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
+#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
+#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
+#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
+#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
+#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
-#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
-#define STM32_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */
-#define STM32_OTGFS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */
-#define STM32_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */
-#define STM32_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */
-#define STM32_OTGFS_DIEPCTL4_OFFSET 0x0980 /* Device control IN endpoint 4 control register */
-#define STM32_OTGFS_DIEPCTL5_OFFSET 0x09a0 /* Device control IN endpoint 4 control register */
+#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
+#define STM32L4_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */
+#define STM32L4_OTGFS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */
+#define STM32L4_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */
+#define STM32L4_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */
+#define STM32L4_OTGFS_DIEPCTL4_OFFSET 0x0980 /* Device control IN endpoint 4 control register */
+#define STM32L4_OTGFS_DIEPCTL5_OFFSET 0x09a0 /* Device control IN endpoint 4 control register */
-#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
-#define STM32_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */
-#define STM32_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */
-#define STM32_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */
-#define STM32_OTGFS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */
-#define STM32_OTGFS_DIEPINT4_OFFSET 0x0988 /* Device endpoint-3 interrupt register */
-#define STM32_OTGFS_DIEPINT5_OFFSET 0x09a8 /* Device endpoint-3 interrupt register */
+#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
+#define STM32L4_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */
+#define STM32L4_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */
+#define STM32L4_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */
+#define STM32L4_OTGFS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */
+#define STM32L4_OTGFS_DIEPINT4_OFFSET 0x0988 /* Device endpoint-3 interrupt register */
+#define STM32L4_OTGFS_DIEPINT5_OFFSET 0x09a8 /* Device endpoint-3 interrupt register */
-#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
-#define STM32_OTGFS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */
-#define STM32_OTGFS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */
-#define STM32_OTGFS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */
-#define STM32_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */
-#define STM32_OTGFS_DIEPTSIZ4_OFFSET 0x0990 /* Device IN endpoint 3 transfer size register */
-#define STM32_OTGFS_DIEPTSIZ5_OFFSET 0x09b0 /* Device IN endpoint 3 transfer size register */
+#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
+#define STM32L4_OTGFS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */
+#define STM32L4_OTGFS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */
+#define STM32L4_OTGFS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */
+#define STM32L4_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */
+#define STM32L4_OTGFS_DIEPTSIZ4_OFFSET 0x0990 /* Device IN endpoint 3 transfer size register */
+#define STM32L4_OTGFS_DIEPTSIZ5_OFFSET 0x09b0 /* Device IN endpoint 3 transfer size register */
-#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
-#define STM32_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */
-#define STM32_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */
-#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */
-#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */
-#define STM32_OTGFS_DTXFSTS4_OFFSET 0x0998 /* Device OUT endpoint-3 TxFIFO status register */
-#define STM32_OTGFS_DTXFSTS5_OFFSET 0x09b8 /* Device OUT endpoint-3 TxFIFO status register */
+#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
+#define STM32L4_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */
+#define STM32L4_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */
+#define STM32L4_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */
+#define STM32L4_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */
+#define STM32L4_OTGFS_DTXFSTS4_OFFSET 0x0998 /* Device OUT endpoint-3 TxFIFO status register */
+#define STM32L4_OTGFS_DTXFSTS5_OFFSET 0x09b8 /* Device OUT endpoint-3 TxFIFO status register */
-#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
-#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
-#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
-#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
+#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
+#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
+#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
+#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
-#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
-#define STM32_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */
-#define STM32_OTGFS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */
-#define STM32_OTGFS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */
-#define STM32_OTGFS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */
-#define STM32_OTGFS_DOEPCTL4_OFFSET 0x00b80 /* Device OUT endpoint 4 control register */
-#define STM32_OTGFS_DOEPCTL5_OFFSET 0x00ba0 /* Device OUT endpoint 5 control register */
+#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
+#define STM32L4_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */
+#define STM32L4_OTGFS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */
+#define STM32L4_OTGFS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */
+#define STM32L4_OTGFS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */
+#define STM32L4_OTGFS_DOEPCTL4_OFFSET 0x00b80 /* Device OUT endpoint 4 control register */
+#define STM32L4_OTGFS_DOEPCTL5_OFFSET 0x00ba0 /* Device OUT endpoint 5 control register */
-#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
-#define STM32_OTGFS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */
-#define STM32_OTGFS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */
-#define STM32_OTGFS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */
-#define STM32_OTGFS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */
-#define STM32_OTGFS_DOEPINT4_OFFSET 0x00b88 /* Device endpoint-4 interrupt register */
-#define STM32_OTGFS_DOEPINT5_OFFSET 0x00ba8 /* Device endpoint-5 interrupt register */
+#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
+#define STM32L4_OTGFS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */
+#define STM32L4_OTGFS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */
+#define STM32L4_OTGFS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */
+#define STM32L4_OTGFS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */
+#define STM32L4_OTGFS_DOEPINT4_OFFSET 0x00b88 /* Device endpoint-4 interrupt register */
+#define STM32L4_OTGFS_DOEPINT5_OFFSET 0x00ba8 /* Device endpoint-5 interrupt register */
-#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
-#define STM32_OTGFS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */
-#define STM32_OTGFS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */
-#define STM32_OTGFS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */
-#define STM32_OTGFS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */
-#define STM32_OTGFS_DOEPTSIZ4_OFFSET 0x00b90 /* Device OUT endpoint-4 transfer size register */
-#define STM32_OTGFS_DOEPTSIZ5_OFFSET 0x00bb0 /* Device OUT endpoint-5 transfer size register */
+#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
+#define STM32L4_OTGFS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */
+#define STM32L4_OTGFS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */
+#define STM32L4_OTGFS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */
+#define STM32L4_OTGFS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */
+#define STM32L4_OTGFS_DOEPTSIZ4_OFFSET 0x00b90 /* Device OUT endpoint-4 transfer size register */
+#define STM32L4_OTGFS_DOEPTSIZ5_OFFSET 0x00bb0 /* Device OUT endpoint-5 transfer size register */
/* Power and clock gating registers */
-#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
+#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
/* Data FIFO (DFIFO) access registers */
-#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
-#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
+#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
+#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
-#define STM32_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */
-#define STM32_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */
+#define STM32L4_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */
+#define STM32L4_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */
-#define STM32_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */
-#define STM32_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */
+#define STM32L4_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */
+#define STM32L4_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */
-#define STM32_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */
-#define STM32_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */
+#define STM32L4_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */
+#define STM32L4_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */
-#define STM32_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */
-#define STM32_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */
+#define STM32L4_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */
+#define STM32L4_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */
-#define STM32_OTGFS_DFIFO_DEP4_OFFSET 0x5000 /* 0x5000-0x5ffc Device IN/OUT Endpoint 4 DFIFO Write/Read Access */
-#define STM32_OTGFS_DFIFO_HCH4_OFFSET 0x5000 /* 0x5000-0x5ffc Host OUT/IN Channel 4 DFIFO Read/Write Access */
+#define STM32L4_OTGFS_DFIFO_DEP4_OFFSET 0x5000 /* 0x5000-0x5ffc Device IN/OUT Endpoint 4 DFIFO Write/Read Access */
+#define STM32L4_OTGFS_DFIFO_HCH4_OFFSET 0x5000 /* 0x5000-0x5ffc Host OUT/IN Channel 4 DFIFO Read/Write Access */
-#define STM32_OTGFS_DFIFO_DEP5_OFFSET 0x6000 /* 0x6000-0x6ffc Device IN/OUT Endpoint 5 DFIFO Write/Read Access */
-#define STM32_OTGFS_DFIFO_HCH5_OFFSET 0x6000 /* 0x6000-0x6ffc Host OUT/IN Channel 5 DFIFO Read/Write Access */
+#define STM32L4_OTGFS_DFIFO_DEP5_OFFSET 0x6000 /* 0x6000-0x6ffc Device IN/OUT Endpoint 5 DFIFO Write/Read Access */
+#define STM32L4_OTGFS_DFIFO_HCH5_OFFSET 0x6000 /* 0x6000-0x6ffc Host OUT/IN Channel 5 DFIFO Read/Write Access */
/* Register Addresses *******************************************************************************/
-#define STM32_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET)
-#define STM32_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET)
-#define STM32_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET)
-#define STM32_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET)
-#define STM32_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET)
-#define STM32_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET)
-#define STM32_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET)
-#define STM32_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET)
-#define STM32_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET)
-#define STM32_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET)
-#define STM32_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET)
-#define STM32_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET)
-#define STM32_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET)
-#define STM32_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET)
-#define STM32_OTGFS_CID (STM32L4_OTGFS_BASE+STM32_OTGFS_CID_OFFSET)
-#define STM32_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET)
-#define STM32_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET)
-#define STM32_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET)
-#define STM32_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET)
+#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET)
+#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET)
+#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET)
+#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET)
+#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET)
+#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET)
+#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET)
+#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET)
+#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET)
+#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET)
+#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET)
+#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET)
+#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET)
+#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET)
+#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET)
+#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET)
+#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET)
+#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET)
+#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET)
-#define STM32_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n))
-#define STM32_OTGFS_DIEPTXF1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF1_OFFSET)
-#define STM32_OTGFS_DIEPTXF2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF2_OFFSET)
-#define STM32_OTGFS_DIEPTXF3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF3_OFFSET)
-#define STM32_OTGFS_DIEPTXF4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF4_OFFSET)
-#define STM32_OTGFS_DIEPTXF5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTXF5_OFFSET)
+#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n))
+#define STM32L4_OTGFS_DIEPTXF1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF1_OFFSET)
+#define STM32L4_OTGFS_DIEPTXF2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF2_OFFSET)
+#define STM32L4_OTGFS_DIEPTXF3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF3_OFFSET)
+#define STM32L4_OTGFS_DIEPTXF4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF4_OFFSET)
+#define STM32L4_OTGFS_DIEPTXF5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF5_OFFSET)
/* Host-mode control and status registers */
-#define STM32_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET)
-#define STM32_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET)
-#define STM32_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET)
-#define STM32_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET)
-#define STM32_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET)
-#define STM32_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET)
-#define STM32_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET)
+#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET)
+#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET)
+#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET)
+#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET)
+#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET)
+#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET)
+#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET)
-#define STM32_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n))
+#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n))
-#define STM32_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n))
-#define STM32_OTGFS_HCCHAR0 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR0_OFFSET)
-#define STM32_OTGFS_HCCHAR1 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR1_OFFSET)
-#define STM32_OTGFS_HCCHAR2 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR2_OFFSET)
-#define STM32_OTGFS_HCCHAR3 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR3_OFFSET)
-#define STM32_OTGFS_HCCHAR4 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR4_OFFSET)
-#define STM32_OTGFS_HCCHAR5 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR5_OFFSET)
-#define STM32_OTGFS_HCCHAR6 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR6_OFFSET)
-#define STM32_OTGFS_HCCHAR7 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR7_OFFSET)
-#define STM32_OTGFS_HCCHAR8 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR8_OFFSET)
-#define STM32_OTGFS_HCCHAR9 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR9_OFFSET)
-#define STM32_OTGFS_HCCHAR10 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR10_OFFSET)
-#define STM32_OTGFS_HCCHAR11 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCCHAR11_OFFSET)
+#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n))
+#define STM32L4_OTGFS_HCCHAR0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR0_OFFSET)
+#define STM32L4_OTGFS_HCCHAR1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR1_OFFSET)
+#define STM32L4_OTGFS_HCCHAR2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR2_OFFSET)
+#define STM32L4_OTGFS_HCCHAR3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR3_OFFSET)
+#define STM32L4_OTGFS_HCCHAR4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR4_OFFSET)
+#define STM32L4_OTGFS_HCCHAR5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR5_OFFSET)
+#define STM32L4_OTGFS_HCCHAR6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR6_OFFSET)
+#define STM32L4_OTGFS_HCCHAR7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR7_OFFSET)
+#define STM32L4_OTGFS_HCCHAR8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR8_OFFSET)
+#define STM32L4_OTGFS_HCCHAR9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR9_OFFSET)
+#define STM32L4_OTGFS_HCCHAR10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR10_OFFSET)
+#define STM32L4_OTGFS_HCCHAR11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR11_OFFSET)
-#define STM32_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n))
-#define STM32_OTGFS_HCINT0 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT0_OFFSET)
-#define STM32_OTGFS_HCINT1 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT1_OFFSET)
-#define STM32_OTGFS_HCINT2 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT2_OFFSET)
-#define STM32_OTGFS_HCINT3 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT3_OFFSET)
-#define STM32_OTGFS_HCINT4 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT4_OFFSET)
-#define STM32_OTGFS_HCINT5 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT5_OFFSET)
-#define STM32_OTGFS_HCINT6 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT6_OFFSET)
-#define STM32_OTGFS_HCINT7 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT7_OFFSET)
-#define STM32_OTGFS_HCINT8 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT8_OFFSET)
-#define STM32_OTGFS_HCINT9 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT9_OFFSET)
-#define STM32_OTGFS_HCINT10 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT10_OFFSET)
-#define STM32_OTGFS_HCINT11 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINT11_OFFSET)
+#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n))
+#define STM32L4_OTGFS_HCINT0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT0_OFFSET)
+#define STM32L4_OTGFS_HCINT1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT1_OFFSET)
+#define STM32L4_OTGFS_HCINT2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT2_OFFSET)
+#define STM32L4_OTGFS_HCINT3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT3_OFFSET)
+#define STM32L4_OTGFS_HCINT4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT4_OFFSET)
+#define STM32L4_OTGFS_HCINT5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT5_OFFSET)
+#define STM32L4_OTGFS_HCINT6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT6_OFFSET)
+#define STM32L4_OTGFS_HCINT7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT7_OFFSET)
+#define STM32L4_OTGFS_HCINT8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT8_OFFSET)
+#define STM32L4_OTGFS_HCINT9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT9_OFFSET)
+#define STM32L4_OTGFS_HCINT10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT10_OFFSET)
+#define STM32L4_OTGFS_HCINT11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT11_OFFSET)
-#define STM32_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n))
-#define STM32_OTGFS_HCINTMSK0 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK0_OFFSET)
-#define STM32_OTGFS_HCINTMSK1 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK1_OFFSET)
-#define STM32_OTGFS_HCINTMSK2 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK2_OFFSET)
-#define STM32_OTGFS_HCINTMSK3 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK3_OFFSET)
-#define STM32_OTGFS_HCINTMSK4 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK4_OFFSET)
-#define STM32_OTGFS_HCINTMSK5 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK5_OFFSET)
-#define STM32_OTGFS_HCINTMSK6 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK6_OFFSET)
-#define STM32_OTGFS_HCINTMSK7 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK7_OFFSET)
-#define STM32_OTGFS_HCINTMSK8 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK8_OFFSET)
-#define STM32_OTGFS_HCINTMSK9 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK9_OFFSET)
-#define STM32_OTGFS_HCINTMSK10 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK10_OFFSET)
-#define STM32_OTGFS_HCINTMSK11 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCINTMSK11_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n))
+#define STM32L4_OTGFS_HCINTMSK0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK0_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK1_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK2_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK3_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK4_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK5_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK6_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK7_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK8_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK9_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK10_OFFSET)
+#define STM32L4_OTGFS_HCINTMSK11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK11_OFFSET)
-#define STM32_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n))
-#define STM32_OTGFS_HCTSIZ0 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ0_OFFSET)
-#define STM32_OTGFS_HCTSIZ1 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ1_OFFSET)
-#define STM32_OTGFS_HCTSIZ2 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ2_OFFSET)
-#define STM32_OTGFS_HCTSIZ3 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ3_OFFSET)
-#define STM32_OTGFS_HCTSIZ4 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ4_OFFSET)
-#define STM32_OTGFS_HCTSIZ5 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ5_OFFSET)
-#define STM32_OTGFS_HCTSIZ6 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ6_OFFSET)
-#define STM32_OTGFS_HCTSIZ7 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ7_OFFSET)
-#define STM32_OTGFS_HCTSIZ8 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ8_OFFSET)
-#define STM32_OTGFS_HCTSIZ9 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ9_OFFSET)
-#define STM32_OTGFS_HCTSIZ10 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ10_OFFSET)
-#define STM32_OTGFS_HCTSIZ11 (STM32L4_OTGFS_BASE+STM32_OTGFS_HCTSIZ11_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n))
+#define STM32L4_OTGFS_HCTSIZ0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ0_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ1_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ2_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ3_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ4_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ5_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ6_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ7_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ8_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ9_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ10_OFFSET)
+#define STM32L4_OTGFS_HCTSIZ11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ11_OFFSET)
/* Device-mode control and status registers */
-#define STM32_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET)
-#define STM32_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET)
-#define STM32_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET)
-#define STM32_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET)
-#define STM32_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET)
-#define STM32_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET)
-#define STM32_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET)
-#define STM32_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET)
-#define STM32_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET)
-#define STM32_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
+#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET)
+#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET)
+#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET)
+#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET)
+#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET)
+#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET)
+#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET)
+#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET)
+#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET)
+#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET)
-#define STM32_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
+#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n))
-#define STM32_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
-#define STM32_OTGFS_DIEPCTL0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL0_OFFSET)
-#define STM32_OTGFS_DIEPCTL1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL1_OFFSET)
-#define STM32_OTGFS_DIEPCTL2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL2_OFFSET)
-#define STM32_OTGFS_DIEPCTL3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL3_OFFSET)
-#define STM32_OTGFS_DIEPCTL4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL4_OFFSET)
-#define STM32_OTGFS_DIEPCTL5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPCTL5_OFFSET)
+#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n))
+#define STM32L4_OTGFS_DIEPCTL0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL0_OFFSET)
+#define STM32L4_OTGFS_DIEPCTL1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL1_OFFSET)
+#define STM32L4_OTGFS_DIEPCTL2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL2_OFFSET)
+#define STM32L4_OTGFS_DIEPCTL3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL3_OFFSET)
+#define STM32L4_OTGFS_DIEPCTL4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL4_OFFSET)
+#define STM32L4_OTGFS_DIEPCTL5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL5_OFFSET)
-#define STM32_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n))
-#define STM32_OTGFS_DIEPINT0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT0_OFFSET)
-#define STM32_OTGFS_DIEPINT1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT1_OFFSET)
-#define STM32_OTGFS_DIEPINT2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT2_OFFSET)
-#define STM32_OTGFS_DIEPINT3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT3_OFFSET)
-#define STM32_OTGFS_DIEPINT4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT4_OFFSET)
-#define STM32_OTGFS_DIEPINT5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPINT5_OFFSET)
+#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n))
+#define STM32L4_OTGFS_DIEPINT0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT0_OFFSET)
+#define STM32L4_OTGFS_DIEPINT1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT1_OFFSET)
+#define STM32L4_OTGFS_DIEPINT2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT2_OFFSET)
+#define STM32L4_OTGFS_DIEPINT3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT3_OFFSET)
+#define STM32L4_OTGFS_DIEPINT4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT4_OFFSET)
+#define STM32L4_OTGFS_DIEPINT5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT5_OFFSET)
-#define STM32_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n))
-#define STM32_OTGFS_DIEPTSIZ0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ0_OFFSET)
-#define STM32_OTGFS_DIEPTSIZ1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ1_OFFSET)
-#define STM32_OTGFS_DIEPTSIZ2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ2_OFFSET)
-#define STM32_OTGFS_DIEPTSIZ3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ3_OFFSET)
-#define STM32_OTGFS_DIEPTSIZ4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ4_OFFSET)
-#define STM32_OTGFS_DIEPTSIZ5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ5_OFFSET)
+#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n))
+#define STM32L4_OTGFS_DIEPTSIZ0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ0_OFFSET)
+#define STM32L4_OTGFS_DIEPTSIZ1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ1_OFFSET)
+#define STM32L4_OTGFS_DIEPTSIZ2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ2_OFFSET)
+#define STM32L4_OTGFS_DIEPTSIZ3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ3_OFFSET)
+#define STM32L4_OTGFS_DIEPTSIZ4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ4_OFFSET)
+#define STM32L4_OTGFS_DIEPTSIZ5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ5_OFFSET)
-#define STM32_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n))
-#define STM32_OTGFS_DTXFSTS0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS0_OFFSET)
-#define STM32_OTGFS_DTXFSTS1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS1_OFFSET)
-#define STM32_OTGFS_DTXFSTS2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS2_OFFSET)
-#define STM32_OTGFS_DTXFSTS3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS3_OFFSET)
-#define STM32_OTGFS_DTXFSTS4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS4_OFFSET)
-#define STM32_OTGFS_DTXFSTS5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DTXFSTS5_OFFSET)
+#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n))
+#define STM32L4_OTGFS_DTXFSTS0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS0_OFFSET)
+#define STM32L4_OTGFS_DTXFSTS1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS1_OFFSET)
+#define STM32L4_OTGFS_DTXFSTS2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS2_OFFSET)
+#define STM32L4_OTGFS_DTXFSTS3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS3_OFFSET)
+#define STM32L4_OTGFS_DTXFSTS4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS4_OFFSET)
+#define STM32L4_OTGFS_DTXFSTS5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS5_OFFSET)
-#define STM32_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n))
+#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n))
-#define STM32_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n))
-#define STM32_OTGFS_DOEPCTL0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL0_OFFSET)
-#define STM32_OTGFS_DOEPCTL1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL1_OFFSET)
-#define STM32_OTGFS_DOEPCTL2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL2_OFFSET)
-#define STM32_OTGFS_DOEPCTL3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL3_OFFSET)
-#define STM32_OTGFS_DOEPCTL4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL4_OFFSET)
-#define STM32_OTGFS_DOEPCTL5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPCTL5_OFFSET)
+#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n))
+#define STM32L4_OTGFS_DOEPCTL0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL0_OFFSET)
+#define STM32L4_OTGFS_DOEPCTL1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL1_OFFSET)
+#define STM32L4_OTGFS_DOEPCTL2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL2_OFFSET)
+#define STM32L4_OTGFS_DOEPCTL3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL3_OFFSET)
+#define STM32L4_OTGFS_DOEPCTL4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL4_OFFSET)
+#define STM32L4_OTGFS_DOEPCTL5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL5_OFFSET)
-#define STM32_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n))
-#define STM32_OTGFS_DOEPINT0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT0_OFFSET)
-#define STM32_OTGFS_DOEPINT1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT1_OFFSET)
-#define STM32_OTGFS_DOEPINT2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT2_OFFSET)
-#define STM32_OTGFS_DOEPINT3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT3_OFFSET)
-#define STM32_OTGFS_DOEPINT4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT4_OFFSET)
-#define STM32_OTGFS_DOEPINT5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPINT5_OFFSET)
+#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n))
+#define STM32L4_OTGFS_DOEPINT0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT0_OFFSET)
+#define STM32L4_OTGFS_DOEPINT1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT1_OFFSET)
+#define STM32L4_OTGFS_DOEPINT2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT2_OFFSET)
+#define STM32L4_OTGFS_DOEPINT3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT3_OFFSET)
+#define STM32L4_OTGFS_DOEPINT4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT4_OFFSET)
+#define STM32L4_OTGFS_DOEPINT5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT5_OFFSET)
-#define STM32_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n))
-#define STM32_OTGFS_DOEPTSIZ0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ0_OFFSET)
-#define STM32_OTGFS_DOEPTSIZ1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ1_OFFSET)
-#define STM32_OTGFS_DOEPTSIZ2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ2_OFFSET)
-#define STM32_OTGFS_DOEPTSIZ3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ3_OFFSET)
-#define STM32_OTGFS_DOEPTSIZ4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ4_OFFSET)
-#define STM32_OTGFS_DOEPTSIZ5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ5_OFFSET)
+#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n))
+#define STM32L4_OTGFS_DOEPTSIZ0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ0_OFFSET)
+#define STM32L4_OTGFS_DOEPTSIZ1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ1_OFFSET)
+#define STM32L4_OTGFS_DOEPTSIZ2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ2_OFFSET)
+#define STM32L4_OTGFS_DOEPTSIZ3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ3_OFFSET)
+#define STM32L4_OTGFS_DOEPTSIZ4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ4_OFFSET)
+#define STM32L4_OTGFS_DOEPTSIZ5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ5_OFFSET)
/* Power and clock gating registers */
-#define STM32_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET)
+#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET)
/* Data FIFO (DFIFO) access registers */
-#define STM32_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n))
-#define STM32_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n))
+#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n))
+#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n))
-#define STM32_OTGFS_DFIFO_DEP0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP0_OFFSET)
-#define STM32_OTGFS_DFIFO_HCH0 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH0_OFFSET)
+#define STM32L4_OTGFS_DFIFO_DEP0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP0_OFFSET)
+#define STM32L4_OTGFS_DFIFO_HCH0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH0_OFFSET)
-#define STM32_OTGFS_DFIFO_DEP1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP1_OFFSET)
-#define STM32_OTGFS_DFIFO_HCH1 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH1_OFFSET)
+#define STM32L4_OTGFS_DFIFO_DEP1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP1_OFFSET)
+#define STM32L4_OTGFS_DFIFO_HCH1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH1_OFFSET)
-#define STM32_OTGFS_DFIFO_DEP2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP2_OFFSET)
-#define STM32_OTGFS_DFIFO_HCH2 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH2_OFFSET)
+#define STM32L4_OTGFS_DFIFO_DEP2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP2_OFFSET)
+#define STM32L4_OTGFS_DFIFO_HCH2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH2_OFFSET)
-#define STM32_OTGFS_DFIFO_DEP3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP3_OFFSET)
-#define STM32_OTGFS_DFIFO_HCH3 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH3_OFFSET)
+#define STM32L4_OTGFS_DFIFO_DEP3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP3_OFFSET)
+#define STM32L4_OTGFS_DFIFO_HCH3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH3_OFFSET)
-#define STM32_OTGFS_DFIFO_DEP4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP4_OFFSET)
-#define STM32_OTGFS_DFIFO_HCH4 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH4_OFFSET)
+#define STM32L4_OTGFS_DFIFO_DEP4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP4_OFFSET)
+#define STM32L4_OTGFS_DFIFO_HCH4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH4_OFFSET)
-#define STM32_OTGFS_DFIFO_DEP5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP5_OFFSET)
-#define STM32_OTGFS_DFIFO_HCH5 (STM32L4_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH5_OFFSET)
+#define STM32L4_OTGFS_DFIFO_DEP5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP5_OFFSET)
+#define STM32L4_OTGFS_DFIFO_HCH5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH5_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* Core global control and status registers */
@@ -555,20 +555,20 @@
#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
- /* Bits 8-9: Reserved, must be kept at reset value */
+#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */
#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
- /* Bits 16-17: Reserved, must be kept at reset value */
+#define OTGFS_GINT_RES1617 (3 << 16) /* Bits 16-17: Reserved, must be kept at reset value */
#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
- /* Bit 22: Reserved, must be kept at reset value */
+#define OTGFS_GINT_RES22 (1 << 22) /* Bit 22: Reserved, must be kept at reset value */
#define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h
index 743652bf49b..86800f6b352 100644
--- a/arch/arm/src/stm32l4/stm32l4_oneshot.h
+++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h
@@ -118,7 +118,7 @@ extern "C"
****************************************************************************/
int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan,
- uint16_t resolution);
+ uint16_t resolution);
/****************************************************************************
* Name: stm32l4_oneshot_max_delay
@@ -128,7 +128,8 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, uint64_t *usec);
+int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot,
+ uint64_t *usec);
/****************************************************************************
* Name: stm32l4_oneshot_start
@@ -151,8 +152,8 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, uint64_t *usec)
****************************************************************************/
int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot,
- oneshot_handler_t handler, void *arg,
- const struct timespec *ts);
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts);
/****************************************************************************
* Name: stm32l4_oneshot_cancel
@@ -179,7 +180,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot,
****************************************************************************/
int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot,
- struct timespec *ts);
+ struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c
new file mode 100644
index 00000000000..8a73130dc7d
--- /dev/null
+++ b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c
@@ -0,0 +1,345 @@
+/****************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "stm32l4_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct stm32l4_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct stm32l4_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct stm32l4_oneshot_s oneshot; /* STM32-specific oneshot state */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void stm32l4_oneshot_handler(void *arg);
+
+static int stm32l4_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int stm32l4_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int stm32l4_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = stm32l4_max_delay,
+ .start = stm32l4_start,
+ .cancel = stm32l4_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32l4_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when stm32l4_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void stm32l4_oneshot_handler(void *arg)
+{
+ FAR struct stm32l4_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32l4_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * stm32l4_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: stm32l4_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int stm32l4_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct stm32l4_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32l4_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = stm32l4_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: stm32l4_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int stm32l4_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct stm32l4_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32l4_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = stm32l4_oneshot_start(&priv->oneshot,
+ stm32l4_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: stm32l4_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: stm32l4_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int stm32l4_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct stm32l4_oneshot_lowerhalf_s *priv =
+ (FAR struct stm32l4_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = stm32l4_oneshot_cancel(&priv->oneshot, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: stm32l4_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct stm32l4_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct stm32l4_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct stm32l4_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained STM32 oneshot timer */
+
+ ret = stm32l4_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: stm32l4_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c
index 2ade38444f6..06bab127d35 100644
--- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c
+++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c
@@ -225,6 +225,27 @@
# error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range"
#endif
+#define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \
+ OTGFS_GINT_RES1617 | \
+ OTGFS_GINT_RES22)
+
+#define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \
+ OTGFS_GINT_SOF | \
+ OTGFS_GINT_ESUSP | \
+ OTGFS_GINT_USBSUSP | \
+ OTGFS_GINT_USBRST | \
+ OTGFS_GINT_ENUMDNE | \
+ OTGFS_GINT_ISOODRP | \
+ OTGFS_GINT_EOPF | \
+ OTGFS_GINT_IISOIXFR | \
+ OTGFS_GINT_IISOOXFR | \
+ OTGFS_GINT_RSTDET | \
+ OTGFS_GINT_LPMINT | \
+ OTGFS_GINT_CIDSCHG | \
+ OTGFS_GINT_DISC | \
+ OTGFS_GINT_SRQ | \
+ OTGFS_GINT_WKUP)
+
/* Debug ***********************************************************************/
/* Trace error codes */
@@ -3221,154 +3242,163 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
/* Disable the Rx status queue level interrupt */
- regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK);
- regval &= ~OTGFS_GINT_RXFLVL;
- stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK);
-
- /* Get the status from the top of the FIFO */
-
- regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP);
-
- /* Decode status fields */
-
- epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
-
- if (epphy < STM32L4_NENDPOINTS)
+ while(0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
{
- privep = &priv->epout[epphy];
- /* Handle the RX event according to the packet status field */
+ /* Get the status from the top of the FIFO */
- switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
- {
- /* Global OUT NAK. This indicate that the global OUT NAK bit has taken
- * effect.
- *
- * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
- * Care.
+ regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP);
+
+ /* Decode status fields */
+
+ epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
+
+ /* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP register
+ * happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
+ * All of which provide out of range indexes for epout[epphy]
*/
- case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
- {
- usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0);
- }
- break;
+ if (epphy < STM32L4_NENDPOINTS)
+ {
+ privep = &priv->epout[epphy];
- /* OUT data packet received.
- *
- * PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
- * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
- */
+ /* Handle the RX event according to the packet status field */
- case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
+ switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
- usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), epphy);
- bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
- if (bcnt > 0)
- {
- stm32l4_epout_receive(privep, bcnt);
+ /* Global OUT NAK. This indicate that the global OUT NAK bit has taken
+ * effect.
+ *
+ * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
+ * Care.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
+ {
+ usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0);
+ }
+ break;
+
+ /* OUT data packet received.
+ *
+ * PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
+ * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
+ {
+ usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), epphy);
+ bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
+ if (bcnt > 0)
+ {
+ stm32l4_epout_receive(privep, bcnt);
+ }
+ }
+ break;
+
+ /* OUT transfer completed. This indicates that an OUT data transfer for
+ * the specified OUT endpoint has completed. After this entry is popped
+ * from the receive FIFO, the core asserts a Transfer Completed interrupt
+ * on the specified OUT endpoint.
+ *
+ * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
+ * which the data transfer is complete, DPID = Don't Care.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
+ {
+ usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy);
+ }
+ break;
+
+ /* SETUP transaction completed. This indicates that the Setup stage for
+ * the specified endpoint has completed and the Data stage has started.
+ * After this entry is popped from the receive FIFO, the core asserts a
+ * Setup interrupt on the specified control OUT endpoint (triggers an
+ * interrupt).
+ *
+ * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
+ * DPID = Don't Care.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
+ {
+ usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy);
+
+ /* Now that the Setup Phase is complete if it was an OUT enable
+ * the endpoint
+ * (Doing this here prevents the loss of the first FIFO word)
+ */
+
+ if (priv->ep0state == EP0STATE_SETUP_OUT)
+ {
+
+ /* Clear NAKSTS so that we can receive the data */
+
+ regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL0);
+ regval |= OTGFS_DOEPCTL0_CNAK;
+ stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL0);
+
}
+ }
+ break;
+
+ /* SETUP data packet received. This indicates that a SETUP packet for the
+ * specified endpoint is now available for reading from the receive FIFO.
+ *
+ * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
+ */
+
+ case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
+ {
+ uint16_t datlen;
+
+ usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), epphy);
+
+ /* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
+ * the last one overwrites the previous setup packets and only that
+ * last SETUP packet will be processed.
+ */
+
+ stm32l4_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
+ USB_SIZEOF_CTRLREQ);
+
+ /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
+ * then we need to wait for the completion of the data phase to
+ * process the setup command. If it is an IN SETUP packet, then
+ * we must processing the command BEFORE we enter the DATA phase.
+ *
+ * If the data associated with the OUT SETUP packet is zero length,
+ * then, of course, we don't need to wait.
+ */
+
+ datlen = GETUINT16(priv->ctrlreq.len);
+ if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
+ {
+ /* Wait for the data phase. */
+
+ priv->ep0state = EP0STATE_SETUP_OUT;
+ }
+ else
+ {
+ /* We can process the setup data as soon as SETUP done word is
+ * popped of the RxFIFO.
+ */
+
+ priv->ep0state = EP0STATE_SETUP_READY;
+ }
+ }
+ break;
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS),
+ (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
+ }
+ break;
}
- break;
-
- /* OUT transfer completed. This indicates that an OUT data transfer for
- * the specified OUT endpoint has completed. After this entry is popped
- * from the receive FIFO, the core asserts a Transfer Completed interrupt
- * on the specified OUT endpoint.
- *
- * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
- * which the data transfer is complete, DPID = Don't Care.
- */
-
- case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
- {
- usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy);
- }
- break;
-
- /* SETUP transaction completed. This indicates that the Setup stage for
- * the specified endpoint has completed and the Data stage has started.
- * After this entry is popped from the receive FIFO, the core asserts a
- * Setup interrupt on the specified control OUT endpoint (triggers an
- * interrupt).
- *
- * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
- * DPID = Don't Care.
- */
-
- case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
- {
- usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy);
- }
- break;
-
- /* SETUP data packet received. This indicates that a SETUP packet for the
- * specified endpoint is now available for reading from the receive FIFO.
- *
- * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
- */
-
- case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
- {
- uint16_t datlen;
-
- usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), epphy);
-
- /* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
- * the last one overwrites the previous setup packets and only that
- * last SETUP packet will be processed.
- */
-
- stm32l4_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
- USB_SIZEOF_CTRLREQ);
-
- /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
- * then we need to wait for the completion of the data phase to
- * process the setup command. If it is an IN SETUP packet, then
- * we must processing the command BEFORE we enter the DATA phase.
- *
- * If the data associated with the OUT SETUP packet is zero length,
- * then, of course, we don't need to wait.
- */
-
- datlen = GETUINT16(priv->ctrlreq.len);
- if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
- {
- /* Clear NAKSTS so that we can receive the data */
-
- regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL0);
- regval |= OTGFS_DOEPCTL0_CNAK;
- stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL0);
-
- /* Wait for the data phase. */
-
- priv->ep0state = EP0STATE_SETUP_OUT;
- }
- else
- {
- /* We can process the setup data as soon as SETUP done word is
- * popped of the RxFIFO.
- */
-
- priv->ep0state = EP0STATE_SETUP_READY;
- }
- }
- break;
-
- default:
- {
- usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS),
- (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
- }
- break;
- }
+ }
}
-
- /* Enable the Rx Status Queue Level interrupt */
-
- regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK);
- regval |= OTGFS_GINT_RXFLVL;
- stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK);
}
/****************************************************************************
@@ -3391,7 +3421,7 @@ static inline void stm32l4_enuminterrupt(FAR struct stm32l4_usbdev_s *priv)
regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG);
regval &= ~OTGFS_GUSBCFG_TRDT_MASK;
- regval |= OTGFS_GUSBCFG_TRDT(5);
+ regval |= OTGFS_GUSBCFG_TRDT(6);
stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG);
}
@@ -3605,32 +3635,38 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
/* At present, there is only a single OTG FS device support. Hence it is
* pre-allocated as g_otgfsdev. However, in most code, the private data
* structure will be referenced using the 'priv' pointer (rather than the
- * global data) in order to simplify any future support for multiple
- * devices.
+ * global data) in order to simplify any future support for multiple devices.
*/
FAR struct stm32l4_usbdev_s *priv = &g_otgfsdev;
uint32_t regval;
+ uint32_t reserved;
usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), 0);
/* Assure that we are in device mode */
- DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) ==
- OTGFS_GINTSTS_DEVMODE);
+ DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE);
/* Get the state of all enabled interrupts. We will do this repeatedly
* some interrupts (like RXFLVL) will generate additional interrupting
* events.
*/
-
for (; ; )
{
/* Get the set of pending, un-masked interrupts */
regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS);
+ reserved = (regval & OTGFS_GINT_RESERVED);
regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK);
+ /* With out modifying the reserved bits, acknowledge all
+ * **Writable** pending irqs we will service below
+ */
+
+ stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32L4_OTGFS_GINTSTS);
+
+
/* Break out of the loop when there are no further pending (and
* unmasked) interrupts to be processes.
*/
@@ -3639,7 +3675,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
break;
}
-
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), (uint16_t)regval);
/* OUT endpoint interrupt. The core sets this bit to indicate that an
@@ -3650,7 +3685,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), (uint16_t)regval);
stm32l4_epout_interrupt(priv);
- stm32l4_putreg(OTGFS_GINT_OEP, STM32L4_OTGFS_GINTSTS);
}
/* IN endpoint interrupt. The core sets this bit to indicate that
@@ -3661,7 +3695,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), (uint16_t)regval);
stm32l4_epin_interrupt(priv);
- stm32l4_putreg(OTGFS_GINT_IEP, STM32L4_OTGFS_GINTSTS);
}
/* Host/device mode mismatch error interrupt */
@@ -3670,7 +3703,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_MMIS) != 0)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), (uint16_t)regval);
- stm32l4_putreg(OTGFS_GINT_MMIS, STM32L4_OTGFS_GINTSTS);
}
#endif
@@ -3680,7 +3712,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), (uint16_t)regval);
stm32l4_resumeinterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_WKUP, STM32L4_OTGFS_GINTSTS);
}
/* USB suspend interrupt */
@@ -3689,7 +3720,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), (uint16_t)regval);
stm32l4_suspendinterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_USBSUSP, STM32L4_OTGFS_GINTSTS);
}
/* Start of frame interrupt */
@@ -3698,7 +3728,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_SOF) != 0)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), (uint16_t)regval);
- stm32l4_putreg(OTGFS_GINT_SOF, STM32L4_OTGFS_GINTSTS);
}
#endif
@@ -3710,12 +3739,11 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), (uint16_t)regval);
stm32l4_rxinterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_RXFLVL, STM32L4_OTGFS_GINTSTS);
}
/* USB reset interrupt */
- if ((regval & OTGFS_GINT_USBRST) != 0)
+ if ((regval & (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET)) != 0)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DEVRESET), (uint16_t)regval);
@@ -3723,7 +3751,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
stm32l4_usbreset(priv);
usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), 0);
- stm32l4_putreg(OTGFS_GINT_USBRST, STM32L4_OTGFS_GINTSTS);
return OK;
}
@@ -3733,7 +3760,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), (uint16_t)regval);
stm32l4_enuminterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_ENUMDNE, STM32L4_OTGFS_GINTSTS);
}
/* Incomplete isochronous IN transfer interrupt. When the core finds
@@ -3747,7 +3773,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), (uint16_t)regval);
stm32l4_isocininterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_IISOIXFR, STM32L4_OTGFS_GINTSTS);
}
/* Incomplete isochronous OUT transfer. For isochronous OUT
@@ -3764,7 +3789,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), (uint16_t)regval);
stm32l4_isocoutinterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_IISOOXFR, STM32L4_OTGFS_GINTSTS);
}
#endif
@@ -3775,7 +3799,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), (uint16_t)regval);
stm32l4_sessioninterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_SRQ, STM32L4_OTGFS_GINTSTS);
}
/* OTG interrupt */
@@ -3784,7 +3807,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), (uint16_t)regval);
stm32l4_otginterrupt(priv);
- stm32l4_putreg(OTGFS_GINT_OTG, STM32L4_OTGFS_GINTSTS);
}
#endif
}
@@ -5458,7 +5480,9 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv)
/* Clear any pending interrupts */
- stm32l4_putreg(0xbfffffff, STM32L4_OTGFS_GINTSTS);
+ regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS);
+ regval &= OTGFS_GINT_RESERVED;
+ stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32L4_OTGFS_GINTSTS);
/* Enable the interrupts in the INTMSK */
diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c
index 3d64d812729..bc61ed74460 100644
--- a/arch/arm/src/stm32l4/stm32l4_spi.c
+++ b/arch/arm/src/stm32l4/stm32l4_spi.c
@@ -163,7 +163,7 @@ struct stm32l4_spidev_s
sem_t exclsem; /* Held while chip is selected for mutual exclusion */
uint32_t frequency; /* Requested clock frequency */
uint32_t actual; /* Actual clock frequency */
- int8_t nbits; /* Width of word in bits (8 or 16) */
+ uint8_t nbits; /* Width of word in bits (4 through 16) */
uint8_t mode; /* Mode 0,1,2,3 */
};
@@ -203,6 +203,10 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev,
+ spi_hwfeatures_t features);
+#endif
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd);
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords);
@@ -230,7 +234,7 @@ static const struct spi_ops_s g_spi1ops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0, /* Not supported */
+ .hwfeatures = spi_hwfeatures,
#endif
.status = stm32l4_spi1status,
#ifdef CONFIG_SPI_CMDDATA
@@ -274,6 +278,9 @@ static const struct spi_ops_s g_spi2ops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32l4_spi2status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32l4_spi2cmddata,
@@ -315,6 +322,9 @@ static const struct spi_ops_s g_spi3ops =
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
.status = stm32l4_spi3status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32l4_spi3cmddata,
@@ -348,12 +358,6 @@ static struct stm32l4_spidev_s g_spi3dev =
};
#endif
-/*endif?*/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
/************************************************************************************
* Private Functions
************************************************************************************/
@@ -557,22 +561,7 @@ static inline void spi_writebyte(FAR struct stm32l4_spidev_s *priv, uint8_t byte
static inline bool spi_16bitmode(FAR struct stm32l4_spidev_s *priv)
{
- uint8_t bits = priv->nbits;
-
- /* Get the real number of bits */
-
- if (bits < 0)
- {
- bits = -bits;
- }
-
- return (bits > 8);
-
- /* Should we read the hardware regs? seems to be equivalent ~~ sebastien lorquet
- * (20160413)
- */
-
-// return ((spi_getreg(priv, STM32L4_SPI_CR2_OFFSET) & SPI_CR2_DS_MASK) == SPI_CR2_DS_16BIT);
+ return (priv->nbits > 8);
}
/************************************************************************************
@@ -845,7 +834,8 @@ static inline void spi_dmatxstart(FAR struct stm32l4_spidev_s *priv)
*
************************************************************************************/
-static void spi_modifycr(uint32_t addr, FAR struct stm32l4_spidev_s *priv, uint16_t setbits, uint16_t clrbits)
+static void spi_modifycr(uint32_t addr, FAR struct stm32l4_spidev_s *priv,
+ uint16_t setbits, uint16_t clrbits)
{
uint16_t cr;
@@ -1092,8 +1082,8 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{
FAR struct stm32l4_spidev_s *priv = (FAR struct stm32l4_spidev_s *)dev;
- uint16_t setbits1, setbits2;
- uint16_t clrbits1, clrbits2;
+ uint16_t setbits;
+ uint16_t clrbits;
int savbits = nbits;
spiinfo("nbits=%d\n", nbits);
@@ -1102,30 +1092,17 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
- /* Yes... Set CR1/2 appropriately */
- /* Negative sign means LSBFIRST, set this in CR1*/
-
- if (nbits < 0)
- {
- setbits1 = SPI_CR1_LSBFIRST;
- clrbits1 = 0;
- nbits = -nbits;
- }
- else
- {
- setbits1 = 0;
- clrbits1 = SPI_CR1_LSBFIRST;
- }
-
+ /* Yes... Set CR2 appropriately */
/* Set the number of bits (valid range 4-16) */
if (nbits < 4 || nbits > 16)
{
+ spierr("ERROR: nbits out of range: %d\n", nbits);
return;
}
- clrbits2 = SPI_CR2_DS_MASK;
- setbits2 = SPI_CR2_DS_VAL(nbits);
+ clrbits = SPI_CR2_DS_MASK;
+ setbits = SPI_CR2_DS_VAL(nbits);
/* If nbits is <=8, then we are in byte mode and FRXTH shall be set
* (else, transaction will not complete).
@@ -1133,16 +1110,15 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits < 9)
{
- setbits2 |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
+ setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
}
else
{
- clrbits2 |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
+ clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
}
spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
- spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits1, clrbits1);
- spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits2, clrbits2);
+ spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits);
spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
/* Save the selection so the subsequence re-configurations will be faster */
@@ -1151,6 +1127,58 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
}
}
+/****************************************************************************
+ * Name: spi_hwfeatures
+ *
+ * Description:
+ * Set hardware-specific feature flags.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * features - H/W feature flags
+ *
+ * Returned Value:
+ * Zero (OK) if the selected H/W features are enabled; A negated errno
+ * value if any H/W feature is not supportable.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
+{
+#ifdef CONFIG_SPI_BITORDER
+ FAR struct stm32l4_spidev_s *priv = (FAR struct stm32l4_spidev_s *)dev;
+ uint16_t setbits;
+ uint16_t clrbits;
+
+ spiinfo("features=%08x\n", features);
+
+ /* Transfer data LSB first? */
+
+ if ((features & HWFEAT_LSBFIRST) != 0)
+ {
+ setbits = SPI_CR1_LSBFIRST;
+ clrbits = 0;
+ }
+ else
+ {
+ setbits = 0;
+ clrbits = SPI_CR1_LSBFIRST;
+ }
+
+ spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits);
+ spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ /* Other H/W features are not supported */
+
+ return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
+#else
+ return -ENOSYS;
+#endif
+}
+#endif
+
/************************************************************************************
* Name: spi_send
*
@@ -1501,7 +1529,7 @@ static void spi_bus_initialize(FAR struct stm32l4_spidev_s *priv)
priv->txdma = stm32l4_dmachannel(priv->txch);
DEBUGASSERT(priv->rxdma && priv->txdma);
- spi_putreg(priv, STM32L4_SPI_CR2_OFFSET, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+ spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0);
#endif
/* Enable spi */
@@ -1606,7 +1634,7 @@ FAR struct spi_dev_s *stm32l4_spibus_initialize(int bus)
else
#endif
{
- spierr("ERROR: Unsupbused SPI bus: %d\n", bus);
+ spierr("ERROR: Unsupported SPI bus: %d\n", bus);
return NULL;
}
diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs
index 0ba34f6751a..f3eb92fadce 100644
--- a/arch/arm/src/tiva/Make.defs
+++ b/arch/arm/src/tiva/Make.defs
@@ -101,6 +101,10 @@ ifeq ($(CONFIG_TIVA_I2C),y)
CHIP_CSRCS += tiva_i2c.c
endif
+ifeq ($(CONFIG_TIVA_PWM),y)
+CHIP_CSRCS += tiva_pwm.c
+endif
+
ifeq ($(CONFIG_TIVA_TIMER),y)
CHIP_CSRCS += tiva_timerlib.c
ifeq ($(CONFIG_TIVA_TIMER32_PERIODIC),y)
diff --git a/arch/arm/src/tiva/chip/tiva_pwm.h b/arch/arm/src/tiva/chip/tiva_pwm.h
new file mode 100644
index 00000000000..f0af47a6696
--- /dev/null
+++ b/arch/arm/src/tiva/chip/tiva_pwm.h
@@ -0,0 +1,112 @@
+/************************************************************************************
+ * arch/arm/src/tiva/chip/tiva_pwm.h
+ *
+ * Copyright (C) 2016 Young Mu. All rights reserved.
+ * Author: Young Mu
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TIVA_CHIP_TIVA_PWM_H
+#define __ARCH_ARM_SRC_TIVA_CHIP_TIVA_PWM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define TIVA_PWM_CTL_OFFSET (0x0) /* PWM Master Control */
+#define TIVA_PWM_SYNC_OFFSET (0x4) /* PWM Time Base Sync */
+#define TIVA_PWM_ENABLE_OFFSET (0x8) /* PWM Output Enable */
+#define TIVA_PWM_INVERT_OFFSET (0xc) /* PWM Output Inversion */
+#define TIVA_PWM_FAULT_OFFSET (0x10) /* PWM Output Fault */
+#define TIVA_PWM_INTEN_OFFSET (0x14) /* PWM Interrupt Enable */
+#define TIVA_PWM_RIS_OFFSET (0x18) /* PWM Raw Interrupt Status */
+#define TIVA_PWM_ISC_OFFSET (0x1c) /* PWM Interrupt Status and Clear */
+#define TIVA_PWM_STATUS_OFFSET (0x20) /* PWM Status */
+#define TIVA_PWM_FAULTVAL_OFFSET (0x24) /* PWM Fault Condition Value */
+#define TIVA_PWM_ENUPD_OFFSET (0x28) /* PWM Enable Update */
+
+#define TIVA_PWMn_BASE (0x40) /* PWMn Base */
+#define TIVA_PWMn_INTERVAL (0x40) /* PWMn Interval */
+
+#define TIVA_PWMn_CTL_OFFSET (0x0) /* PWMn Control */
+#define TIVA_PWMn_INTEN_OFFSET (0x4) /* PWMn Interrupt and Trigger Enable */
+#define TIVA_PWMn_RIS_OFFSET (0x8) /* PWMn Raw Interrupt Status */
+#define TIVA_PWMn_ISC_OFFSET (0xc) /* PWMn Interrupt Status and Clear */
+#define TIVA_PWMn_LOAD_OFFSET (0x10) /* PWMn Load */
+#define TIVA_PWMn_COUNT_OFFSET (0x14) /* PWMn Counter */
+#define TIVA_PWMn_CMPA_OFFSET (0x18) /* PWMn Compare A */
+#define TIVA_PWMn_CMPB_OFFSET (0x1c) /* PWMn Compare B */
+#define TIVA_PWMn_GENA_OFFSET (0x20) /* PWMn Generator A Control */
+#define TIVA_PWMn_GENB_OFFSET (0x24) /* PWMn Generator B Control */
+#define TIVA_PWMn_DBCTL_OFFSET (0x28) /* PWMn Dead-Band Control */
+#define TIVA_PWMn_DBRISE_OFFSET (0x2c) /* PWMn Dead-Band Rising-Edge-Delay */
+#define TIVA_PWMn_DBFALL_OFFSET (0x30) /* PWMn Dead-Band Falling-Edge-Delay */
+#define TIVA_PWMn_FLTSRC0_OFFSET (0x34) /* PWMn Fault Source 0 */
+#define TIVA_PWMn_FLTSRC1_OFFSET (0x38) /* PWMn Fault Source 1 */
+#define TIVA_PWMn_MINFLTPER_OFFSET (0x3c) /* PWMn Minimum Fault Period */
+
+#define TIVA_PWMn_FAULT_BASE (0x800) /* PWMn Fault Base */
+#define TIVA_PWMn_FAULT_INTERVAL (0x80) /* PWMn Fault Interval */
+
+#define TIVA_PWMn_FAULT_SEN_OFFSET (0x0) /* PWMn Fault Pin Logic Sense */
+#define TIVA_PWMn_FAULT_STAT0_OFFSET (0x4) /* PWMn Fault Status 0 */
+#define TIVA_PWMn_FAULT_STAT1_OFFSET (0x8) /* PWMn Fault Status 1 */
+
+#define TIVA_PWM_PP (0xfc0) /* PWM Peripheral Properties */
+#define TIVA_PWM_CC (0xfc8) /* PWM Clock Configuration */
+
+#define TIVA_PWMn_GENx_ACTCMPBD (10) /* (Bit) Action for Comparator B Down */
+#define TIVA_PWMn_GENx_ACTCMPBU (8) /* (Bit) Action for Comparator B Up */
+#define TIVA_PWMn_GENx_ACTCMPAD (6) /* (Bit) Action for Comparator A Down */
+#define TIVA_PWMn_GENx_ACTCMPAU (4) /* (Bit) Action for Comparator A Up */
+#define TIVA_PWMn_GENx_ACTLOAD (2) /* (Bit) Action for Counter equals LOAD */
+#define TIVA_PWMn_GENx_ACTZERO (0) /* (Bit) Action for Counter equals ZERO */
+#define GENx_INVERT (0x1) /* (Value) Invert */
+#define GENx_LOW (0x2) /* (Value) Drive Low */
+#define GENx_HIGH (0x3) /* (Value) Drive High */
+
+#define TIVA_PWM_CC_USEPWM (8) /* (Bit) Use PWM Clock Divisor */
+#define TIVA_PWM_CC_PWMDIV (0) /* (Bit) PWM Clock Divider */
+#define CC_USEPWM (0x1) /* (Value) Use PWM divider as clock source */
+#define CC_PWMDIV_2 (0x0) /* (Value) Divided by 2 */
+#define CC_PWMDIV_4 (0x1) /* (Value) Divided by 4 */
+#define CC_PWMDIV_8 (0x2) /* (Value) Divided by 8 */
+#define CC_PWMDIV_16 (0x3) /* (Value) Divided by 16 */
+#define CC_PWMDIV_32 (0x4) /* (Value) Divided by 32 */
+#define CC_PWMDIV_64 (0x5) /* (Value) Divided by 64 */
+
+#define TIVA_PWMn_CTL_ENABLE (0) /* (Bit) PWM Block Enable */
+#define CTL_ENABLE (1) /* (Value) Enable */
+
+#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TIVA_PWM_H */
diff --git a/arch/arm/src/tiva/chip/tm4c129_syscontrol.h b/arch/arm/src/tiva/chip/tm4c129_syscontrol.h
index 928be38e95a..9578313b86b 100644
--- a/arch/arm/src/tiva/chip/tm4c129_syscontrol.h
+++ b/arch/arm/src/tiva/chip/tm4c129_syscontrol.h
@@ -1895,7 +1895,9 @@
/* PWM Power Control */
-#define SYSCON_PCPWM_P0 (1 << 0) /* Bit 0: PWM Module 0 Power Control */
+#define SYSCON_PCPWM(n) (1 << (n)) /* Bit n: PWM module n Power Control */
+# define SYSCON_PCPWM_P0 (1 << 0) /* Bit 0: PWM Module 0 Power Control */
+# define SYSCON_PCPWM_P1 (1 << 1) /* Bit 1: PWM Module 1 Power Control */
/* QE Interface Power Control */
diff --git a/arch/arm/src/tiva/tiva_pwm.c b/arch/arm/src/tiva/tiva_pwm.c
new file mode 100644
index 00000000000..b5032aeb21d
--- /dev/null
+++ b/arch/arm/src/tiva/tiva_pwm.c
@@ -0,0 +1,577 @@
+/************************************************************************************
+ * arch/arm/src/tiva/tiva_pwm.c
+ *
+ * Copyright (C) 2016 Young Mu. All rights reserved.
+ * Author: Young Mu
+ *
+ * The basic structure of this driver derives in spirit (if nothing more) from the
+ * NuttX SAM PWM driver which has:
+ *
+ * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+#include
+#include
+
+#include
+
+#include "up_arch.h"
+#include "tiva_gpio.h"
+#include "tiva_pwm.h"
+#include "tiva_enablepwr.h"
+#include "tiva_enableclks.h"
+
+#include "chip/tiva_pwm.h"
+#include "chip/tiva_pinmap.h"
+#include "chip/tm4c_memorymap.h"
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+uint32_t g_pwm_pinset[] =
+{
+ GPIO_M0_PWM0,
+ GPIO_M0_PWM1,
+ GPIO_M0_PWM2,
+ GPIO_M0_PWM3,
+ GPIO_M0_PWM4,
+ GPIO_M0_PWM5,
+ GPIO_M0_PWM6,
+ GPIO_M0_PWM7,
+};
+
+struct tiva_pwm_chan_s
+{
+ const struct pwm_ops_s *ops;
+ uint8_t controller_id;
+ uintptr_t controller_base;
+ uint8_t generator_id;
+ uintptr_t generator_base;
+ uint8_t channel_id;
+};
+
+/************************************************************************************
+ * Private Function Prototypes
+ ************************************************************************************/
+
+static inline void tiva_pwm_putreg(struct tiva_pwm_chan_s *chan,
+ unsigned int offset, uint32_t regval);
+static inline uint32_t tiva_pwm_getreg(struct tiva_pwm_chan_s *chan,
+ unsigned int offset);
+
+static int tiva_pwm_setup(FAR struct pwm_lowerhalf_s *dev);
+static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
+static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
+ FAR const struct pwm_info_s *info);
+static int tiva_pwm_stop(FAR struct pwm_lowerhalf_s *dev);
+static int tiva_pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
+ int cmd, unsigned long arg);
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static uint32_t g_pwm_freq = 15000000;
+static uint32_t g_pwm_counter = (1 << 16);
+
+static const struct pwm_ops_s g_pwm_ops =
+{
+ .setup = tiva_pwm_setup,
+ .shutdown = tiva_pwm_shutdown,
+ .start = tiva_pwm_start,
+ .stop = tiva_pwm_stop,
+ .ioctl = tiva_pwm_ioctl,
+};
+
+#ifdef CONFIG_TIVA_PWM0_CHAN0
+static struct tiva_pwm_chan_s g_pwm_chan0 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 0,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 0,
+ .channel_id = 0,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN1
+static struct tiva_pwm_chan_s g_pwm_chan1 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 0,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 0,
+ .channel_id = 1,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN2
+static struct tiva_pwm_chan_s g_pwm_chan2 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 1,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 1,
+ .channel_id = 2,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN3
+static struct tiva_pwm_chan_s g_pwm_chan3 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 1,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 1,
+ .channel_id = 3,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN4
+static struct tiva_pwm_chan_s g_pwm_chan4 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 2,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 2,
+ .channel_id = 4,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN5
+static struct tiva_pwm_chan_s g_pwm_chan5 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 2,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 2,
+ .channel_id = 5,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN6
+static struct tiva_pwm_chan_s g_pwm_chan6 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 3,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 3,
+ .channel_id = 6,
+};
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN7
+static struct tiva_pwm_chan_s g_pwm_chan7 =
+{
+ .ops = &g_pwm_ops,
+ .controller_id = 0,
+ .controller_base = TIVA_PWM0_BASE,
+ .generator_id = 3,
+ .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 3,
+ .channel_id = 7,
+};
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: tiva_pwm_getreg
+ *
+ * Description:
+ * Get a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint32_t tiva_pwm_getreg(struct tiva_pwm_chan_s *chan,
+ unsigned int offset)
+{
+ uintptr_t regaddr = chan->generator_base + offset;
+ return getreg32(regaddr);
+}
+
+/************************************************************************************
+ * Name: tiva_pwm_putreg
+ *
+ * Description:
+ * Put a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void tiva_pwm_putreg(struct tiva_pwm_chan_s *chan,
+ unsigned int offset, uint32_t regval)
+{
+ uintptr_t regaddr = chan->generator_base + offset;
+ putreg32(regval, regaddr);
+}
+
+/****************************************************************************
+ * Name: pwm_setup
+ *
+ * Description:
+ * This method is called when the driver is opened. The lower half driver
+ * will be configured and initialized the device so that it is ready for
+ * use. It will not, however, output pulses until the start method is
+ * called.
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int tiva_pwm_setup(FAR struct pwm_lowerhalf_s *dev)
+{
+ FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev;
+ pwminfo("setup PWM for channel %d\n", chan->channel_id);
+
+ /* Enable GPIO port, GPIO pin type and GPIO alternate function (refer to
+ * TM4C1294NC 23.4.2-4)
+ */
+
+ int ret = tiva_configgpio(g_pwm_pinset[chan->channel_id]);
+ if (ret < 0)
+ {
+ pwmerr("ERROR: tiva_configgpio failed (%x)\n",
+ g_pwm_pinset[chan->channel_id]);
+ return ret;
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_shutdown
+ *
+ * Description:
+ * This method is called when the driver is closed. The lower half driver
+ * stop pulsed output, free any resources, disable the timer hardware, and
+ * put the system into the lowest possible power usage state
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
+{
+ FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev;
+ pwminfo("shutdown PWM for channel %d\n", chan->channel_id);
+
+ /* Remove unused-variable warning */
+
+ (void)chan;
+
+ /* Ensure the PWM channel has been stopped */
+
+ tiva_pwm_stop(dev);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_start
+ *
+ * Description:
+ * (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
+ FAR const struct pwm_info_s *info)
+{
+ FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev;
+ pwminfo("start PWM for channel %d\n", chan->channel_id);
+
+ uint16_t duty = info->duty;
+ uint32_t frequency = info->frequency;
+
+ /* Configure PWM countdown mode (refer to TM4C1294NC 23.4.6) */
+
+ tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, 0);
+ if (chan->channel_id % 2 == 0)
+ {
+ tiva_pwm_putreg(chan, TIVA_PWMn_GENA_OFFSET,
+ GENx_LOW << TIVA_PWMn_GENx_ACTCMPAD | GENx_HIGH << TIVA_PWMn_GENx_ACTLOAD);
+ }
+ else
+ {
+ tiva_pwm_putreg(chan, TIVA_PWMn_GENB_OFFSET,
+ GENx_LOW << TIVA_PWMn_GENx_ACTCMPBD | GENx_HIGH << TIVA_PWMn_GENx_ACTLOAD);
+ }
+
+ /* Set the PWM period (refer to TM4C1294NC 23.4.7) */
+
+ uint32_t pwm_min_freq = (uint32_t)(g_pwm_freq / g_pwm_counter) + 1;
+ uint32_t pwm_max_freq = g_pwm_freq;
+ uint32_t load = (uint32_t)(g_pwm_freq / frequency);
+
+ pwminfo("channel %d: load = %u (%08x)\n", chan->channel_id, load, load);
+
+ if (load >= g_pwm_counter || load < 1)
+ {
+ pwmerr("ERROR: frequency should be in [%d, %d] Hz\n",
+ pwm_min_freq, pwm_max_freq);
+ return -ERANGE;
+ }
+
+ tiva_pwm_putreg(chan, TIVA_PWMn_LOAD_OFFSET, load - 1);
+
+ /* Configure PWM duty (refer to TM4C1294NC 23.4.8-9)
+ *
+ * Workaround:
+ * When comp equals to load, the signal is never pulled down,
+ * so let comp equals to (comp-1)
+ */
+
+ uint32_t comp = (uint32_t)((1 - (float)duty / g_pwm_counter) * load);
+ comp = (duty == 0) ? (comp - 1) : (comp);
+ pwminfo("channel %d: comp = %u (%08x)\n", chan->channel_id, comp, comp);
+
+ if (chan->channel_id % 2 == 0)
+ {
+ tiva_pwm_putreg(chan, TIVA_PWMn_CMPA_OFFSET, comp - 1);
+ }
+ else
+ {
+ tiva_pwm_putreg(chan, TIVA_PWMn_CMPB_OFFSET, comp - 1);
+ }
+
+ /* Enable the PWM generator (refer to TM4C1294NC 23.4.10) */
+
+ tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, CTL_ENABLE << TIVA_PWMn_CTL_ENABLE);
+
+ /* Enable PWM channel (refer to TM4C1294NC 23.4.11) */
+
+ uint32_t enable = getreg32(chan->controller_base + TIVA_PWM_ENABLE_OFFSET);
+ enable |= (1 << chan->channel_id);
+ putreg32(enable, chan->controller_base + TIVA_PWM_ENABLE_OFFSET);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_stop
+ *
+ * Description:
+ * Stop the pulsed output and reset the timer resources
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ * This function is called to stop the pulsed output at anytime. This
+ * method is also called from the timer interrupt handler when a repetition
+ * count expires... automatically stopping the timer.
+ *
+ ****************************************************************************/
+
+static int tiva_pwm_stop(FAR struct pwm_lowerhalf_s *dev)
+{
+ FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev;
+ pwminfo("stop PWM for channel %d\n", chan->channel_id);
+
+ /* Disable PWM channel */
+
+ uint32_t value = getreg32(chan->controller_base + TIVA_PWM_ENABLE_OFFSET);
+ value &= ~(1 << chan->channel_id);
+ putreg32(value, chan->controller_base + TIVA_PWM_ENABLE_OFFSET);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_ioctl
+ *
+ * Description:
+ * Lower-half logic may support platform-specific ioctl commands
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * cmd - The ioctl command
+ * arg - The argument accompanying the ioctl command
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int tiva_pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd,
+ unsigned long arg)
+{
+ FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev;
+ pwminfo("ioctl PWM for channel %d\n", chan->channel_id);
+
+ /* Remove unused-variable warning */
+
+ (void)chan;
+
+ /* There are no platform-specific ioctl commands */
+
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: tiva_pwm_initialize
+ *
+ * Description:
+ * Initialize one PWM channel for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * channel - A number identifying the PWM channel use.
+ *
+ * Returned Value:
+ * On success, a pointer to the SAMA5 lower half PWM driver is returned.
+ * NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel)
+{
+ assert(channel >= 0 && channel <= 7);
+ FAR struct tiva_pwm_chan_s *chan;
+
+ switch (channel)
+ {
+#ifdef CONFIG_TIVA_PWM0_CHAN0
+ case 0:
+ chan = &g_pwm_chan0;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN1
+ case 1:
+ chan = &g_pwm_chan1;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN2
+ case 2:
+ chan = &g_pwm_chan2;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN3
+ case 3:
+ chan = &g_pwm_chan3;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN4
+ case 4:
+ chan = &g_pwm_chan4;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN5
+ case 5:
+ chan = &g_pwm_chan5;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN6
+ case 6:
+ chan = &g_pwm_chan6;
+ break;
+#endif
+
+#ifdef CONFIG_TIVA_PWM0_CHAN7
+ case 7:
+ chan = &g_pwm_chan7;
+ break;
+#endif
+
+ default:
+ pwmerr("ERROR: invalid channel %d\n", channel);
+ return NULL;
+ }
+
+ pwminfo("channel %d: channel_id=%d, ", channel, chan->channel_id);
+ pwminfo("controller_id=%d, controller_base=%08x, ",
+ chan->controller_id, chan->controller_base);
+ pwminfo("generator_id=%d, generator_base=%08x\n",
+ chan->generator_id, chan->generator_base);
+
+ /* Enable PWM controller (refer to TM4C1294NC 23.4.1) */
+
+ assert(chan->controller_id == 0);
+ tiva_pwm_enablepwr(chan->controller_id);
+ tiva_pwm_enableclk(chan->controller_id);
+
+ /* Configure PWM Clock Configuration (refer to TM4C1294NC 23.4.5)
+ *
+ * On TM4C1294NC, configure the PWM clock source as 15MHz (the system
+ * clock 120MHz divided by 8)
+ *
+ * TODO: need an algorithm to choose the best divider and load value combo.
+ */
+
+ putreg32(CC_USEPWM << TIVA_PWM_CC_USEPWM | CC_PWMDIV_8 << TIVA_PWM_CC_PWMDIV,
+ chan->controller_base + TIVA_PWM_CC);
+
+ return (FAR struct pwm_lowerhalf_s *)chan;
+}
diff --git a/arch/arm/src/tiva/tiva_pwm.h b/arch/arm/src/tiva/tiva_pwm.h
new file mode 100644
index 00000000000..c60b37617b2
--- /dev/null
+++ b/arch/arm/src/tiva/tiva_pwm.h
@@ -0,0 +1,52 @@
+/************************************************************************************
+ * arch/arm/src/tiva/tiva_pwm.h
+ *
+ * Copyright (C) 2016 Young Mu. All rights reserved.
+ * Author: Young Mu
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TIVA_TIVA_PWM_H
+#define __ARCH_ARM_SRC_TIVA_TIVA_PWM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel);
+void tm4c_pwm_register(int channel);
+
+#endif /* __ARCH_ARM_SRC_TIVA_TIVA_PWM_H */
diff --git a/arch/arm/src/tiva/tiva_timerlow32.c b/arch/arm/src/tiva/tiva_timerlow32.c
index 2491e01f634..2fcf9694298 100644
--- a/arch/arm/src/tiva/tiva_timerlow32.c
+++ b/arch/arm/src/tiva/tiva_timerlow32.c
@@ -511,7 +511,7 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd,
{
int ret = -ENOTTY;
- DEBUGASSERT(priv);
+ DEBUGASSERT(lower);
tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
return ret;
diff --git a/arch/hc/src/m9s12/Make.defs b/arch/hc/src/m9s12/Make.defs
index 97fc4861a92..5b7ffaffea4 100644
--- a/arch/hc/src/m9s12/Make.defs
+++ b/arch/hc/src/m9s12/Make.defs
@@ -1,5 +1,5 @@
############################################################################
-# arch/arm/src/m9s12/Make.defs
+# arch/hc/src/m9s12/Make.defs
#
# Copyright (C) 2009, 2011, 2014 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_atd.h b/arch/hc/src/m9s12/m9s12_atd.h
index 6c6946bceb6..6df615b31a6 100644
--- a/arch/hc/src/m9s12/m9s12_atd.h
+++ b/arch/hc/src/m9s12/m9s12_atd.h
@@ -1,6 +1,6 @@
/************************************************************************************
* arch/hc/src/m9s12/m9s12_atd.h
- * Defintions for ATD10b8c v3
+ * Definitions for ATD10b8c v3
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_dumpgpio.c b/arch/hc/src/m9s12/m9s12_dumpgpio.c
index ad6ce5860fb..4a7d3860fa2 100644
--- a/arch/hc/src/m9s12/m9s12_dumpgpio.c
+++ b/arch/hc/src/m9s12/m9s12_dumpgpio.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/m9s12/m9s12_dumpgpio.c
+ * arch/hc/src/m9s12/m9s12_dumpgpio.c
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c
index 958a10affec..fe2656e97a9 100644
--- a/arch/hc/src/m9s12/m9s12_ethernet.c
+++ b/arch/hc/src/m9s12/m9s12_ethernet.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * drivers/net/m9s12_ethernet.c
+ * arch/hc/src/m9s12/m9s12_ethernet.c
*
* Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_gpio.c b/arch/hc/src/m9s12/m9s12_gpio.c
index 0004bdf5de7..b861ee2b402 100644
--- a/arch/hc/src/m9s12/m9s12_gpio.c
+++ b/arch/hc/src/m9s12/m9s12_gpio.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/m9s12/m9s12_gpio.c
+ * arch/hc/src/m9s12/m9s12_gpio.c
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_gpioirq.c b/arch/hc/src/m9s12/m9s12_gpioirq.c
index d16c208f4cb..b0f72d77622 100644
--- a/arch/hc/src/m9s12/m9s12_gpioirq.c
+++ b/arch/hc/src/m9s12/m9s12_gpioirq.c
@@ -1,6 +1,5 @@
/****************************************************************************
- * arch/arm/src/m9s12/m9s12_gpioirq.c
- * arch/arm/src/chip/m9s12_gpioirq.c
+ * arch/hc/src/m9s12/m9s12_gpioirq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_irq.c b/arch/hc/src/m9s12/m9s12_irq.c
index 4ce19d70e90..9f95388915c 100644
--- a/arch/hc/src/m9s12/m9s12_irq.c
+++ b/arch/hc/src/m9s12/m9s12_irq.c
@@ -1,6 +1,5 @@
/****************************************************************************
- * arch/arm/src/m9s12/m9s12_irq.c
- * arch/arm/src/chip/m9s12_irq.c
+ * arch/hc/src/m9s12/m9s12_irq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_lowputc.S b/arch/hc/src/m9s12/m9s12_lowputc.S
index 1b363435e9a..ca7f0647846 100644
--- a/arch/hc/src/m9s12/m9s12_lowputc.S
+++ b/arch/hc/src/m9s12/m9s12_lowputc.S
@@ -1,5 +1,5 @@
/**************************************************************************
- * arch/arm/src/m9s12/m9s12_lowputc.S
+ * arch/hc/src/m9s12/m9s12_lowputc.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_saveusercontext.S b/arch/hc/src/m9s12/m9s12_saveusercontext.S
index 8538cc1f063..417af5a66e1 100644
--- a/arch/hc/src/m9s12/m9s12_saveusercontext.S
+++ b/arch/hc/src/m9s12/m9s12_saveusercontext.S
@@ -1,5 +1,5 @@
/**************************************************************************
- * arch/arm/src/m9s12/m9s12_saveusercontext.S
+ * arch/hc/src/m9s12/m9s12_saveusercontext.S
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_start.S b/arch/hc/src/m9s12/m9s12_start.S
index 3747967f5b7..f6b54ad58f0 100644
--- a/arch/hc/src/m9s12/m9s12_start.S
+++ b/arch/hc/src/m9s12/m9s12_start.S
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/hc/src/m9s12/m9s12_start.S
- * arch/hc/src/chip/m9s12_start.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/hc/src/m9s12/m9s12_vectors.S b/arch/hc/src/m9s12/m9s12_vectors.S
index fbe4d69f0a7..10bbe540648 100644
--- a/arch/hc/src/m9s12/m9s12_vectors.S
+++ b/arch/hc/src/m9s12/m9s12_vectors.S
@@ -1,6 +1,5 @@
/************************************************************************************
* arch/hc/src/m9s12/m9s12_vectors.S
- * arch/hc/src/chip/m9s12_vectors.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c
index 8578977b3b4..8a1bc084828 100644
--- a/arch/mips/src/pic32mx/pic32mx-ethernet.c
+++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/pic32mx/pic32mx_ethernet.c
+ * arch/mips/src/pic32mx/pic32mx_ethernet.c
*
* Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c
index ded512f6e1d..f9e82155dc2 100644
--- a/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx-irq.c
- * arch/mips/src/chip/pic32mx-irq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c
index 87a91962d4e..b2df3654497 100644
--- a/arch/mips/src/pic32mz/pic32mz-ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/pic32mz/pic32mz_ethernet.c
+ * arch/mips/src/pic32mz/pic32mz_ethernet.c
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/Kconfig b/arch/renesas/Kconfig
similarity index 75%
rename from arch/sh/Kconfig
rename to arch/renesas/Kconfig
index 48c76f3ca03..c8818030d79 100644
--- a/arch/sh/Kconfig
+++ b/arch/renesas/Kconfig
@@ -3,10 +3,10 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
-if ARCH_SH
+if ARCH_RENESAS
choice
- prompt "SH chip selection"
+ prompt "Renesas chip selection"
default ARCH_CHIP_SH7032
config ARCH_CHIP_SH7032
@@ -37,8 +37,8 @@ config ARCH_CHIP
default "sh1" if ARCH_SH1
default "m16c" if ARCH_M16C
-source arch/sh/src/common/Kconfig
-source arch/sh/src/m16c/Kconfig
-source arch/sh/src/sh1/Kconfig
+source arch/renesas/src/common/Kconfig
+source arch/renesas/src/m16c/Kconfig
+source arch/renesas/src/sh1/Kconfig
-endif # ARCH_SH
+endif # ARCH_RENESAS
diff --git a/arch/sh/include/README.txt b/arch/renesas/include/README.txt
similarity index 100%
rename from arch/sh/include/README.txt
rename to arch/renesas/include/README.txt
diff --git a/arch/sh/include/arch.h b/arch/renesas/include/arch.h
similarity index 95%
rename from arch/sh/include/arch.h
rename to arch/renesas/include/arch.h
index 4b4c7e934d9..a4824ce9841 100644
--- a/arch/sh/include/arch.h
+++ b/arch/renesas/include/arch.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/arch.h
+ * arch/renesas/include/arch.h
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/arch.h
*/
-#ifndef __ARCH_SH_INCLUDE_ARCH_H
-#define __ARCH_SH_INCLUDE_ARCH_H
+#ifndef __ARCH_RENESAS_INCLUDE_ARCH_H
+#define __ARCH_RENESAS_INCLUDE_ARCH_H
/****************************************************************************
* Included Files
@@ -77,4 +77,4 @@ extern "C"
}
#endif
-#endif /* __ARCH_SH_INCLUDE_ARCH_H */
+#endif /* __ARCH_RENESAS_INCLUDE_ARCH_H */
diff --git a/arch/sh/include/irq.h b/arch/renesas/include/irq.h
similarity index 95%
rename from arch/sh/include/irq.h
rename to arch/renesas/include/irq.h
index 78617accce6..4f365ceaa84 100644
--- a/arch/sh/include/irq.h
+++ b/arch/renesas/include/irq.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/irq.h
+ * arch/renesas/include/irq.h
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_SH_INCLUDE_IRQ_H
-#define __ARCH_SH_INCLUDE_IRQ_H
+#ifndef __ARCH_RENESAS_INCLUDE_IRQ_H
+#define __ARCH_RENESAS_INCLUDE_IRQ_H
/****************************************************************************
* Included Files
@@ -82,5 +82,5 @@ extern "C"
#endif
#endif
-#endif /* __ARCH_SH_INCLUDE_IRQ_H */
+#endif /* __ARCH_RENESAS_INCLUDE_IRQ_H */
diff --git a/arch/sh/include/limits.h b/arch/renesas/include/limits.h
similarity index 93%
rename from arch/sh/include/limits.h
rename to arch/renesas/include/limits.h
index feb02e5d6f3..56c729c0c74 100644
--- a/arch/sh/include/limits.h
+++ b/arch/renesas/include/limits.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/limits.h
+ * arch/renesas/include/limits.h
*
* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __ARCH_SH_INCLUDE_LIMITS_H
-#define __ARCH_SH_INCLUDE_LIMITS_H
+#ifndef __ARCH_RENESAS_INCLUDE_LIMITS_H
+#define __ARCH_RENESAS_INCLUDE_LIMITS_H
/****************************************************************************
* Included Files
@@ -46,4 +46,4 @@
* Pre-processor Definitions
****************************************************************************/
-#endif /* __ARCH_SH_INCLUDE_LIMITS_H */
+#endif /* __ARCH_RENESAS_INCLUDE_LIMITS_H */
diff --git a/arch/sh/include/m16c/irq.h b/arch/renesas/include/m16c/irq.h
similarity index 98%
rename from arch/sh/include/m16c/irq.h
rename to arch/renesas/include/m16c/irq.h
index 2528e911eb7..0d000f975f8 100644
--- a/arch/sh/include/m16c/irq.h
+++ b/arch/renesas/include/m16c/irq.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/include/m16c/irq.h
+ * arch/renesas/include/m16c/irq.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_SH_INCLUDE_M16C_IRQ_H
-#define __ARCH_SH_INCLUDE_M16C_IRQ_H
+#ifndef __ARCH_RENESAS_INCLUDE_M16C_IRQ_H
+#define __ARCH_RENESAS_INCLUDE_M16C_IRQ_H
/************************************************************************************
* Included Files
@@ -328,5 +328,5 @@ static inline void up_irq_restore(irqstate_t flags)
#endif
#endif
-#endif /* __ARCH_SH_INCLUDE_M16C_IRQ_H */
+#endif /* __ARCH_RENESAS_INCLUDE_M16C_IRQ_H */
diff --git a/arch/sh/include/m16c/limits.h b/arch/renesas/include/m16c/limits.h
similarity index 94%
rename from arch/sh/include/m16c/limits.h
rename to arch/renesas/include/m16c/limits.h
index 27723d99686..26cb2726f36 100644
--- a/arch/sh/include/m16c/limits.h
+++ b/arch/renesas/include/m16c/limits.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/m16c/limits.h
+ * arch/renesas/include/m16c/limits.h
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __ARCH_SH_INCLUDE_M16C_LIMITS_H
-#define __ARCH_SH_INCLUDE_M16C_LIMITS_H
+#ifndef __ARCH_RENESAS_INCLUDE_M16C_LIMITS_H
+#define __ARCH_RENESAS_INCLUDE_M16C_LIMITS_H
/****************************************************************************
* Included Files
@@ -85,4 +85,4 @@
#define PTR_MAX 32767
#define UPTR_MAX 65535U
-#endif /* __ARCH_SH_INCLUDE_M16C_LIMITS_H */
+#endif /* __ARCH_RENESAS_INCLUDE_M16C_LIMITS_H */
diff --git a/arch/sh/include/m16c/types.h b/arch/renesas/include/m16c/types.h
similarity index 95%
rename from arch/sh/include/m16c/types.h
rename to arch/renesas/include/m16c/types.h
index 3211209e93f..8eb35288337 100644
--- a/arch/sh/include/m16c/types.h
+++ b/arch/renesas/include/m16c/types.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/m16c/types.h
+ * arch/renesas/include/m16c/types.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* through sys/types.h
*/
-#ifndef __ARCH_SH_INCLUDE_M16C_TYPES_H
-#define __ARCH_SH_INCLUDE_M16C_TYPES_H
+#ifndef __ARCH_RENESAS_INCLUDE_M16C_TYPES_H
+#define __ARCH_RENESAS_INCLUDE_M16C_TYPES_H
/****************************************************************************
* Included Files
@@ -95,4 +95,4 @@ typedef _uint16_t irqstate_t;
* Public Function Prototypes
****************************************************************************/
-#endif /* __ARCH_SH_INCLUDE_M16C_TYPES_H */
+#endif /* __ARCH_RENESAS_INCLUDE_M16C_TYPES_H */
diff --git a/arch/sh/include/serial.h b/arch/renesas/include/serial.h
similarity index 94%
rename from arch/sh/include/serial.h
rename to arch/renesas/include/serial.h
index 2ec4ac9054a..224e769c1e0 100644
--- a/arch/sh/include/serial.h
+++ b/arch/renesas/include/serial.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/serial.h
+ * arch/renesas/include/serial.h
*
* Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __ARCH_SH_INCLUDE_SERIAL_H
-#define __ARCH_SH_INCLUDE_SERIAL_H
+#ifndef __ARCH_RENESAS_INCLUDE_SERIAL_H
+#define __ARCH_RENESAS_INCLUDE_SERIAL_H
/****************************************************************************
* Included Files
@@ -54,4 +54,4 @@
* Public Functions
****************************************************************************/
-#endif /* __ARCH_SH_INCLUDE_SERIAL_H */
+#endif /* __ARCH_RENESAS_INCLUDE_SERIAL_H */
diff --git a/arch/sh/include/sh1/irq.h b/arch/renesas/include/sh1/irq.h
similarity index 99%
rename from arch/sh/include/sh1/irq.h
rename to arch/renesas/include/sh1/irq.h
index b4af921bdbb..9c82e0b39e0 100644
--- a/arch/sh/include/sh1/irq.h
+++ b/arch/renesas/include/sh1/irq.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/include/sh1/irq.h
+ * arch/renesas/include/sh1/irq.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_SH_INCLUDE_SH1_IRQ_H
-#define __ARCH_SH_INCLUDE_SH1_IRQ_H
+#ifndef __ARCH_RENESAS_INCLUDE_SH1_IRQ_H
+#define __ARCH_RENESAS_INCLUDE_SH1_IRQ_H
/************************************************************************************
* Included Files
@@ -563,5 +563,5 @@ static inline void up_irq_restore(irqstate_t flags)
#endif
#endif
-#endif /* __ARCH_SH_INCLUDE_SH1_IRQ_H */
+#endif /* __ARCH_RENESAS_INCLUDE_SH1_IRQ_H */
diff --git a/arch/sh/include/sh1/limits.h b/arch/renesas/include/sh1/limits.h
similarity index 94%
rename from arch/sh/include/sh1/limits.h
rename to arch/renesas/include/sh1/limits.h
index 071189c4ec1..661ed6bd1ee 100644
--- a/arch/sh/include/sh1/limits.h
+++ b/arch/renesas/include/sh1/limits.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/sh1/limits.h
+ * arch/renesas/include/sh1/limits.h
*
* Copyright (C) 2008, 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __ARCH_SH_INCLUDE_SH1_LIMITS_H
-#define __ARCH_SH_INCLUDE_SH1_LIMITS_H
+#ifndef __ARCH_RENESAS_INCLUDE_SH1_LIMITS_H
+#define __ARCH_RENESAS_INCLUDE_SH1_LIMITS_H
/****************************************************************************
* Included Files
@@ -85,4 +85,4 @@
#define PTR_MAX 2147483647
#define UPTR_MAX 4294967295U
-#endif /* __ARCH_SH_INCLUDE_SH1_LIMITS_H */
+#endif /* __ARCH_RENESAS_INCLUDE_SH1_LIMITS_H */
diff --git a/arch/sh/include/sh1/types.h b/arch/renesas/include/sh1/types.h
similarity index 95%
rename from arch/sh/include/sh1/types.h
rename to arch/renesas/include/sh1/types.h
index aeafe71c3d6..86d7b5b9bb3 100644
--- a/arch/sh/include/sh1/types.h
+++ b/arch/renesas/include/sh1/types.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/sh1/types.h
+ * arch/renesas/include/sh1/types.h
*
* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* through sys/types.h
*/
-#ifndef __ARCH_SH_INCLUDE_SH1_TYPES_H
-#define __ARCH_SH_INCLUDE_SH1_TYPES_H
+#ifndef __ARCH_RENESAS_INCLUDE_SH1_TYPES_H
+#define __ARCH_RENESAS_INCLUDE_SH1_TYPES_H
/****************************************************************************
* Included Files
@@ -93,4 +93,4 @@ typedef unsigned long irqstate_t;
* Public Function Prototypes
****************************************************************************/
-#endif /* __ARCH_SH_INCLUDE_SH1_TYPES_H */
+#endif /* __ARCH_RENESAS_INCLUDE_SH1_TYPES_H */
diff --git a/arch/renesas/include/sh1Plimits.h b/arch/renesas/include/sh1Plimits.h
new file mode 100644
index 00000000000..661ed6bd1ee
--- /dev/null
+++ b/arch/renesas/include/sh1Plimits.h
@@ -0,0 +1,88 @@
+/****************************************************************************
+ * arch/renesas/include/sh1/limits.h
+ *
+ * Copyright (C) 2008, 2009, 2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RENESAS_INCLUDE_SH1_LIMITS_H
+#define __ARCH_RENESAS_INCLUDE_SH1_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN 0
+#define CHAR_MAX UCHAR_MAX
+#else
+#define CHAR_MIN SCHAR_MIN
+#define CHAR_MAX SCHAR_MAX
+#endif
+
+#define SHRT_MIN (-SHRT_MAX - 1)
+#define SHRT_MAX 32767
+#define USHRT_MAX 65535U
+
+/* On SH-1, type 'int' is 32-bits */
+
+#define INT_MIN (-INT_MAX - 1)
+#define INT_MAX 2147483647
+#define UINT_MAX 4294967295U
+
+/* On SH-1, type 'long' is the same size as type 'int', 32-bits */
+
+#define LONG_MIN (-LONG_MAX - 1)
+#define LONG_MAX 2147483647L
+#define ULONG_MAX 4294967295UL
+
+#define LLONG_MIN (-LLONG_MAX - 1)
+#define LLONG_MAX 9223372036854775807LL
+#define ULLONG_MAX 18446744073709551615ULL
+
+/* A pointer is 4 bytes */
+
+#define PTR_MIN (-PTR_MAX - 1)
+#define PTR_MAX 2147483647
+#define UPTR_MAX 4294967295U
+
+#endif /* __ARCH_RENESAS_INCLUDE_SH1_LIMITS_H */
diff --git a/arch/renesas/include/sh1Ptypes.h b/arch/renesas/include/sh1Ptypes.h
new file mode 100644
index 00000000000..86d7b5b9bb3
--- /dev/null
+++ b/arch/renesas/include/sh1Ptypes.h
@@ -0,0 +1,96 @@
+/****************************************************************************
+ * arch/renesas/include/sh1/types.h
+ *
+ * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly\
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_RENESAS_INCLUDE_SH1_TYPES_H
+#define __ARCH_RENESAS_INCLUDE_SH1_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long long _int64_t;
+typedef unsigned long long _uint64_t;
+#define __INT64_DEFINED
+
+/* A pointer is 4 bytes */
+
+typedef signed int _intptr_t;
+typedef unsigned int _uintptr_t;
+
+/* This is the size of the interrupt state save returned by
+ * up_irq_save()
+ */
+
+typedef unsigned long irqstate_t;
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RENESAS_INCLUDE_SH1_TYPES_H */
diff --git a/arch/sh/include/syscall.h b/arch/renesas/include/syscall.h
similarity index 95%
rename from arch/sh/include/syscall.h
rename to arch/renesas/include/syscall.h
index b26dffcd39c..afe93f69761 100644
--- a/arch/sh/include/syscall.h
+++ b/arch/renesas/include/syscall.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/syscall.h
+ * arch/renesas/include/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* through include/syscall.h or include/sys/sycall.h
*/
-#ifndef __ARCH_SH_INCLUDE_SYSCALL_H
-#define __ARCH_SH_INCLUDE_SYSCALL_H
+#ifndef __ARCH_RENESAS_INCLUDE_SYSCALL_H
+#define __ARCH_RENESAS_INCLUDE_SYSCALL_H
/****************************************************************************
* Included Files
@@ -79,5 +79,5 @@ extern "C"
#endif
#endif
-#endif /* __ARCH_SH_INCLUDE_SYSCALL_H */
+#endif /* __ARCH_RENESAS_INCLUDE_SYSCALL_H */
diff --git a/arch/sh/include/types.h b/arch/renesas/include/types.h
similarity index 94%
rename from arch/sh/include/types.h
rename to arch/renesas/include/types.h
index db6c6178ad3..aca5f944635 100644
--- a/arch/sh/include/types.h
+++ b/arch/renesas/include/types.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/types.h
+ * arch/renesas/include/types.h
*
* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* through sys/types.h
*/
-#ifndef __ARCH_SH_INCLUDE_TYPES_H
-#define __ARCH_SH_INCLUDE_TYPES_H
+#ifndef __ARCH_RENESAS_INCLUDE_TYPES_H
+#define __ARCH_RENESAS_INCLUDE_TYPES_H
/****************************************************************************
* Included Files
@@ -58,4 +58,4 @@
* Public Function Prototypes
****************************************************************************/
-#endif /* __ARCH_SH_INCLUDE_TYPES_H */
+#endif /* __ARCH_RENESAS_INCLUDE_TYPES_H */
diff --git a/arch/sh/include/watchdog.h b/arch/renesas/include/watchdog.h
similarity index 94%
rename from arch/sh/include/watchdog.h
rename to arch/renesas/include/watchdog.h
index 091729833cd..002bc420595 100644
--- a/arch/sh/include/watchdog.h
+++ b/arch/renesas/include/watchdog.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/include/watchdog.h
+ * arch/renesas/include/watchdog.h
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __ARCH_SH_INCLUDE_WATCHDOG_H
-#define __ARCH_SH_INCLUDE_WATCHDOG_H
+#ifndef __ARCH_RENESAS_INCLUDE_WATCHDOG_H
+#define __ARCH_RENESAS_INCLUDE_WATCHDOG_H
/****************************************************************************
* Included Files
@@ -56,4 +56,4 @@
* Public Functions
****************************************************************************/
-#endif /* __ARCH_SH_INCLUDE_WATCHDOG_H */
+#endif /* __ARCH_RENESAS_INCLUDE_WATCHDOG_H */
diff --git a/arch/sh/src/.gitignore b/arch/renesas/src/.gitignore
similarity index 100%
rename from arch/sh/src/.gitignore
rename to arch/renesas/src/.gitignore
diff --git a/arch/sh/src/Makefile b/arch/renesas/src/Makefile
similarity index 99%
rename from arch/sh/src/Makefile
rename to arch/renesas/src/Makefile
index 81e0b5b8c14..14e4bc23122 100644
--- a/arch/sh/src/Makefile
+++ b/arch/renesas/src/Makefile
@@ -1,5 +1,5 @@
############################################################################
-# arch/sh/src/Makefile
+# arch/renesas/src/Makefile
#
# Copyright (C) 2008, 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
diff --git a/arch/renesas/src/README.txt b/arch/renesas/src/README.txt
new file mode 100644
index 00000000000..77c3cdeca87
--- /dev/null
+++ b/arch/renesas/src/README.txt
@@ -0,0 +1,7 @@
+This directory provides a build area for all Renesas and legacy Hitachi
+architectures. The 'common' subdirectory contains source files shared by
+all Renesas architectures; Source files unique to a specific Renesas chip
+architecture are contained in a subdirectory named after the chip. At
+configuration time, additional directories will be linked here: 'board'
+will be a link to the configs/*/src directory; 'chip' will be a link to
+the SH chip sub-directory.
diff --git a/arch/sh/src/common/Kconfig b/arch/renesas/src/common/Kconfig
similarity index 89%
rename from arch/sh/src/common/Kconfig
rename to arch/renesas/src/common/Kconfig
index f6c044427de..cb8747aca76 100644
--- a/arch/sh/src/common/Kconfig
+++ b/arch/renesas/src/common/Kconfig
@@ -3,5 +3,5 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
-if ARCH_SH
+if ARCH_RENESAS
endif
diff --git a/arch/sh/src/common/up_allocateheap.c b/arch/renesas/src/common/up_allocateheap.c
similarity index 98%
rename from arch/sh/src/common/up_allocateheap.c
rename to arch/renesas/src/common/up_allocateheap.c
index ddf287983a1..4148407fb79 100644
--- a/arch/sh/src/common/up_allocateheap.c
+++ b/arch/renesas/src/common/up_allocateheap.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_allocateheap.c
+ * arch/renesas/src/common/up_allocateheap.c
*
* Copyright (C) 2008, 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_arch.h b/arch/renesas/src/common/up_arch.h
similarity index 94%
rename from arch/sh/src/common/up_arch.h
rename to arch/renesas/src/common/up_arch.h
index b624da189d5..5637ddf5a2d 100644
--- a/arch/sh/src/common/up_arch.h
+++ b/arch/renesas/src/common/up_arch.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_arch.h
+ * arch/renesas/src/common/up_arch.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef ___ARCH_SH_SRC_COMMON_UP_ARCH_H
-#define ___ARCH_SH_SRC_COMMON_UP_ARCH_H
+#ifndef ___ARCH_RENESAS_SRC_COMMON_UP_ARCH_H
+#define ___ARCH_RENESAS_SRC_COMMON_UP_ARCH_H
/****************************************************************************
* Included Files
@@ -67,4 +67,4 @@
#endif
-#endif /* ___ARCH_SH_SRC_COMMON_UP_ARCH_H */
+#endif /* ___ARCH_RENESAS_SRC_COMMON_UP_ARCH_H */
diff --git a/arch/sh/src/common/up_assert.c b/arch/renesas/src/common/up_assert.c
similarity index 99%
rename from arch/sh/src/common/up_assert.c
rename to arch/renesas/src/common/up_assert.c
index ec02578cfd0..eaee6f7fec0 100644
--- a/arch/sh/src/common/up_assert.c
+++ b/arch/renesas/src/common/up_assert.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_assert.c
+ * arch/renesas/src/common/up_assert.c
*
* Copyright (C) 2008-2009, 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_blocktask.c b/arch/renesas/src/common/up_blocktask.c
similarity index 99%
rename from arch/sh/src/common/up_blocktask.c
rename to arch/renesas/src/common/up_blocktask.c
index 75ecdef5077..9e8ba57db75 100644
--- a/arch/sh/src/common/up_blocktask.c
+++ b/arch/renesas/src/common/up_blocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_blocktask.c
+ * arch/renesas/src/common/up_blocktask.c
*
* Copyright (C) 2008-2009, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_createstack.c b/arch/renesas/src/common/up_createstack.c
similarity index 99%
rename from arch/sh/src/common/up_createstack.c
rename to arch/renesas/src/common/up_createstack.c
index 3a2a4118119..1bbf3cc8e0f 100644
--- a/arch/sh/src/common/up_createstack.c
+++ b/arch/renesas/src/common/up_createstack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_createstack.c
+ * arch/renesas/src/common/up_createstack.c
*
* Copyright (C) 2008-2009, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_doirq.c b/arch/renesas/src/common/up_doirq.c
similarity index 99%
rename from arch/sh/src/common/up_doirq.c
rename to arch/renesas/src/common/up_doirq.c
index a2996c9f482..9ac9d99aa00 100644
--- a/arch/sh/src/common/up_doirq.c
+++ b/arch/renesas/src/common/up_doirq.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_doirq.c
+ * arch/renesas/src/common/up_doirq.c
*
* Copyright (C) 2008-2009, 2011, 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_exit.c b/arch/renesas/src/common/up_exit.c
similarity index 99%
rename from arch/sh/src/common/up_exit.c
rename to arch/renesas/src/common/up_exit.c
index 1aa9644dba9..f565d3d3d43 100644
--- a/arch/sh/src/common/up_exit.c
+++ b/arch/renesas/src/common/up_exit.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_exit.c
+ * arch/renesas/src/=common/up_exit.c
*
* Copyright (C) 2008-2009, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_idle.c b/arch/renesas/src/common/up_idle.c
similarity index 98%
rename from arch/sh/src/common/up_idle.c
rename to arch/renesas/src/common/up_idle.c
index 0333722347b..c1fc2ed0ce4 100644
--- a/arch/sh/src/common/up_idle.c
+++ b/arch/renesas/src/common/up_idle.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_idle.c
+ * arch/renesas/src/common/up_idle.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_initialize.c b/arch/renesas/src/common/up_initialize.c
similarity index 99%
rename from arch/sh/src/common/up_initialize.c
rename to arch/renesas/src/common/up_initialize.c
index 2cd40a07188..fc61dc0e363 100644
--- a/arch/sh/src/common/up_initialize.c
+++ b/arch/renesas/src/common/up_initialize.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_initialize.c
+ * arch/renesas/src/common/up_initialize.c
*
* Copyright (C) 2008-2010, 2012-2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_internal.h b/arch/renesas/src/common/up_internal.h
similarity index 97%
rename from arch/sh/src/common/up_internal.h
rename to arch/renesas/src/common/up_internal.h
index c055436edb6..e04157953a0 100644
--- a/arch/sh/src/common/up_internal.h
+++ b/arch/renesas/src/common/up_internal.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_internal.h
+ * arch/renesas/src/common/up_internal.h
*
* Copyright (C) 2008-2009, 2012-2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef ___ARCH_SH_SRC_COMMON_UP_INTERNAL_H
-#define ___ARCH_SH_SRC_COMMON_UP_INTERNAL_H
+#ifndef ___ARCH_RENESAS_SRC_COMMON_UP_INTERNAL_H
+#define ___ARCH_RENESAS_SRC_COMMON_UP_INTERNAL_H
/****************************************************************************
* Included Files
@@ -237,4 +237,4 @@ void up_dumpstate(void);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* ___ARCH_SH_SRC_COMMON_UP_INTERNAL_H */
+#endif /* ___ARCH_RENESAS_SRC_COMMON_UP_INTERNAL_H */
diff --git a/arch/sh/src/common/up_interruptcontext.c b/arch/renesas/src/common/up_interruptcontext.c
similarity index 98%
rename from arch/sh/src/common/up_interruptcontext.c
rename to arch/renesas/src/common/up_interruptcontext.c
index 56e4f9478ea..a67f13d0c30 100644
--- a/arch/sh/src/common/up_interruptcontext.c
+++ b/arch/renesas/src/common/up_interruptcontext.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_interruptcontext.c
+ * arch/renesas/src/common/up_interruptcontext.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_lowputs.c b/arch/renesas/src/common/up_lowputs.c
similarity index 98%
rename from arch/sh/src/common/up_lowputs.c
rename to arch/renesas/src/common/up_lowputs.c
index 592ea8177f7..76617901e78 100644
--- a/arch/sh/src/common/up_lowputs.c
+++ b/arch/renesas/src/common/up_lowputs.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_lowputs.c
+ * arch/renesas/src/common/up_lowputs.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_mdelay.c b/arch/renesas/src/common/up_mdelay.c
similarity index 98%
rename from arch/sh/src/common/up_mdelay.c
rename to arch/renesas/src/common/up_mdelay.c
index e7ed4f90156..e3120ce74b4 100644
--- a/arch/sh/src/common/up_mdelay.c
+++ b/arch/renesas/src/common/up_mdelay.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_mdelay.c
+ * arch/renesas/src/common/up_mdelay.c
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_puts.c b/arch/renesas/src/common/up_puts.c
similarity index 98%
rename from arch/sh/src/common/up_puts.c
rename to arch/renesas/src/common/up_puts.c
index 24dccecbe40..5bc2cc8433f 100644
--- a/arch/sh/src/common/up_puts.c
+++ b/arch/renesas/src/common/up_puts.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_puts.c
+ * arch/renesas/src/common/up_puts.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_releasepending.c b/arch/renesas/src/common/up_releasepending.c
similarity index 99%
rename from arch/sh/src/common/up_releasepending.c
rename to arch/renesas/src/common/up_releasepending.c
index 195935ff458..5c3f5748217 100644
--- a/arch/sh/src/common/up_releasepending.c
+++ b/arch/renesas/src/common/up_releasepending.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_releasepending.c
+ * arch/renesas/src/common/up_releasepending.c
*
* Copyright (C) 2008-2009, 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_releasestack.c b/arch/renesas/src/common/up_releasestack.c
similarity index 99%
rename from arch/sh/src/common/up_releasestack.c
rename to arch/renesas/src/common/up_releasestack.c
index 8e01456fdbf..e2b5948b142 100644
--- a/arch/sh/src/common/up_releasestack.c
+++ b/arch/renesas/src/common/up_releasestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_releasestack.c
+ * arch/renesas/src/common/up_releasestack.c
*
* Copyright (C) 2008-2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_reprioritizertr.c b/arch/renesas/src/common/up_reprioritizertr.c
similarity index 99%
rename from arch/sh/src/common/up_reprioritizertr.c
rename to arch/renesas/src/common/up_reprioritizertr.c
index f2d0d1a2266..c476dbad376 100644
--- a/arch/sh/src/common/up_reprioritizertr.c
+++ b/arch/renesas/src/common/up_reprioritizertr.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_reprioritizertr.c
+ * arch/renesas/src/common/up_reprioritizertr.c
*
* Copyright (C) 2008-2009, 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_stackframe.c b/arch/renesas/src/common/up_stackframe.c
similarity index 99%
rename from arch/sh/src/common/up_stackframe.c
rename to arch/renesas/src/common/up_stackframe.c
index 06d2c218a34..811fcd4aad1 100644
--- a/arch/sh/src/common/up_stackframe.c
+++ b/arch/renesas/src/common/up_stackframe.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_stackframe.c
+ * arch/renesas/src/common/up_stackframe.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_udelay.c b/arch/renesas/src/common/up_udelay.c
similarity index 99%
rename from arch/sh/src/common/up_udelay.c
rename to arch/renesas/src/common/up_udelay.c
index 6af5d2f76d4..9f9bda30330 100644
--- a/arch/sh/src/common/up_udelay.c
+++ b/arch/renesas/src/common/up_udelay.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_udelay.c
+ * arch/renesas/src/common/up_udelay.c
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_unblocktask.c b/arch/renesas/src/common/up_unblocktask.c
similarity index 99%
rename from arch/sh/src/common/up_unblocktask.c
rename to arch/renesas/src/common/up_unblocktask.c
index d506d97d094..de3008f98a0 100644
--- a/arch/sh/src/common/up_unblocktask.c
+++ b/arch/renesas/src/common/up_unblocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_unblocktask.c
+ * arch/renesas/src/common/up_unblocktask.c
*
* Copyright (C) 2008-2009, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/common/up_usestack.c b/arch/renesas/src/common/up_usestack.c
similarity index 99%
rename from arch/sh/src/common/up_usestack.c
rename to arch/renesas/src/common/up_usestack.c
index 2da654391ca..de4c4aca95f 100644
--- a/arch/sh/src/common/up_usestack.c
+++ b/arch/renesas/src/common/up_usestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/common/up_usestack.c
+ * arch/renesas/src/common/up_usestack.c
*
* Copyright (C) 2008-2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/Kconfig b/arch/renesas/src/m16c/Kconfig
similarity index 100%
rename from arch/sh/src/m16c/Kconfig
rename to arch/renesas/src/m16c/Kconfig
diff --git a/arch/sh/src/m16c/Make.defs b/arch/renesas/src/m16c/Make.defs
similarity index 98%
rename from arch/sh/src/m16c/Make.defs
rename to arch/renesas/src/m16c/Make.defs
index 6995d37b1e4..d44d9b2f097 100644
--- a/arch/sh/src/m16c/Make.defs
+++ b/arch/renesas/src/m16c/Make.defs
@@ -1,5 +1,5 @@
##############################################################################
-# arch/sh/src/m16c/Make.defs
+# arch/renesas/src/m16c/Make.defs
#
# Copyright (C) 2009, 2014 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/chip.h b/arch/renesas/src/m16c/chip.h
similarity index 98%
rename from arch/sh/src/m16c/chip.h
rename to arch/renesas/src/m16c/chip.h
index 695814d4324..80fbc0e734d 100644
--- a/arch/sh/src/m16c/chip.h
+++ b/arch/renesas/src/m16c/chip.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/m16c/chip.h
+ * arch/renesas/src/m16c/chip.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_SH_SRC_M16C_CHIP_H
-#define __ARCH_SH_SRC_M16C_CHIP_H
+#ifndef __ARCH_RENESAS_SRC_M16C_CHIP_H
+#define __ARCH_RENESAS_SRC_M16C_CHIP_H
/************************************************************************************
* Included Files
@@ -278,4 +278,4 @@ extern uint32_t g_idle_topstack; /* Start of the heap */
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_SH_SRC_M16C_CHIP_H */
+#endif /* __ARCH_RENESAS_SRC_M16C_CHIP_H */
diff --git a/arch/sh/src/m16c/m16c_copystate.c b/arch/renesas/src/m16c/m16c_copystate.c
similarity index 98%
rename from arch/sh/src/m16c/m16c_copystate.c
rename to arch/renesas/src/m16c/m16c_copystate.c
index 2aa48d6c72a..662a6870f63 100644
--- a/arch/sh/src/m16c/m16c_copystate.c
+++ b/arch/renesas/src/m16c/m16c_copystate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/up_copystate.c
+ * arch/renesas/src/m16c/up_copystate.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_dumpstate.c b/arch/renesas/src/m16c/m16c_dumpstate.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_dumpstate.c
rename to arch/renesas/src/m16c/m16c_dumpstate.c
index 7dc1a74ee43..cfd9bd0fdb2 100644
--- a/arch/sh/src/m16c/m16c_dumpstate.c
+++ b/arch/renesas/src/m16c/m16c_dumpstate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_assert.c
+ * arch/renesas/src/m16c/m16c_assert.c
*
* Copyright (C) 2009, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_head.S b/arch/renesas/src/m16c/m16c_head.S
similarity index 99%
rename from arch/sh/src/m16c/m16c_head.S
rename to arch/renesas/src/m16c/m16c_head.S
index 711ce26aaaf..2ed97e4853b 100644
--- a/arch/sh/src/m16c/m16c_head.S
+++ b/arch/renesas/src/m16c/m16c_head.S
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/m16c/m16c_head.S
+ * arch/renesas/src/m16c/m16c_head.S
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_initialstate.c b/arch/renesas/src/m16c/m16c_initialstate.c
similarity index 98%
rename from arch/sh/src/m16c/m16c_initialstate.c
rename to arch/renesas/src/m16c/m16c_initialstate.c
index cc913fde649..abf31035d10 100644
--- a/arch/sh/src/m16c/m16c_initialstate.c
+++ b/arch/renesas/src/m16c/m16c_initialstate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_initialstate.c
+ * arch/renesas/src/m16c/m16c_initialstate.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_irq.c b/arch/renesas/src/m16c/m16c_irq.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_irq.c
rename to arch/renesas/src/m16c/m16c_irq.c
index 2951033206e..ce94eb4d344 100644
--- a/arch/sh/src/m16c/m16c_irq.c
+++ b/arch/renesas/src/m16c/m16c_irq.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_irq.c
+ * arch/renesas/src/m16c/m16c_irq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_lowputc.c b/arch/renesas/src/m16c/m16c_lowputc.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_lowputc.c
rename to arch/renesas/src/m16c/m16c_lowputc.c
index 5ec641fbec6..ecda7343800 100644
--- a/arch/sh/src/m16c/m16c_lowputc.c
+++ b/arch/renesas/src/m16c/m16c_lowputc.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_lowputc.c
+ * arch/renesas/src/m16c/m16c_lowputc.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_schedulesigaction.c b/arch/renesas/src/m16c/m16c_schedulesigaction.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_schedulesigaction.c
rename to arch/renesas/src/m16c/m16c_schedulesigaction.c
index 23d105240bf..69913944663 100644
--- a/arch/sh/src/m16c/m16c_schedulesigaction.c
+++ b/arch/renesas/src/m16c/m16c_schedulesigaction.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_schedulesigaction.c
+ * arch/renesas/src/m16c/m16c_schedulesigaction.c
*
* Copyright (C) 2009-2010, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_serial.c b/arch/renesas/src/m16c/m16c_serial.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_serial.c
rename to arch/renesas/src/m16c/m16c_serial.c
index 4bc1f969ce6..cdbcc2471c8 100644
--- a/arch/sh/src/m16c/m16c_serial.c
+++ b/arch/renesas/src/m16c/m16c_serial.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_serial.c
+ * arch/renesas/src/m16c/m16c_serial.c
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_sigdeliver.c b/arch/renesas/src/m16c/m16c_sigdeliver.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_sigdeliver.c
rename to arch/renesas/src/m16c/m16c_sigdeliver.c
index 40976346f3d..a56448c36bc 100644
--- a/arch/sh/src/m16c/m16c_sigdeliver.c
+++ b/arch/renesas/src/m16c/m16c_sigdeliver.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_sigdeliver.c
+ * arch/renesas/src/m16c/m16c_sigdeliver.c
*
* Copyright (C) 2009-2010, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_timer.h b/arch/renesas/src/m16c/m16c_timer.h
similarity index 98%
rename from arch/sh/src/m16c/m16c_timer.h
rename to arch/renesas/src/m16c/m16c_timer.h
index ff542163222..5c19ff6ed55 100644
--- a/arch/sh/src/m16c/m16c_timer.h
+++ b/arch/renesas/src/m16c/m16c_timer.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/m16c/m16c_timer.h
+ * arch/renesas/src/m16c/m16c_timer.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_SH_SRC_M16C_M16C_TIMER_H
-#define __ARCH_SH_SRC_M16C_M16C_TIMER_H
+#ifndef __ARCH_RENESAS_SRC_M16C_M16C_TIMER_H
+#define __ARCH_RENESAS_SRC_M16C_M16C_TIMER_H
/************************************************************************************
* Included Files
@@ -223,4 +223,4 @@
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_SH_SRC_M16C_M16C_TIMER_H */
+#endif /* __ARCH_RENESAS_SRC_M16C_M16C_TIMER_H */
diff --git a/arch/sh/src/m16c/m16c_timerisr.c b/arch/renesas/src/m16c/m16c_timerisr.c
similarity index 99%
rename from arch/sh/src/m16c/m16c_timerisr.c
rename to arch/renesas/src/m16c/m16c_timerisr.c
index adaa18af022..02570de1cc0 100644
--- a/arch/sh/src/m16c/m16c_timerisr.c
+++ b/arch/renesas/src/m16c/m16c_timerisr.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/m16c/m16c_timerisr.c
+ * arch/renesas/src/m16c/m16c_timerisr.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/m16c/m16c_uart.h b/arch/renesas/src/m16c/m16c_uart.h
similarity index 97%
rename from arch/sh/src/m16c/m16c_uart.h
rename to arch/renesas/src/m16c/m16c_uart.h
index 382411538d3..c50d9b90183 100644
--- a/arch/sh/src/m16c/m16c_uart.h
+++ b/arch/renesas/src/m16c/m16c_uart.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/m16c/m16c_uart.h
+ * arch/renesas/src/m16c/m16c_uart.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_SH_SRC_M16C_M16C_UART_H
-#define __ARCH_SH_SRC_M16C_M16C_UART_H
+#ifndef __ARCH_RENESAS_SRC_M16C_M16C_UART_H
+#define __ARCH_RENESAS_SRC_M16C_M16C_UART_H
/************************************************************************************
* Included Files
@@ -142,4 +142,4 @@
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_SH_SRC_M16C_M16C_UART_H */
+#endif /* __ARCH_RENESAS_SRC_M16C_M16C_UART_H */
diff --git a/arch/sh/src/m16c/m16c_vectors.S b/arch/renesas/src/m16c/m16c_vectors.S
similarity index 99%
rename from arch/sh/src/m16c/m16c_vectors.S
rename to arch/renesas/src/m16c/m16c_vectors.S
index b59f179864f..0925db3e4ed 100644
--- a/arch/sh/src/m16c/m16c_vectors.S
+++ b/arch/renesas/src/m16c/m16c_vectors.S
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/m16c/m16c_vectors.S
+ * arch/renesas/src/m16c/m16c_vectors.S
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/Kconfig b/arch/renesas/src/sh1/Kconfig
similarity index 100%
rename from arch/sh/src/sh1/Kconfig
rename to arch/renesas/src/sh1/Kconfig
diff --git a/arch/sh/src/sh1/Make.defs b/arch/renesas/src/sh1/Make.defs
similarity index 98%
rename from arch/sh/src/sh1/Make.defs
rename to arch/renesas/src/sh1/Make.defs
index 180034a72d2..adbfd361986 100644
--- a/arch/sh/src/sh1/Make.defs
+++ b/arch/renesas/src/sh1/Make.defs
@@ -1,5 +1,5 @@
##############################################################################
-# arch/sh/src/sh1/Make.defs
+# arch/renesas/src/sh1/Make.defs
#
# Copyright (C) 2008, 2009, 2014 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/chip.h b/arch/renesas/src/sh1/chip.h
similarity index 95%
rename from arch/sh/src/sh1/chip.h
rename to arch/renesas/src/sh1/chip.h
index 490b20973e8..4459bdcadb3 100644
--- a/arch/sh/src/sh1/chip.h
+++ b/arch/renesas/src/sh1/chip.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/sh1/chip.h
+ * arch/renesas/src/sh1/chip.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_SH_SRC_SH1_CHIP_H
-#define __ARCH_SH_SRC_SH1_CHIP_H
+#ifndef __ARCH_RENESAS_SRC_SH1_CHIP_H
+#define __ARCH_RENESAS_SRC_SH1_CHIP_H
/************************************************************************************
* Included Files
@@ -71,4 +71,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_SH_SRC_SH1_CHIP_H */
+#endif /* __ARCH_RENESAS_SRC_SH1_CHIP_H */
diff --git a/arch/sh/src/sh1/sh1_703x.h b/arch/renesas/src/sh1/sh1_703x.h
similarity index 99%
rename from arch/sh/src/sh1/sh1_703x.h
rename to arch/renesas/src/sh1/sh1_703x.h
index 87f2c1bcd17..ba5ab4d6270 100644
--- a/arch/sh/src/sh1/sh1_703x.h
+++ b/arch/renesas/src/sh1/sh1_703x.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/sh/src/sh1/sh1_703x.h
+ * arch/renesas/src/sh1/sh1_703x.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_SH_SRC_SH1_703X_H
-#define __ARCH_SH_SRC_SH1_703X_H
+#ifndef __ARCH_RENESAS_SRC_SH1_703X_H
+#define __ARCH_RENESAS_SRC_SH1_703X_H
/************************************************************************************
* Included Files
@@ -459,7 +459,7 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_SH_SRC_SH1_703X_H */
+#endif /* __ARCH_RENESAS_SRC_SH1_703X_H */
diff --git a/arch/sh/src/sh1/sh1_copystate.c b/arch/renesas/src/sh1/sh1_copystate.c
similarity index 98%
rename from arch/sh/src/sh1/sh1_copystate.c
rename to arch/renesas/src/sh1/sh1_copystate.c
index 57fa2d46386..8b2404ca257 100644
--- a/arch/sh/src/sh1/sh1_copystate.c
+++ b/arch/renesas/src/sh1/sh1_copystate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/up_copystate.c
+ * arch/renesas/src/sh1/up_copystate.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_dumpstate.c b/arch/renesas/src/sh1/sh1_dumpstate.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_dumpstate.c
rename to arch/renesas/src/sh1/sh1_dumpstate.c
index e9b0e590784..4609b435591 100644
--- a/arch/sh/src/sh1/sh1_dumpstate.c
+++ b/arch/renesas/src/sh1/sh1_dumpstate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_assert.c
+ * arch/renesas/src/sh1/sh1_assert.c
*
* Copyright (C) 2008-2009, 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_head.S b/arch/renesas/src/sh1/sh1_head.S
similarity index 99%
rename from arch/sh/src/sh1/sh1_head.S
rename to arch/renesas/src/sh1/sh1_head.S
index e46522da885..695e0d86537 100644
--- a/arch/sh/src/sh1/sh1_head.S
+++ b/arch/renesas/src/sh1/sh1_head.S
@@ -1,5 +1,5 @@
/*****************************************************************************
- * arch/sh/src/sh1/sh1_head.S
+ * arch/renesas/src/sh1/sh1_head.S
*
* Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_initialstate.c b/arch/renesas/src/sh1/sh1_initialstate.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_initialstate.c
rename to arch/renesas/src/sh1/sh1_initialstate.c
index 984829a370d..0575b0300f6 100644
--- a/arch/sh/src/sh1/sh1_initialstate.c
+++ b/arch/renesas/src/sh1/sh1_initialstate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_initialstate.c
+ * arch/renesas/src/sh1/sh1_initialstate.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_irq.c b/arch/renesas/src/sh1/sh1_irq.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_irq.c
rename to arch/renesas/src/sh1/sh1_irq.c
index bb598773402..8fe7241c607 100644
--- a/arch/sh/src/sh1/sh1_irq.c
+++ b/arch/renesas/src/sh1/sh1_irq.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_irq.c
+ * arch/renesas/src/sh1/sh1_irq.c
*
* Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_lowputc.c b/arch/renesas/src/sh1/sh1_lowputc.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_lowputc.c
rename to arch/renesas/src/sh1/sh1_lowputc.c
index 8b423b75b8f..b04612b7024 100644
--- a/arch/sh/src/sh1/sh1_lowputc.c
+++ b/arch/renesas/src/sh1/sh1_lowputc.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_lowputc.c
+ * arch/renesas/src/sh1/sh1_lowputc.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_saveusercontext.S b/arch/renesas/src/sh1/sh1_saveusercontext.S
similarity index 99%
rename from arch/sh/src/sh1/sh1_saveusercontext.S
rename to arch/renesas/src/sh1/sh1_saveusercontext.S
index 8084e5bd0d8..e2fcebd7ef3 100644
--- a/arch/sh/src/sh1/sh1_saveusercontext.S
+++ b/arch/renesas/src/sh1/sh1_saveusercontext.S
@@ -1,5 +1,5 @@
/**************************************************************************
- * arch/sh/src/sh1/sh1_saveusercontext.S
+ * arch/renesas/src/sh1/sh1_saveusercontext.S
*
* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_schedulesigaction.c b/arch/renesas/src/sh1/sh1_schedulesigaction.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_schedulesigaction.c
rename to arch/renesas/src/sh1/sh1_schedulesigaction.c
index 11c241ddea3..503272b5a95 100644
--- a/arch/sh/src/sh1/sh1_schedulesigaction.c
+++ b/arch/renesas/src/sh1/sh1_schedulesigaction.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_schedulesigaction.c
+ * arch/renesas/src/sh1/sh1_schedulesigaction.c
*
* Copyright (C) 2008-2010, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_serial.c b/arch/renesas/src/sh1/sh1_serial.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_serial.c
rename to arch/renesas/src/sh1/sh1_serial.c
index 44c9cf8a934..ff9246fad99 100644
--- a/arch/sh/src/sh1/sh1_serial.c
+++ b/arch/renesas/src/sh1/sh1_serial.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_serial.c
+ * arch/renesas/src/sh1/sh1_serial.c
*
* Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_sigdeliver.c b/arch/renesas/src/sh1/sh1_sigdeliver.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_sigdeliver.c
rename to arch/renesas/src/sh1/sh1_sigdeliver.c
index 85b8f57978d..8662cb47c5f 100644
--- a/arch/sh/src/sh1/sh1_sigdeliver.c
+++ b/arch/renesas/src/sh1/sh1_sigdeliver.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_sigdeliver.c
+ * arch/renesas/src/common/up_sigdeliver.c
*
* Copyright (C) 2008-2010, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_timerisr.c b/arch/renesas/src/sh1/sh1_timerisr.c
similarity index 99%
rename from arch/sh/src/sh1/sh1_timerisr.c
rename to arch/renesas/src/sh1/sh1_timerisr.c
index 08647be112f..c291735ad22 100644
--- a/arch/sh/src/sh1/sh1_timerisr.c
+++ b/arch/renesas/src/sh1/sh1_timerisr.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sh/src/sh1/sh1_timerisr.c
+ * arch/renesas/src/sh1/sh1_timerisr.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/sh1/sh1_vector.S b/arch/renesas/src/sh1/sh1_vector.S
similarity index 99%
rename from arch/sh/src/sh1/sh1_vector.S
rename to arch/renesas/src/sh1/sh1_vector.S
index 396e33cd276..78ec75f310c 100644
--- a/arch/sh/src/sh1/sh1_vector.S
+++ b/arch/renesas/src/sh1/sh1_vector.S
@@ -1,5 +1,5 @@
/*****************************************************************************
- * arch/sh/src/sh1/sh1_vector.S
+ * arch/renesas/src/sh1/sh1_vector.S
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sh/src/README.txt b/arch/sh/src/README.txt
deleted file mode 100644
index 3cbd17c0fd8..00000000000
--- a/arch/sh/src/README.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-This directory provides a build area for all SH architectures.
-The 'common' subdirectory contains source files shared by all SH
-architectures; Source files unique to a specific SH chip
-architecture are contained in a subdirectory named after the chip.
-At configuration time, additional directories will be linked here:
-'build' will be a link to the configs/*/src directory; 'chip' will
-be a link to the SH chip sub-directory.
diff --git a/arch/sim/Kconfig b/arch/sim/Kconfig
index 614b8e7ef7e..975d0449a5b 100644
--- a/arch/sim/Kconfig
+++ b/arch/sim/Kconfig
@@ -211,8 +211,33 @@ config SIM_TCNWAITERS
default 4
depends on !POLL_DISABLE && SIM_TOUCHSCREEN
---help---
- The maximum number of threads that can be waiting on poll() for a touchscreen event.
- Default: 4
+ The maximum number of threads that can be waiting on poll() for a
+ touchscreen event. Default: 4
+
+config SIM_IOEXPANDER
+ bool "Simulated I/O Expander"
+ default n
+ depends on IOEXPANDER
+ select IOEXPANDER_INT_ENABLE
+ ---help---
+ Build a simple, simulated I/O Expander chip simulation (for testing
+ purposes only).
+
+if SIM_IOEXPANDER
+
+config SIM_INT_NCALLBACKS
+ int "Max number of interrupt callbacks"
+ default 4
+ ---help---
+ This is the maximum number of interrupt callbacks supported
+
+config SIM_INT_POLLDELAY
+ int "Interrupt poll delay (used)"
+ default 500000
+ ---help---
+ This microsecond delay defines the polling rate for missed interrupts.
+
+endif # SIM_IOEXPANDER
config SIM_SPIFLASH
bool "Simulated SPI FLASH with SMARTFS"
@@ -395,4 +420,4 @@ config SIM_QSPIFLASH_PAGESIZE
"wrap" causing the initial data sent to be overwritten.
This is consistent with standard SPI FLASH operation.
-endif
+endif # ARCH_SIM
diff --git a/arch/sim/include/arch.h b/arch/sim/include/arch.h
index 29cf6495fce..83fdc737c45 100644
--- a/arch/sim/include/arch.h
+++ b/arch/sim/include/arch.h
@@ -37,8 +37,8 @@
* only indirectly through nuttx/arch.h
*/
-#ifndef __ARCH_ARCH_H
-#define __ARCH_ARCH_H
+#ifndef __ARCH_SIM_INCLUDE_ARCH_H
+#define __ARCH_SIM_INCLUDE_ARCH_H
/****************************************************************************
* Included Files
@@ -77,5 +77,5 @@ extern "C"
}
#endif
-#endif /* __ARCH_ARCH_H */
+#endif /* __ARCH_SIM_INCLUDE_ARCH_H */
diff --git a/arch/sim/include/irq.h b/arch/sim/include/irq.h
index 9a9781dda46..ae95625ace7 100644
--- a/arch/sim/include/irq.h
+++ b/arch/sim/include/irq.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * irq.h
+ * arch/sim/include/irq.h
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_IRQ_H
-#define __ARCH_IRQ_H
+#ifndef __ARCH_SIM_INCLUDE_IRQ_H
+#define __ARCH_SIM_INCLUDE_IRQ_H
/****************************************************************************
* Included Files
@@ -132,5 +132,5 @@ extern "C"
}
#endif
-#endif /* __ARCH_IRQ_H */
+#endif /* __ARCH_SIM_INCLUDE_IRQ_H */
diff --git a/arch/sim/include/tls.h b/arch/sim/include/tls.h
index ae2cf3b85a2..6df7505714b 100644
--- a/arch/sim/include/tls.h
+++ b/arch/sim/include/tls.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/sin/include/tls.h
+ * arch/sim/include/tls.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile
index fdac7796be5..69d8e85b1e3 100644
--- a/arch/sim/src/Makefile
+++ b/arch/sim/src/Makefile
@@ -85,6 +85,10 @@ ifeq ($(CONFIG_DEV_CONSOLE),y)
HOSTSRCS += up_simuart.c
endif
+ifeq ($(CONFIG_ONESHOT),y)
+ CSRCS += up_oneshot.c
+endif
+
ifeq ($(CONFIG_NX_LCDDRIVER),y)
CSRCS += board_lcd.c
else
@@ -103,6 +107,10 @@ endif
endif
endif
+ifeq ($(CONFIG_SIM_IOEXPANDER),y)
+ CSRCS += up_ioexpander.c
+endif
+
ifeq ($(CONFIG_ELF),y)
CSRCS += up_elf.c
endif
diff --git a/arch/sim/src/nuttx-names.dat b/arch/sim/src/nuttx-names.dat
index 13c064b1778..759743be534 100644
--- a/arch/sim/src/nuttx-names.dat
+++ b/arch/sim/src/nuttx-names.dat
@@ -88,6 +88,7 @@ setenv NXsetenv
setlogmask NXsetlogmask
setsockopt NXsetsockopt
sigaction NXsigaction
+sigaddset NXsigaddset
sigdelset NXsigdelset
sigemptyset NXsigemptyset
sigfillset NXsigfillset
diff --git a/arch/sim/src/up_internal.h b/arch/sim/src/up_internal.h
index 1304419af34..658ec0539bc 100644
--- a/arch/sim/src/up_internal.h
+++ b/arch/sim/src/up_internal.h
@@ -296,6 +296,13 @@ int up_buttonevent(int x, int y, int buttons);
int sim_ajoy_initialize(void);
#endif
+/* up_ioexpander.c ********************************************************/
+
+#ifdef CONFIG_SIM_IOEXPANDER
+struct ioexpander_dev_s;
+FAR struct ioexpander_dev_s *sim_ioexpander_initialize(void);
+#endif
+
/* up_tapdev.c ************************************************************/
#if defined(CONFIG_NET_ETHERNET) && !defined(__CYGWIN__)
diff --git a/arch/sim/src/up_ioexpander.c b/arch/sim/src/up_ioexpander.c
new file mode 100644
index 00000000000..584a2e97f69
--- /dev/null
+++ b/arch/sim/src/up_ioexpander.c
@@ -0,0 +1,866 @@
+/****************************************************************************
+ * arch/sim/src/up_ioexpander.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "up_internal.h"
+
+#ifdef CONFIG_SIM_IOEXPANDER
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SIM_POLLDELAY (CONFIG_SIM_INT_POLLDELAY / USEC_PER_TICK)
+
+#define SIM_INT_ENABLED(d,p) \
+ (((d)->intenab & ((ioe_pinset_t)1 << (p))) != 0)
+#define SIM_INT_DISABLED(d,p) \
+ (((d)->intenab & ((ioe_pinset_t)1 << (p))) == 0)
+
+#define SIM_LEVEL_SENSITIVE(d,p) \
+ (((d)->trigger & ((ioe_pinset_t)1 << (p))) == 0)
+#define SIM_LEVEL_HIGH(d,p) \
+ (((d)->level[0] & ((ioe_pinset_t)1 << (p))) != 0)
+#define SIM_LEVEL_LOW(d,p) \
+ (((d)->level[1] & ((ioe_pinset_t)1 << (p))) != 0)
+
+#define SIM_EDGE_SENSITIVE(d,p) \
+ (((d)->trigger & ((ioe_pinset_t)1 << (p))) != 0)
+#define SIM_EDGE_RISING(d,p) \
+ (((d)->level[0] & ((ioe_pinset_t)1 << (p))) != 0)
+#define SIM_EDGE_FALLING(d,p) \
+ (((d)->level[1] & ((ioe_pinset_t)1 << (p))) != 0)
+#define SIM_EDGE_BOTH(d,p) \
+ (SIM_LEVEL_RISING(d,p) && SIM_LEVEL_FALLING(d,p))
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This type represents on registered pin interrupt callback */
+
+struct sim_callback_s
+{
+ ioe_pinset_t pinset; /* Set of pin interrupts that will generate
+ * the callback. */
+ ioe_callback_t cbfunc; /* The saved callback function pointer */
+ FAR void *cbarg; /* Callback argument */
+};
+
+/* This structure represents the state of the I/O Expander driver */
+
+struct sim_dev_s
+{
+ struct ioexpander_dev_s dev; /* Nested structure to allow casting as public gpio
+ * expander. */
+ ioe_pinset_t inpins; /* Pins select as inputs */
+ ioe_pinset_t invert; /* Pin value inversion */
+ ioe_pinset_t outval; /* Value of output pins */
+ ioe_pinset_t inval; /* Simulated input register */
+ ioe_pinset_t intenab; /* Interrupt enable */
+ ioe_pinset_t last; /* Last pin inputs (for detection of changes) */
+ ioe_pinset_t trigger; /* Bit encoded: 0=level 1=edge */
+ ioe_pinset_t level[2]; /* Bit encoded: 01=high/rising, 10 low/falling, 11 both */
+
+ WDOG_ID wdog; /* Timer used to poll for interrupt simulation */
+ struct work_s work; /* Supports the interrupt handling "bottom half" */
+
+ /* Saved callback information for each I/O expander client */
+
+ struct sim_callback_s cb[CONFIG_SIM_INT_NCALLBACKS];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* I/O Expander Methods */
+
+static int sim_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ int dir);
+static int sim_option(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ int opt, void *regval);
+static int sim_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ bool value);
+static int sim_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ FAR bool *value);
+#ifdef CONFIG_IOEXPANDER_MULTIPIN
+static int sim_multiwritepin(FAR struct ioexpander_dev_s *dev,
+ FAR uint8_t *pins, FAR bool *values, int count);
+static int sim_multireadpin(FAR struct ioexpander_dev_s *dev,
+ FAR uint8_t *pins, FAR bool *values, int count);
+#endif
+static FAR void *sim_attach(FAR struct ioexpander_dev_s *dev,
+ ioe_pinset_t pinset, ioe_callback_t callback, FAR void *arg);
+static int sim_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle);
+
+static ioe_pinset_t sim_int_update(FAR struct sim_dev_s *priv);
+static void sim_interrupt_work(void *arg);
+static void sim_interrupt(int argc, wdparm_t arg1, ...);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Since only single device is supported, the driver state structure may as
+ * well be pre-allocated.
+ */
+
+static struct sim_dev_s g_ioexpander;
+
+/* I/O expander vtable */
+
+static const struct ioexpander_ops_s g_sim_ops =
+{
+ sim_direction,
+ sim_option,
+ sim_writepin,
+ sim_readpin,
+ sim_readpin
+#ifdef CONFIG_IOEXPANDER_MULTIPIN
+ , sim_multiwritepin
+ , sim_multireadpin
+ , sim_multireadpin
+#endif
+ , sim_attach
+ , sim_detach
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sim_direction
+ *
+ * Description:
+ * Set the direction of an ioexpander pin. Required.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pin - The index of the pin to alter in this call
+ * dir - One of the IOEXPANDER_DIRECTION_ macros
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+static int sim_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ int direction)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+
+ DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS &&
+ (direction == IOEXPANDER_DIRECTION_IN ||
+ direction == IOEXPANDER_DIRECTION_OUT));
+
+ gpioinfo("pin=%u direction=%s\n",
+ pin, (direction == IOEXPANDER_DIRECTION_IN) ? "IN" : "OUT");
+
+ /* Set the pin direction */
+
+ if (direction == IOEXPANDER_DIRECTION_IN)
+ {
+ /* Configure pin as input. */
+
+ priv->inpins |= (1 << pin);
+ }
+ else /* if (direction == IOEXPANDER_DIRECTION_OUT) */
+ {
+ /* Configure pin as output. If a bit in this register is cleared to
+ * 0, the corresponding port pin is enabled as an output.
+ *
+ * REVISIT: The value of output has not been selected! This might
+ * put a glitch on the output.
+ */
+
+ priv->inpins &= ~(1 << pin);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sim_option
+ *
+ * Description:
+ * Set pin options. Required.
+ * Since all IO expanders have various pin options, this API allows setting
+ * pin options in a flexible way.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pin - The index of the pin to alter in this call
+ * opt - One of the IOEXPANDER_OPTION_ macros
+ * val - The option's value
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+static int sim_option(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ int opt, FAR void *value)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+ int ret = -ENOSYS;
+
+ DEBUGASSERT(priv != NULL);
+
+ gpioinfo("pin=%u option=%u\n", pin, opt);
+
+ /* Check for pin polarity inversion. The Polarity Inversion Register
+ * allows polarity inversion of pins defined as inputs by the
+ * Configuration Register. If a bit in this register is set, the
+ * corresponding port pin's polarity is inverted. If a bit in this
+ * register is cleared, the corresponding port pin's original polarity
+ * is retained.
+ */
+
+ if (opt == IOEXPANDER_OPTION_INVERT)
+ {
+ if ((uintptr_t)value == IOEXPANDER_OPTION_INVERT)
+ {
+ priv->invert |= (1 << pin);
+ }
+ else
+ {
+ priv->invert &= ~(1 << pin);
+ }
+ }
+
+ /* Interrupt configuration */
+
+ else if (opt == IOEXPANDER_OPTION_INTCFG)
+ {
+ ioe_pinset_t bit = ((ioe_pinset_t)1 << pin);
+
+ ret = OK;
+ switch ((uintptr_t)value)
+ {
+ case IOEXPANDER_VAL_HIGH: /* Interrupt on high level */
+ priv->intenab |= bit;
+ priv->trigger &= ~bit;
+ priv->level[0] |= bit;
+ priv->level[1] &= ~bit;
+ break;
+
+ case IOEXPANDER_VAL_LOW: /* Interrupt on low level */
+ priv->intenab |= bit;
+ priv->trigger &= ~bit;
+ priv->level[0] &= ~bit;
+ priv->level[1] |= bit;
+ break;
+
+ case IOEXPANDER_VAL_RISING: /* Interrupt on rising edge */
+ priv->intenab |= bit;
+ priv->trigger |= bit;
+ priv->level[0] |= bit;
+ priv->level[1] &= ~bit;
+ break;
+
+ case IOEXPANDER_VAL_FALLING: /* Interrupt on falling edge */
+ priv->intenab |= bit;
+ priv->trigger |= bit;
+ priv->level[0] &= ~bit;
+ priv->level[1] |= bit;
+ break;
+
+ case IOEXPANDER_VAL_BOTH: /* Interrupt on both edges */
+ priv->intenab |= bit;
+ priv->trigger |= bit;
+ priv->level[0] |= bit;
+ priv->level[1] |= bit;
+ break;
+
+ case IOEXPANDER_VAL_DISABLE:
+ priv->trigger &= ~bit;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sim_writepin
+ *
+ * Description:
+ * Set the pin level. Required.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pin - The index of the pin to alter in this call
+ * val - The pin level. Usually TRUE will set the pin high,
+ * except if OPTION_INVERT has been set on this pin.
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+static int sim_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ bool value)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+
+ DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS);
+
+ gpioinfo("pin=%u value=%u\n", pin, (unsigned int)value);
+
+ /* Set output pins default value (before configuring it as output) The
+ * Output Port Register shows the outgoing logic levels of the pins
+ * defined as outputs by the Configuration Register.
+ */
+
+ if (value && (priv->invert & (1 << pin)) == 0)
+ {
+ priv->outval |= (1 << pin);
+ }
+ else
+ {
+ priv->outval &= ~(1 << pin);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sim_readpin
+ *
+ * Description:
+ * Read the actual PIN level. This can be different from the last value written
+ * to this pin. Required.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pin - The index of the pin
+ * valptr - Pointer to a buffer where the pin level is stored. Usually TRUE
+ * if the pin is high, except if OPTION_INVERT has been set on this pin.
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+static int sim_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
+ FAR bool *value)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+ ioe_pinset_t inval;
+ bool retval;
+
+ DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS && value != NULL);
+
+ gpioinfo("pin=%u\n", pin);
+
+ /* Is this an output pin? */
+
+ if ((priv->inpins & (1 << pin)) != 0)
+ {
+ inval = priv->inval;
+ }
+ else
+ {
+ inval = priv->outval;
+ }
+
+ /* Return 0 or 1 to indicate the state of pin */
+
+ retval = (((inval >> pin) & 1) != 0);
+ *value = ((priv->invert & (1 << pin)) != 0) ? !retval : retval;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sim_multiwritepin
+ *
+ * Description:
+ * Set the pin level for multiple pins. This routine may be faster than
+ * individual pin accesses. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pins - The list of pin indexes to alter in this call
+ * val - The list of pin levels.
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_IOEXPANDER_MULTIPIN
+static int sim_multiwritepin(FAR struct ioexpander_dev_s *dev,
+ FAR uint8_t *pins, FAR bool *values,
+ int count)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+ uint8_t pin;
+ int i;
+
+ gpioinfo("count=%d\n", count);
+ DEBUGASSERT(priv != NULL && pins != NULL && values != NULL && count > 0);
+
+ /* Apply the user defined changes */
+
+ for (i = 0; i < count; i++)
+ {
+ pin = pins[i];
+ DEBUGASSERT(pin < CONFIG_IOEXPANDER_NPINS);
+
+ if (values[i] && (priv->invert & (1 << pin)) == 0)
+ {
+ priv->outval |= (1 << pin);
+ }
+ else
+ {
+ priv->outval &= ~(1 << pin);
+ }
+ }
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: sim_multireadpin
+ *
+ * Description:
+ * Read the actual level for multiple pins. This routine may be faster than
+ * individual pin accesses. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pin - The list of pin indexes to read
+ * valptr - Pointer to a buffer where the pin levels are stored.
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_IOEXPANDER_MULTIPIN
+static int sim_multireadpin(FAR struct ioexpander_dev_s *dev,
+ FAR uint8_t *pins, FAR bool *values,
+ int count)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+ ioe_pinset_t inval;
+ uint8_t pin;
+ bool pinval;
+ int i;
+
+ gpioinfo("count=%d\n", count);
+ DEBUGASSERT(priv != NULL && pins != NULL && values != NULL && count > 0);
+
+ /* Update the input status with the 8 bits read from the expander */
+
+ for (i = 0; i < count; i++)
+ {
+ pin = pins[i];
+ DEBUGASSERT(pin < CONFIG_IOEXPANDER_NPINS);
+
+ /* Is this an output pin? */
+
+ if ((priv->inpins & (1 << pin)) != 0)
+ {
+ inval = priv->inval;
+ }
+ else
+ {
+ inval = priv->outval;
+ }
+
+ pinval = ((inval & (1 << pin)) != 0);
+ values[i] = ((priv->invert & (1 << pin)) != 0) ? !pinval : pinval;
+ }
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: sim_attach
+ *
+ * Description:
+ * Attach and enable a pin interrupt callback function.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * pinset - The set of pin events that will generate the callback
+ * callback - The pointer to callback function. NULL will detach the
+ * callback.
+ * arg - User-provided callback argument
+ *
+ * Returned Value:
+ * A non-NULL handle value is returned on success. This handle may be
+ * used later to detach and disable the pin interrupt.
+ *
+ ****************************************************************************/
+
+static FAR void *sim_attach(FAR struct ioexpander_dev_s *dev,
+ ioe_pinset_t pinset, ioe_callback_t callback,
+ FAR void *arg)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+ FAR void *handle = NULL;
+ int i;
+
+ gpioinfo("pinset=%lx callback=%p arg=%p\n",
+ (unsigned long)pinset, callback, arg);
+
+ /* Find and available in entry in the callback table */
+
+ for (i = 0; i < CONFIG_SIM_INT_NCALLBACKS; i++)
+ {
+ /* Is this entry available (i.e., no callback attached) */
+
+ if (priv->cb[i].cbfunc == NULL)
+ {
+ /* Yes.. use this entry */
+
+ priv->cb[i].pinset = pinset;
+ priv->cb[i].cbfunc = callback;
+ priv->cb[i].cbarg = arg;
+ handle = &priv->cb[i];
+ break;
+ }
+ }
+
+ return handle;
+}
+
+/****************************************************************************
+ * Name: sim_detach
+ *
+ * Description:
+ * Detach and disable a pin interrupt callback function.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * handle - The non-NULL opaque value return by sim_attch()
+ *
+ * Returned Value:
+ * 0 on success, else a negative error code
+ *
+ ****************************************************************************/
+
+static int sim_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)dev;
+ FAR struct sim_callback_s *cb = (FAR struct sim_callback_s *)handle;
+
+ gpioinfo("handle=%p\n", handle);
+
+ DEBUGASSERT(priv != NULL && cb != NULL);
+ DEBUGASSERT((uintptr_t)cb >= (uintptr_t)&priv->cb[0] &&
+ (uintptr_t)cb <= (uintptr_t)&priv->cb[CONFIG_SIM_INT_NCALLBACKS-1]);
+ UNUSED(priv);
+
+ cb->pinset = 0;
+ cb->cbfunc = NULL;
+ cb->cbarg = NULL;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sim_int_update
+ *
+ * Description:
+ * Check for pending interrupts.
+ *
+ ****************************************************************************/
+
+static ioe_pinset_t sim_int_update(FAR struct sim_dev_s *priv)
+{
+ ioe_pinset_t toggles;
+ ioe_pinset_t diff;
+ ioe_pinset_t input;
+ ioe_pinset_t intstat;
+ bool pinval;
+ int pin;
+ int i;
+
+ /* First, toggle all input bits that have associated, attached interrupt
+ * handler. This is a crude simulation for toggle interrupt inputs.
+ */
+
+ toggles = 0;
+ for (i = 0; i < CONFIG_SIM_INT_NCALLBACKS; i++)
+ {
+ /* Is there a callback attached? */
+
+ if (priv->cb[i].cbfunc != NULL)
+ {
+ /* Yes, add the input pins to set of pins to toggle */
+
+ toggles |= (priv->cb[i].pinset & priv->inpins);
+ }
+ }
+
+ priv->inval = (priv->inval & ~toggles) | (~priv->inval & toggles);
+
+ /* Check the changed bits from last read (Only applies to input pins) */
+
+ input = priv->inval;
+ diff = priv->last ^ input;
+ if (diff != 0)
+ {
+ gpioinfo("toggles=%lx inval=%lx last=%lx diff=%lx\n",
+ (unsigned long)toggles, (unsigned long)priv->inval,
+ (unsigned long)priv->last, (unsigned long)diff);
+ }
+
+ priv->last = input;
+ intstat = 0;
+
+ /* Check for changes in pins that could generate an interrupt. */
+
+ for (pin = 0; pin < CONFIG_IOEXPANDER_NPINS; pin++)
+ {
+ /* Get the value of the pin (accounting for inversion) */
+
+ pinval = ((input & 1) != 0);
+ if ((priv->invert & (1 << pin)) != 0)
+ {
+ pinval = !pinval;
+ }
+
+ if (SIM_INT_DISABLED(priv, pin))
+ {
+ /* Interrupts disabled on this pin. Do nothing.. just skip to the
+ * next pin.
+ */
+ }
+ else if (SIM_EDGE_SENSITIVE(priv, pin))
+ {
+ /* Edge triggered. Was there a change in the level? */
+
+ if ((diff & 1) != 0)
+ {
+ /* Set interrupt as a function of edge type */
+
+ if ((!pinval && SIM_EDGE_FALLING(priv, pin)) ||
+ ( pinval && SIM_EDGE_RISING(priv, pin)))
+ {
+ intstat |= 1 << pin;
+ }
+ }
+ }
+ else /* if (SIM_LEVEL_SENSITIVE(priv, pin)) */
+ {
+ /* Level triggered. Set intstat if match in level type. */
+
+ if ((pinval && SIM_LEVEL_HIGH(priv, pin)) ||
+ (!pinval && SIM_LEVEL_LOW(priv, pin)))
+ {
+ intstat |= 1 << pin;
+ }
+ }
+
+ diff >>= 1;
+ input >>= 1;
+ }
+
+ return intstat;
+}
+
+/****************************************************************************
+ * Name: sim_interrupt_work
+ *
+ * Description:
+ * Handle GPIO interrupt events (this function actually executes in the
+ * context of the worker thread).
+ *
+ ****************************************************************************/
+
+static void sim_interrupt_work(void *arg)
+{
+ FAR struct sim_dev_s *priv = (FAR struct sim_dev_s *)arg;
+ ioe_pinset_t intstat;
+ int ret;
+ int i;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Update the input status with the 32 bits read from the expander */
+
+ intstat = sim_int_update(priv);
+ if (intstat != 0)
+ {
+ gpioinfo("intstat=%lx\n", (unsigned long)intstat);
+
+ /* Perform pin interrupt callbacks */
+
+ for (i = 0; i < CONFIG_SIM_INT_NCALLBACKS; i++)
+ {
+ /* Is this entry valid (i.e., callback attached)? */
+
+ if (priv->cb[i].cbfunc != NULL)
+ {
+ /* Did any of the requested pin interrupts occur? */
+
+ ioe_pinset_t match = intstat & priv->cb[i].pinset;
+ if (match != 0)
+ {
+ /* Yes.. perform the callback */
+
+ (void)priv->cb[i].cbfunc(&priv->dev, match,
+ priv->cb[i].cbarg);
+ }
+ }
+ }
+ }
+
+ /* Re-start the poll timer */
+
+ ret = wd_start(priv->wdog, SIM_POLLDELAY, (wdentry_t)sim_interrupt,
+ 1, (wdparm_t)priv);
+ if (ret < 0)
+ {
+ gpioerr("ERROR: Failed to start poll timer\n");
+ }
+}
+
+/****************************************************************************
+ * Name: sim_interrupt
+ *
+ * Description:
+ * The poll timer has expired; check for missed interrupts
+ *
+ * Input Parameters:
+ * Standard wdog expiration arguments.
+ *
+ ****************************************************************************/
+
+static void sim_interrupt(int argc, wdparm_t arg1, ...)
+{
+ FAR struct sim_dev_s *priv;
+
+ DEBUGASSERT(argc == 1);
+ priv = (FAR struct sim_dev_s *)arg1;
+ DEBUGASSERT(priv != NULL);
+
+ /* Defer interrupt processing to the worker thread. This is not only
+ * much kinder in the use of system resources but is probably necessary
+ * to access the I/O expander device.
+ *
+ * Notice that further GPIO interrupts are disabled until the work is
+ * actually performed. This is to prevent overrun of the worker thread.
+ * Interrupts are re-enabled in sim_interrupt_work() when the work is
+ * completed.
+ */
+
+ if (work_available(&priv->work))
+ {
+ /* Schedule interrupt related work on the high priority worker thread. */
+
+ work_queue(HPWORK, &priv->work, sim_interrupt_work,
+ (FAR void *)priv, 0);
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sim_ioexpander_initialize
+ *
+ * Description:
+ * Instantiate and configure the I/O Expander device driver to use the provided
+ * I2C device instance.
+ *
+ * Input Parameters:
+ * i2c - An I2C driver instance
+ * minor - The device i2c address
+ * config - Persistent board configuration data
+ *
+ * Returned Value:
+ * an ioexpander_dev_s instance on success, NULL on failure.
+ *
+ ****************************************************************************/
+
+FAR struct ioexpander_dev_s *sim_ioexpander_initialize(void)
+{
+ FAR struct sim_dev_s *priv = &g_ioexpander;
+ int ret;
+
+ /* Initialize the device state structure */
+
+ priv->dev.ops = &g_sim_ops;
+
+ /* Initial interrupt state: Edge triggered on both edges */
+
+ priv->trigger = PINSET_ALL; /* All edge triggered */
+ priv->level[0] = PINSET_ALL; /* All rising edge */
+ priv->level[1] = PINSET_ALL; /* All falling edge */
+
+ /* Set up a timer to poll for simulated interrupts */
+
+ priv->wdog = wd_create();
+ DEBUGASSERT(priv->wdog != NULL);
+
+ ret = wd_start(priv->wdog, SIM_POLLDELAY, (wdentry_t)sim_interrupt,
+ 1, (wdparm_t)priv);
+ if (ret < 0)
+ {
+ gpioerr("ERROR: Failed to start poll timer\n");
+ }
+
+ return &priv->dev;
+}
+
+#endif /* CONFIG_SIM_IOEXPANDER */
diff --git a/arch/sim/src/up_oneshot.c b/arch/sim/src/up_oneshot.c
new file mode 100644
index 00000000000..7481e40017b
--- /dev/null
+++ b/arch/sim/src/up_oneshot.c
@@ -0,0 +1,322 @@
+/****************************************************************************
+ * arch/sim/src/up_oneshot.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct sim_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct sim_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ WDOG_ID wdog; /* Simulates oneshot timer */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void sim_oneshot_handler(int argc, wdparm_t arg1, ...);
+
+static int sim_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int sim_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int sim_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = sim_max_delay,
+ .start = sim_start,
+ .cancel = sim_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sim_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when sim_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sim_oneshot_handler(int argc, wdparm_t arg1, ...)
+{
+ FAR struct sim_oneshot_lowerhalf_s *priv =
+ (FAR struct sim_oneshot_lowerhalf_s *)arg1;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(argc == 1 && priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * sim_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: sim_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sim_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ DEBUGASSERT(lower != NULL && ts != NULL);
+
+ ts->tv_sec = INT_MAX;
+ ts->tv_nsec = 1000000000ul - 1;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sim_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sim_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct sim_oneshot_lowerhalf_s *priv =
+ (FAR struct sim_oneshot_lowerhalf_s *)lower;
+ systime_t ticks;
+ int64_t nsec;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Convert time to ticks */
+
+ nsec = (int64_t)ts->tv_sec * NSEC_PER_SEC +
+ (int64_t)ts->tv_nsec;
+ ticks = (systime_t)((nsec + NSEC_PER_TICK - 1) / NSEC_PER_TICK);
+
+ /* Save the callback information and start the timer */
+
+ priv->callback = callback;
+ priv->arg = arg;
+
+ return wd_start(priv->wdog, ticks, (wdentry_t)sim_oneshot_handler,
+ 1, (wdparm_t)priv);
+}
+
+/****************************************************************************
+ * Name: sim_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int sim_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sim_oneshot_lowerhalf_s *priv =
+ (FAR struct sim_oneshot_lowerhalf_s *)lower;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ ret = wd_cancel(priv->wdog);
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct sim_oneshot_lowerhalf_s *priv;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct sim_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct sim_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained watchdog timer */
+
+ priv->wdog = wd_create();
+ if (priv->wdog == NULL)
+ {
+ tmrerr("ERROR: Failed to create wdog\n");
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
\ No newline at end of file
diff --git a/arch/x86/include/i486/io.h b/arch/x86/include/i486/io.h
index 56471b5ab54..a6f455b79c3 100644
--- a/arch/x86/include/i486/io.h
+++ b/arch/x86/include/i486/io.h
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/x86/include/i486/io.h
- * arch/chip/io.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/z16/include/arch.h b/arch/z16/include/arch.h
index cb574663df1..350a94b4196 100644
--- a/arch/z16/include/arch.h
+++ b/arch/z16/include/arch.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arch.h
+ * arch/z16/include/arch/arch.h
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/arch.h
*/
-#ifndef __ARCH_ARCH_H
-#define __ARCH_ARCH_H
+#ifndef __ARCH_Z16_INCLUDE_ARCH_H
+#define __ARCH_Z16_INCLUDE_ARCH_H
/****************************************************************************
* Included Files
@@ -77,5 +77,5 @@ extern "C"
}
#endif
-#endif /* __ARCH_ARCH_H */
+#endif /* __ARCH_Z16_INCLUDE_ARCH_H */
diff --git a/arch/z16/include/irq.h b/arch/z16/include/irq.h
index 9aab0cc1331..5fcd165487f 100644
--- a/arch/z16/include/irq.h
+++ b/arch/z16/include/irq.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/irq.h
+ * arch/z16/include/irq.h
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_IRQ_H
-#define __ARCH_IRQ_H
+#ifndef __ARCH_Z16_INCLUDE_IRQ_H
+#define __ARCH_Z16_INCLUDE_IRQ_H
/****************************************************************************
* Included Files
@@ -78,5 +78,5 @@ extern "C"
#endif
#endif
-#endif /* __ARCH_IRQ_H */
+#endif /* __ARCH_Z16_INCLUDE_IRQ_H */
diff --git a/arch/z16/include/serial.h b/arch/z16/include/serial.h
index c1ce4aa1f18..ced8e9e596f 100644
--- a/arch/z16/include/serial.h
+++ b/arch/z16/include/serial.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/serial.h
+ * arch/z16/include/serial.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __ARCH_SERIAL_H
-#define __ARCH_SERIAL_H
+#ifndef __ARCH_Z16_INCLUDE_SERIAL_H
+#define __ARCH_Z16_INCLUDE_SERIAL_H
/****************************************************************************
* Included Files
@@ -52,4 +52,4 @@
* Public Functions
****************************************************************************/
-#endif /* __ARCH_SERIAL_H */
+#endif /* __ARCH_Z16_INCLUDE_SERIAL_H */
diff --git a/arch/z16/src/common/up_allocateheap.c b/arch/z16/src/common/up_allocateheap.c
index f307a8a73e2..948f770210a 100644
--- a/arch/z16/src/common/up_allocateheap.c
+++ b/arch/z16/src/common/up_allocateheap.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_allocateheap.c
+ * arch/z16/src/common/up_allocateheap.c
*
* Copyright (C) 2008, 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/z16/src/common/up_arch.h b/arch/z16/src/common/up_arch.h
index be1f77d67de..1b98ccc2aea 100644
--- a/arch/z16/src/common/up_arch.h
+++ b/arch/z16/src/common/up_arch.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * common/up_arch.h
+ * arch/z16/src/common/up_arch.h
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/z16/src/common/up_blocktask.c b/arch/z16/src/common/up_blocktask.c
index 584aec0ea83..8328086de62 100644
--- a/arch/z16/src/common/up_blocktask.c
+++ b/arch/z16/src/common/up_blocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_blocktask.c
+ * arch/z16/src/common/up_blocktask.c
*
* Copyright (C) 2008-2009, 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/z16/src/common/up_copystate.c b/arch/z16/src/common/up_copystate.c
index f9240c74450..8ef14c73947 100644
--- a/arch/z16/src/common/up_copystate.c
+++ b/arch/z16/src/common/up_copystate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_copystate.c
+ * arch/z16/src/common/up_copystate.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -43,18 +43,6 @@
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c
index d401f580f6b..fb4954fc618 100644
--- a/arch/z16/src/common/up_doirq.c
+++ b/arch/z16/src/common/up_doirq.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_doirq.c
+ * arch/z16/src/common/up_doirq.c
*
* Copyright (C) 2008-2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -49,22 +49,6 @@
#include "chip/chip.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/z16/src/common/up_exit.c b/arch/z16/src/common/up_exit.c
index a47e042b38c..0fbb210ea03 100644
--- a/arch/z16/src/common/up_exit.c
+++ b/arch/z16/src/common/up_exit.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_exit.c
+ * arch/z16/src/common/up_exit.c
*
* Copyright (C) 2008-2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/z16/src/common/up_idle.c b/arch/z16/src/common/up_idle.c
index 01aa0f8d6d8..58ddb4d455e 100644
--- a/arch/z16/src/common/up_idle.c
+++ b/arch/z16/src/common/up_idle.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * common/up_idle.c
+ * arch/z16/src/common/up_idle.c
*
* Copyright (C) 2008-2009, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt