Replace all ASSERT with DEBUGASSERT to save the code space

arch/arm/src/arm/up_blocktask.c

@@ -81,8 +81,8 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
-         (tcb->task_state <= LAST_READY_TO_RUN_STATE));
+              (tcb->task_state <= LAST_READY_TO_RUN_STATE));
 
   /* Remove the tcb task from the ready-to-run list.  If we
    * are blocking the task at the head of the task list (the

arch/arm/src/arm/up_sigdeliver.c

@@ -97,7 +97,7 @@ void up_sigdeliver(void)
 
   sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
-  ASSERT(rtcb->xcp.sigdeliver != NULL);
+  DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
 
   /* Save the real return state on the stack. */
 

arch/arm/src/arm/up_unblocktask.c

@@ -75,8 +75,8 @@ void up_unblock_task(struct tcb_s *tcb)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
-         (tcb->task_state <= LAST_BLOCKED_STATE));
+              (tcb->task_state <= LAST_BLOCKED_STATE));
 
   /* Remove the task from the blocked task list */
 

arch/arm/src/armv6-m/up_blocktask.c

@@ -79,8 +79,8 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
-         (tcb->task_state <= LAST_READY_TO_RUN_STATE));
+              (tcb->task_state <= LAST_READY_TO_RUN_STATE));
 
   /* Remove the tcb task from the ready-to-run list.  If we
    * are blocking the task at the head of the task list (the

arch/arm/src/armv6-m/up_sigdeliver.c

@@ -90,7 +90,7 @@ void up_sigdeliver(void)
 
   sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
-  ASSERT(rtcb->xcp.sigdeliver != NULL);
+  DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
 
   /* Save the real return state on the stack. */
 

arch/arm/src/armv6-m/up_unblocktask.c

@@ -73,8 +73,8 @@ void up_unblock_task(struct tcb_s *tcb)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
-         (tcb->task_state <= LAST_BLOCKED_STATE));
+              (tcb->task_state <= LAST_BLOCKED_STATE));
 
   /* Remove the task from the blocked task list */
 

arch/arm/src/armv7-a/arm_blocktask.c

@@ -94,8 +94,8 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
-         (tcb->task_state <= LAST_READY_TO_RUN_STATE));
+              (tcb->task_state <= LAST_READY_TO_RUN_STATE));
 
   /* Remove the tcb task from the ready-to-run list.  If we
    * are blocking the task at the head of the task list (the

arch/arm/src/armv7-a/arm_doirq.c

@@ -216,8 +216,8 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
        * multiple pending SGI interrupts.
        */
 
-      ASSERT((unsigned int)irq <= GIC_IRQ_SGI15 &&
+      DEBUGASSERT((unsigned int)irq <= GIC_IRQ_SGI15 &&
-             (g_sgi_pending[cpu] & bit) == 0);
+                  (g_sgi_pending[cpu] & bit) == 0);
 
       /* Mare the SGI as pending and return immediately */
 

arch/arm/src/armv7-a/arm_sigdeliver.c

@@ -94,7 +94,7 @@ void up_sigdeliver(void)
 
   sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
-  ASSERT(rtcb->xcp.sigdeliver != NULL);
+  DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
 
   /* Save the real return state on the stack. */
 

arch/arm/src/armv7-a/arm_unblocktask.c

@@ -88,8 +88,8 @@ void up_unblock_task(struct tcb_s *tcb)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
-         (tcb->task_state <= LAST_BLOCKED_STATE));
+              (tcb->task_state <= LAST_BLOCKED_STATE));
 
   /* Remove the task from the blocked task list */
 

arch/arm/src/armv7-m/up_blocktask.c

@@ -80,8 +80,8 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
-         (tcb->task_state <= LAST_READY_TO_RUN_STATE));
+              (tcb->task_state <= LAST_READY_TO_RUN_STATE));
 
   /* Remove the tcb task from the ready-to-run list.  If we
    * are blocking the task at the head of the task list (the

arch/arm/src/armv7-m/up_sigdeliver.c

@@ -95,7 +95,7 @@ void up_sigdeliver(void)
 
   sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
-  ASSERT(rtcb->xcp.sigdeliver != NULL);
+  DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
 
   /* Save the real return state on the stack. */
 

arch/arm/src/armv7-m/up_unblocktask.c

@@ -74,8 +74,8 @@ void up_unblock_task(struct tcb_s *tcb)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
-         (tcb->task_state <= LAST_BLOCKED_STATE));
+              (tcb->task_state <= LAST_BLOCKED_STATE));
 
   /* Remove the task from the blocked task list */
 

arch/arm/src/armv7-r/arm_blocktask.c

@@ -81,8 +81,8 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
-         (tcb->task_state <= LAST_READY_TO_RUN_STATE));
+              (tcb->task_state <= LAST_READY_TO_RUN_STATE));
 
   /* Remove the tcb task from the ready-to-run list.  If we
    * are blocking the task at the head of the task list (the

arch/arm/src/armv7-r/arm_sigdeliver.c

@@ -85,7 +85,7 @@ void up_sigdeliver(void)
 
   sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
-  ASSERT(rtcb->xcp.sigdeliver != NULL);
+  DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
 
   /* Save the real return state on the stack. */
 

arch/arm/src/armv7-r/arm_unblocktask.c

@@ -87,8 +87,8 @@ void up_unblock_task(struct tcb_s *tcb)
 
   /* Verify that the context switch can be performed */
 
-  ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
+  DEBUGASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) &&
-         (tcb->task_state <= LAST_BLOCKED_STATE));
+              (tcb->task_state <= LAST_BLOCKED_STATE));
 
   /* Remove the task from the blocked task list */
 

arch/arm/src/efm32/efm32_i2c.c

@@ -1604,11 +1604,11 @@ int efm32_i2c_reset(FAR struct i2c_master_s *dev)
   uint32_t sda_gpio;
   int ret = ERROR;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Our caller must own a ref */
 
-  ASSERT(priv->refs > 0);
+  DEBUGASSERT(priv->refs > 0);
 
   /* Lock out other clients */
 
@@ -1765,7 +1765,7 @@ int efm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
   FAR struct efm32_i2c_priv_s *priv = (struct efm32_i2c_priv_s *)dev;
   irqstate_t flags;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement reference count and check for underflow */
 

arch/arm/src/efm32/efm32_pwm.c

@@ -405,7 +405,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
       break;
 
     default:
-      ASSERT(false);
+      DEBUGASSERT(false);
     }
 
   pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval);
@@ -625,7 +625,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
       break;
 
     default:
-      ASSERT(false);
+      DEBUGASSERT(false);
       break;
     }
 

arch/arm/src/imxrt/imxrt_enet.c

@@ -523,7 +523,7 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
     }
   else
     {
-       ASSERT(txdesc->data == buf);
+       DEBUGASSERT(txdesc->data == buf);
     }
 
   /* Start the TX transfer (if it was not already waiting for buffers) */

arch/arm/src/kinetis/kinetis_enet.c

@@ -494,7 +494,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
     }
   else
     {
-       ASSERT(txdesc->data == buf);
+       DEBUGASSERT(txdesc->data == buf);
     }
 
   /* Start the TX transfer (if it was not already waiting for buffers) */

arch/arm/src/lc823450/lc823450_clockconfig.c

@@ -168,7 +168,7 @@ void lc823450_clockconfig()
     }
   else
     {
-      ASSERT(false);
+      DEBUGASSERT(false);
     }
 #endif
 

arch/arm/src/lc823450/lc823450_i2c.c

@@ -1107,7 +1107,7 @@ FAR struct i2c_master_s *lc823450_i2cbus_initialize(int port)
         break;
 #endif
     default:
-      ASSERT(false);
+      DEBUGASSERT(false);
       return NULL;
     }
 
@@ -1144,7 +1144,7 @@ int lc823450_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
   irqstate_t flags;
   int port = -1;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement refs and check for underflow */
 

arch/arm/src/lc823450/lc823450_i2s.c

@@ -271,7 +271,7 @@ extern unsigned int XT1OSC_CLK;
 
 static void _setup_audio_pll(uint32_t freq)
 {
-  ASSERT(24000000 == XT1OSC_CLK);
+  DEBUGASSERT(24000000 == XT1OSC_CLK);
 
   uint32_t m;
   uint32_t n;
@@ -289,7 +289,7 @@ static void _setup_audio_pll(uint32_t freq)
         break;
 
       default:
-        ASSERT(false);
+        DEBUGASSERT(false);
     }
 
   /* Set divider */
@@ -396,7 +396,7 @@ static void lc823450_i2s_setchannel(char id, uint8_t ch)
         break;
 
       default:
-        ASSERT(false);
+        DEBUGASSERT(false);
         break;
     }
 
@@ -441,7 +441,7 @@ static int lc823450_i2s_ioctl(struct i2s_dev_s *dev, int cmd, unsigned long arg)
     {
       case AUDIOIOC_CONFIGURE:
         cap_desc = (FAR const struct audio_caps_desc_s *)((uintptr_t)arg);
-        ASSERT(NULL != cap_desc);
+        DEBUGASSERT(NULL != cap_desc);
 
         tx_th   = cap_desc->caps.ac_controls.w >> 24;
         rate[1] = cap_desc->caps.ac_controls.w & 0xfffff;
@@ -663,7 +663,7 @@ static int lc823450_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
   uint32_t bufc_enabled;
   uint32_t decsel;
 
-  ASSERT(0 < n);
+  DEBUGASSERT(0 < n);
 
   decsel = getreg32(AUDSEL) & AUDSEL_DECSEL;
 

arch/arm/src/lc823450/lc823450_irq.c

@@ -736,7 +736,7 @@ void up_ack_irq(int irq)
     {
       /* IRQ should be handled on CPU0 */
 
-      ASSERT(false);
+      DEBUGASSERT(false);
     }
 #endif
 

arch/arm/src/lc823450/lc823450_mtd.c

@@ -655,9 +655,9 @@ int lc823450_mtd_initialize(uint32_t devno)
 #ifdef CONFIG_DEBUG
   for (i = 0; i < LC823450_NPARTS - 1; i++)
     {
-      ASSERT(partinfo[i].startblock < partinfo[i + 1].startblock);
+      DEBUGASSERT(partinfo[i].startblock < partinfo[i + 1].startblock);
-      ASSERT(partinfo[i].startblock + partinfo[i].nblocks <= maxblock);
+      DEBUGASSERT(partinfo[i].startblock + partinfo[i].nblocks <= maxblock);
-      ASSERT(partinfo[i + 1].startblock + partinfo[i + 1].nblocks <= maxblock);
+      DEBUGASSERT(partinfo[i + 1].startblock + partinfo[i + 1].nblocks <= maxblock);
     }
 #endif
 

arch/arm/src/lc823450/lc823450_sdc.c

@@ -241,7 +241,7 @@ int lc823450_sdc_initialize(uint32_t ch)
 
   /* Only ES2 is supported */
 
-  ASSERT(1 == cpu_ver);
+  DEBUGASSERT(1 == cpu_ver);
 
   struct SdDrCfg_s *psd = _cfg[ch];
 
@@ -280,7 +280,7 @@ int lc823450_sdc_initialize(uint32_t ch)
 #endif
 
       default:
-        ASSERT(false);
+        DEBUGASSERT(false);
     }
 
   mcinfo("++++ start \n");

arch/arm/src/lc823450/lc823450_sddrv_dep.c

@@ -110,7 +110,7 @@ static int _get_ch_from_cfg(struct SdDrCfg_s *cfg)
         break;
 
       default:
-        ASSERT(false);
+        DEBUGASSERT(false);
     }
 
   return ch;

arch/arm/src/lc823450/lc823450_syscontrol.c

@@ -146,7 +146,7 @@ void up_enable_clk(enum clock_e clk)
   irqstate_t flags;
   flags = spin_lock_irqsave();
 
-  ASSERT(clk < LC823450_CLOCK_NUM);
+  DEBUGASSERT(clk < LC823450_CLOCK_NUM);
 
   if (lc823450_clocks[clk].count++ == 0)
     {
@@ -166,7 +166,7 @@ void up_disable_clk(enum clock_e clk)
   irqstate_t flags;
   flags = spin_lock_irqsave();
 
-  ASSERT(clk < LC823450_CLOCK_NUM);
+  DEBUGASSERT(clk < LC823450_CLOCK_NUM);
 
   if (--lc823450_clocks[clk].count == 0)
     {
@@ -174,7 +174,7 @@ void up_disable_clk(enum clock_e clk)
                   lc823450_clocks[clk].regmask, 0);
     }
 
-  /*  ASSERT(lc823450_clocks[clk].count >= 0); */
+  /*  DEBUGASSERT(lc823450_clocks[clk].count >= 0); */
 
   if (lc823450_clocks[clk].count < 0)
     {

arch/arm/src/lc823450/lc823450_timer.c

@@ -355,7 +355,7 @@ int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
     {
       if (profile_ptr != CONFIG_PROFILE_SAMPLES)
         {
-          ASSERT(current_regs);
+          DEBUGASSERT(current_regs);
           profile_data[profile_ptr++] = current_regs[REG_R15];
         }
       else

arch/arm/src/lpc43xx/lpc43_timer.c

@@ -752,7 +752,7 @@ void lpc43_tmrinitialize(FAR const char *devpath, int irq)
 #endif
 
     default:
-      ASSERT(0);
+      DEBUGASSERT(0);
     }
 
   priv->ops = &g_tmrops;

arch/arm/src/sam34/sam_tc.c

@@ -642,7 +642,7 @@ void sam_tcinitialize(FAR const char *devpath, int irq)
 #endif
 
     default:
-      ASSERT(0);
+      DEBUGASSERT(0);
     }
 
   priv->ops = &g_tcops;

arch/arm/src/sam34/sam_wdt.c

@@ -570,7 +570,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
   return oldhandler;
 
 #endif
-  ASSERT(0);
+  DEBUGASSERT(0);
   return NULL;
 }
 

arch/arm/src/sama5/sam_adc.c

@@ -610,7 +610,7 @@ static void sam_adc_dmadone(void *arg)
   int i;
 
   ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
-  ASSERT(priv != NULL && !priv->ready);
+  DEBUGASSERT(priv != NULL && !priv->ready);
 
   /* If the DMA transfer is not enabled, just ignore the data (and do not start
    * the next DMA transfer).
@@ -853,7 +853,7 @@ static void sam_adc_endconversion(void *arg)
   uint32_t pending;
   int chan;
 
-  ASSERT(priv != NULL);
+  DEBUGASSERT(priv != NULL);
   ainfo("pending=%08x\n", priv->pending);
 
   /* Get the set of unmasked, pending ADC interrupts */

arch/arm/src/sama5/sam_ssc.c

@@ -970,7 +970,7 @@ static struct sam_buffer_s *ssc_buf_allocate(struct sam_ssc_s *priv)
 
   flags = enter_critical_section();
   bfcontainer = priv->freelist;
-  ASSERT(bfcontainer);
+  DEBUGASSERT(bfcontainer);
 
   /* Unlink the buffer from the freelist */
 

arch/arm/src/sama5/sam_tsd.c

@@ -522,7 +522,7 @@ static void sam_tsd_bottomhalf(void *arg)
   uint32_t p;
   bool pendown;
 
-  ASSERT(priv != NULL);
+  DEBUGASSERT(priv != NULL);
 
   /* Get the set of pending ADC interrupts and pen status */
 

arch/arm/src/sama5/sam_twi.c

@@ -873,7 +873,7 @@ static int twi_reset(FAR struct i2c_master_s *dev)
   uint32_t sdapin;
   int ret;
 
-  ASSERT(priv);
+  DEBUGASSERT(priv);
 
   /* Get exclusive access to the TWI device */
 

arch/arm/src/samd2l2/sam_i2c_master.c

@@ -1404,7 +1404,7 @@ int sam_i2c_reset(FAR struct i2c_master_s *dev)
   struct sam_i2c_dev_s *priv = (struct sam_i2c_dev_s *)dev;
   int ret;
 
-  ASSERT(priv);
+  DEBUGASSERT(priv);
 
   /* Get exclusive access to the I2C device */
 

arch/arm/src/samd5e5/sam_i2c_master.c

@@ -1455,7 +1455,7 @@ int sam_i2c_reset(FAR struct i2c_master_s *dev)
   struct sam_i2c_dev_s *priv = (struct sam_i2c_dev_s *)dev;
   int ret;
 
-  ASSERT(priv);
+  DEBUGASSERT(priv);
 
   /* Get exclusive access to the I2C device */
 

arch/arm/src/samv7/sam_ssc.c

@@ -944,7 +944,7 @@ static struct sam_buffer_s *ssc_buf_allocate(struct sam_ssc_s *priv)
 
   flags = enter_critical_section();
   bfcontainer = priv->freelist;
-  ASSERT(bfcontainer);
+  DEBUGASSERT(bfcontainer);
 
   /* Unlink the buffer from the freelist */
 

arch/arm/src/stm32/stm32_dma2d.c

@@ -409,7 +409,7 @@ static int stm32_dma2dirq(int irq, void *context, FAR void *arg)
     {
       /* Unknown irq, should not occur */
 
-      ASSERT("Unknown interrupt error\n");
+      DEBUGASSERT("Unknown interrupt error\n");
     }
 
   /* Unlock the semaphore if locked */

arch/arm/src/stm32/stm32_i2c.c

@@ -1801,11 +1801,11 @@ static int stm32_i2c_reset(FAR struct i2c_master_s *dev)
   uint32_t frequency;
   int ret = ERROR;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Our caller must own a ref */
 
-  ASSERT(priv->refs > 0);
+  DEBUGASSERT(priv->refs > 0);
 
   /* Lock out other clients */
 
@@ -1986,7 +1986,7 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
   FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
   irqstate_t flags;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement reference count and check for underflow */
 

arch/arm/src/stm32/stm32_i2c_alt.c

@@ -2266,11 +2266,11 @@ static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
   uint32_t frequency;
   int ret = ERROR;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Our caller must own a ref */
 
-  ASSERT(priv->refs > 0);
+  DEBUGASSERT(priv->refs > 0);
 
   /* Lock out other clients */
 
@@ -2448,7 +2448,7 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
   FAR struct stm32_i2c_priv_s *priv = (FAR struct stm32_i2c_priv_s *)dev;
   irqstate_t flags;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement reference count and check for underflow */
 

arch/arm/src/stm32/stm32_i2s.c

@@ -710,7 +710,7 @@ static struct stm32_buffer_s *i2s_buf_allocate(struct stm32_i2s_s *priv)
 
   flags = enter_critical_section();
   bfcontainer = priv->freelist;
-  ASSERT(bfcontainer);
+  DEBUGASSERT(bfcontainer);
 
   /* Unlink the buffer from the freelist */
 

arch/arm/src/stm32/stm32_ltdc.c

@@ -1524,7 +1524,7 @@ static int stm32_ltdcirq(int irq, void *context, FAR void *arg)
     }
   else
     {
-      ASSERT("Unknown interrupt");
+      DEBUGASSERT("Unknown interrupt");
     }
 
   /* Unlock the semaphore if locked */

arch/arm/src/stm32/stm32_tickless.c

@@ -447,7 +447,7 @@ void arm_timer_initialize(void)
 
         /* Basic timers not supported by this implementation */
 
-        ASSERT(0);
+        DEBUGASSERT(0);
         break;
 #endif
 
@@ -456,7 +456,7 @@ void arm_timer_initialize(void)
 
         /* Basic timers not supported by this implementation */
 
-        ASSERT(0);
+        DEBUGASSERT(0);
         break;
 #endif
 
@@ -517,7 +517,7 @@ void arm_timer_initialize(void)
 #endif
 
       default:
-        ASSERT(0);
+        DEBUGASSERT(0);
     }
 
   /* Get the TC frequency that corresponds to the requested resolution */
@@ -535,7 +535,7 @@ void arm_timer_initialize(void)
   if (!g_tickless.tch)
     {
       tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer);
-      ASSERT(0);
+      DEBUGASSERT(0);
     }
 
   STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency);

arch/arm/src/stm32/stm32f30xxx_i2c.c

@@ -1804,11 +1804,11 @@ static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
   uint32_t frequency;
   int ret = ERROR;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Our caller must own a ref */
 
-  ASSERT(priv->refs > 0);
+  DEBUGASSERT(priv->refs > 0);
 
   /* Lock out other clients */
 
@@ -1986,7 +1986,7 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
   FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
   irqstate_t flags;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement refs and check for underflow */
 

arch/arm/src/stm32f0/stm32f0_i2c.c

@@ -1779,11 +1779,11 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev)
   uint32_t frequency;
   int ret = -EIO;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Our caller must own a ref */
 
-  ASSERT(priv->refs > 0);
+  DEBUGASSERT(priv->refs > 0);
 
   /* Lock out other clients */
 
@@ -1969,7 +1969,7 @@ int stm32f0_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
   FAR struct stm32f0_i2c_priv_s *priv = (struct stm32f0_i2c_priv_s *)dev;
   irqstate_t flags;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement refs and check for underflow */
 

arch/arm/src/stm32f7/stm32_dma2d.c

@@ -410,7 +410,7 @@ static int stm32_dma2dirq(int irq, void *context, FAR void *arg)
     {
       /* Unknown irq, should not occur */
 
-      ASSERT("Unknown interrupt error\n");
+      DEBUGASSERT("Unknown interrupt error\n");
     }
 
   /* Unlock the semaphore if locked */

arch/arm/src/stm32f7/stm32_i2c.c

@@ -2554,7 +2554,7 @@ static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
   uint32_t frequency;
   int ret = ERROR;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Get I2C private structure */
 
@@ -2562,7 +2562,7 @@ static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
 
   /* Our caller must own a ref */
 
-  ASSERT(priv->refs > 0);
+  DEBUGASSERT(priv->refs > 0);
 
   /* Lock out other clients */
 
@@ -2837,7 +2837,7 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
 {
   irqstate_t irqs;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev);
 
   /* Decrement refs and check for underflow */
 

arch/arm/src/stm32f7/stm32_ltdc.c

@@ -1526,7 +1526,7 @@ static int stm32_ltdcirq(int irq, void *context, FAR void *arg)
     }
   else
     {
-      ASSERT("Unknown interrupt");
+      DEBUGASSERT("Unknown interrupt");
     }
 
   /* Unlock the semaphore if locked */