diff --git a/configs/lpc4330-xplorer/README.txt b/configs/lpc4330-xplorer/README.txt index d1fcd7fb9ea..701ecad97a0 100644 --- a/configs/lpc4330-xplorer/README.txt +++ b/configs/lpc4330-xplorer/README.txt @@ -406,6 +406,21 @@ LPC4330-Xplorer Configuration Options CONFIG_ARCH_FPU - The LPC43xxx supports a floating point unit (FPU) CONFIG_ARCH_FPU=y + + CONFIG_BOOT_xxx - The startup code needs to know if the code is running + from internal FLASH, external FLASH, SPIFI, or SRAM in order to + initialize properly. Note that a boot device is not specified for + cases where the code is copied into SRAM; those cases are all covered + by CONFIG_BOOT_SRAM. + + CONFIG_BOOT_SRAM=y : Running from SRAM (0x1000:0000) + CONFIG_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000) + CONFIG_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000) + CONFIG_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000) + CONFIG_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000) + CONFIG_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000) + CONFIG_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000) + CONFIG_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000) CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs diff --git a/configs/lpc4330-xplorer/include/board.h b/configs/lpc4330-xplorer/include/board.h index 6a3f36158ba..1c2f42b2c7b 100644 --- a/configs/lpc4330-xplorer/include/board.h +++ b/configs/lpc4330-xplorer/include/board.h @@ -53,14 +53,40 @@ ****************************************************************************/ /* Clocking ****************************************************************/ -/* NOTE: The following definitions require lpc43_syscon.h. It is not included here - * because the including C file may not have that file in its include path. +/* NOTE: The following definitions require lpc43_cgu.h. It is not included + * here because the including C file may not have that file in its include + * path. + * + * The Xplorer board has four crystals on board: + * + * Y1 - RTC 32.768 MHz oscillator input, + * Y2 - 24.576 MHz input to the UDA 1380 audio codec, + * Y3 - 12.000 MHz LPC43xx crystal oscillator input + * Y4 - 50 MHz input for Ethernet */ -#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ -#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ -#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ -#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency (Y3) */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency (Y1) */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ + +/* Integer and direct modes are supported: + * + * In integer mode: + * Fclkin = BOARD_XTAL_FREQUENCY + * Fclkout = Msel * FClkin / Nsel + * Fcco = 2 * Psel * Nclkout + * In direct mode: + * Fclkin = BOARD_XTAL_FREQUENCY + * Fclkout = Msel * FClkin / Nsel + * Fcco = Fclkout + */ + +#undef BOARD_PLL1_DIRECT /* Integer mode */ +#define BOARD_PLL_MSEL (6) /* Msel = 6 */ +#define BOARD_PLL_NSEL (1) /* Nsel = 1 */ +#define BOARD_PLL_PSEL (2) /* Psel = 2 */ +#define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */ +#define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * 72,000,000 */ /* This is the clock setup we configure for: * @@ -69,64 +95,7 @@ * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define LPC43_CCLK 80000000 /* 80Mhz*/ - -/* Select the main oscillator as the frequency source. SYSCLK is then the frequency - * of the main oscillator. - */ - -#undef CONFIG_LPC43_MAINOSC -#define CONFIG_LPC43_MAINOSC 1 -#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN - -/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. - * The input to the divider (PLLCLK) will be determined by the PLL output. - */ - -#define BOARD_CCLKCFG_DIVIDER 6 -#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) - -/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). - * - * Source clock: Main oscillator - * PLL0 Multiplier value (M): 20 - * PLL0 Pre-divider value (N): 1 - * - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz - */ - -#undef CONFIG_LPC43_PLL0 -#define CONFIG_LPC43_PLL0 1 -#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN - -#define BOARD_PLL0CFG_MSEL 20 -#define BOARD_PLL0CFG_NSEL 1 -#define BOARD_PLL0CFG_VALUE \ - (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ - ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) - -/* PLL1 -- Not used. */ - -#undef CONFIG_LPC43_PLL1 -#define BOARD_PLL1CFG_MSEL 36 -#define BOARD_PLL1CFG_NSEL 1 -#define BOARD_PLL1CFG_VALUE \ - (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ - ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) - -/* USB divider. This divider is used when PLL1 is not enabled to get the - * USB clock from PLL0: - * - * USBCLK = PLL0CLK / 10 = 48MHz - */ - -#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10 - -/* FLASH Configuration */ - -#undef CONFIG_LP17_FLASH -#define CONFIG_LP17_FLASH 1 -#define BOARD_FLASHCFG_VALUE 0x0000303a +#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY /* LED definitions *********************************************************/ /* The LPC4330-Xplorer has 2 user-controllable LEDs labeled D2 an D3 in the diff --git a/configs/lpc4330-xplorer/ostest/Make.defs b/configs/lpc4330-xplorer/ostest/Make.defs index f5746db136f..1e8427c1caf 100644 --- a/configs/lpc4330-xplorer/ostest/Make.defs +++ b/configs/lpc4330-xplorer/ostest/Make.defs @@ -87,6 +87,26 @@ ifeq ($(CONFIG_LPC43_BUILDROOT),y) MAXOPTIMIZATION = -Os endif +# Setup for the kind of memory that we are executing from + +ifeq ($(CONFIG_BOOT_SRAM),y) + LDSCRIPT = ramconfig.ld +endif +ifeq ($(CONFIG_BOOT_SPIFI),y) + LDSCRIPT = spiconfig.ld +endif +ifeq ($(CONFIG_BOOT_FLASHA),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_BOOT_FLASHB),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_BOOT_CS0FLASH),y) + LDSCRIPT = cs0flash.ld +endif + +# Setup for Windows vs Linux/Cygwin/OSX environments + ifeq ($(WINTOOL),y) # Windows-native toolchains DIRLINK = $(TOPDIR)/tools/winlink.sh @@ -94,14 +114,14 @@ ifeq ($(WINTOOL),y) MKDEP = $(TOPDIR)/tools/mknulldeps.sh ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ramconfig.ld}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" MAXOPTIMIZATION = -O2 else # Linux/Cygwin-native toolchain MKDEP = $(TOPDIR)/tools/mkdeps.sh ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ramconfig.ld + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) endif CC = $(CROSSDEV)gcc diff --git a/configs/lpc4330-xplorer/ostest/defconfig b/configs/lpc4330-xplorer/ostest/defconfig index bd894902d96..848c43eac0a 100644 --- a/configs/lpc4330-xplorer/ostest/defconfig +++ b/configs/lpc4330-xplorer/ostest/defconfig @@ -96,6 +96,31 @@ CONFIG_ARCH_CALIBRATION=n CONFIG_ARCH_DMA=n CONFIG_ARMV7M_CMNVECTOR=y +# +# CONFIG_BOOT_xxx - The startup code needs to know if the code is running +# from internal FLASH, external FLASH, SPIFI, or SRAM in order to +# initialize properly. Note that a boot device is not specified for +# cases where the code is copied into SRAM; those cases are all covered +# by CONFIG_BOOT_SRAM. +# +# CONFIG_BOOT_SRAM=y : Running from SRAM (0x1000:0000) +# CONFIG_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000) +# CONFIG_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000) +# CONFIG_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000) +# CONFIG_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000) +# CONFIG_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000) +# CONFIG_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000) +# CONFIG_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000) +# +CONFIG_BOOT_SRAM=y +CONFIG_BOOT_SPIFI=n +CONFIG_BOOT_FLASHA=n +CONFIG_BOOT_FLASHB=n +CONFIG_BOOT_CS0FLASH=n +CONFIG_BOOT_CS1FLASH=n +CONFIG_BOOT_CS2FLASH=n +CONFIG_BOOT_CS3FLASH=n + # # Identify toolchain and linker options # diff --git a/configs/lpc4330-xplorer/scripts/ramconfig.ld b/configs/lpc4330-xplorer/scripts/ramconfig.ld index 4e4abca8a11..f44d6181e29 100644 --- a/configs/lpc4330-xplorer/scripts/ramconfig.ld +++ b/configs/lpc4330-xplorer/scripts/ramconfig.ld @@ -32,6 +32,27 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000 0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000 0000. The default, + * reset value of the shadow pointer is 0x1040 0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000 0000, sets the ARM's shadow + * pointer to 0x1000 0000, and jumps to that location. + * + * However, using JTAG the executable image can be also loaded directly into + * and executed from SRAM. + */ /* The LPC4330 on the LPC4330-Xplorer has the following memory resources: * @@ -41,6 +62,7 @@ * b. 72KB beginning at address 0x1008:0000 and * c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000, * 0x2000:8000 and 0x2000:C000. + * 3. No internal FLASH * * Here we assume that: * diff --git a/configs/lpc4330-xplorer/scripts/spificonfig.ld b/configs/lpc4330-xplorer/scripts/spificonfig.ld index 6aa7c2657d8..7bbb3d2957c 100644 --- a/configs/lpc4330-xplorer/scripts/spificonfig.ld +++ b/configs/lpc4330-xplorer/scripts/spificonfig.ld @@ -32,6 +32,27 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000 0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000 0000. The default, + * reset value of the shadow pointer is 0x1040 0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000 0000, sets the ARM's shadow + * pointer to 0x1000 0000, and jumps to that location. + * + * Of course, using JTAG the executable image can be also loaded directly + * into and executed from SRAM. + */ /* The LPC4330 on the LPC4330-Xplorer has the following memory resources: * @@ -41,6 +62,7 @@ * b. 72KB beginning at address 0x1008:0000 and * c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000, * 0x2000:8000 and 0x2000:C000. + * 3. No internal FLASH * * Here we assume that: *