diff --git a/arch/arm/include/armv6-m/irq.h b/arch/arm/include/armv6-m/irq.h
index 45ce521fcdb..9d23cc15271 100644
--- a/arch/arm/include/armv6-m/irq.h
+++ b/arch/arm/include/armv6-m/irq.h
@@ -131,6 +131,12 @@
 
 #define REG_PIC             REG_R10
 
+/* CONTROL register */
+
+#define CONTROL_FPCA        (1 << 2) /* Bit 2: Floating-point context active */
+#define CONTROL_SPSEL       (1 << 1) /* Bit 1: Stack-pointer select */
+#define CONTROL_NPRIV       (1 << 0) /* Bit 0: Not privileged */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h
index 7cca75bb3e3..3ba7c7308a8 100644
--- a/arch/arm/include/armv7-m/irq.h
+++ b/arch/arm/include/armv7-m/irq.h
@@ -87,6 +87,12 @@
 
 #define REG_PIC             REG_R10
 
+/* CONTROL register */
+
+#define CONTROL_FPCA        (1 << 2) /* Bit 2: Floating-point context active */
+#define CONTROL_SPSEL       (1 << 1) /* Bit 1: Stack-pointer select */
+#define CONTROL_NPRIV       (1 << 0) /* Bit 0: Not privileged */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
diff --git a/arch/arm/include/armv8-m/irq.h b/arch/arm/include/armv8-m/irq.h
index df03f7a1de4..8898f30ef39 100644
--- a/arch/arm/include/armv8-m/irq.h
+++ b/arch/arm/include/armv8-m/irq.h
@@ -87,6 +87,17 @@
 
 #define REG_PIC             REG_R10
 
+/* CONTROL register */
+
+#define CONTROL_UPAC_EN     (1 << 7) /* Bit 7: Unprivileged pointer authentication enable */
+#define CONTROL_PAC_EN      (1 << 6) /* Bit 6: Privileged pointer authentication enable */
+#define CONTROL_UBTI_EN     (1 << 5) /* Bit 5: Unprivileged branch target identification enable */
+#define CONTROL_BTI_EN      (1 << 4) /* Bit 4: Privileged branch target identification enable */
+#define CONTROL_SFPA        (1 << 3) /* Bit 3: Secure Floating-point active */
+#define CONTROL_FPCA        (1 << 2) /* Bit 2: Floating-point context active */
+#define CONTROL_SPSEL       (1 << 1) /* Bit 1: Stack-pointer select */
+#define CONTROL_NPRIV       (1 << 0) /* Bit 0: Not privileged */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c
index b66f2dafe6f..3ac0b136136 100644
--- a/arch/arm/src/cxd56xx/cxd56_start.c
+++ b/arch/arm/src/cxd56xx/cxd56_start.c
@@ -147,7 +147,7 @@ void fpuconfig(void)
    */
 
   regval  = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -177,7 +177,7 @@ void fpuconfig(void)
    */
 
   regval  = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index f65fbd7f02c..1accb748597 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -139,7 +139,7 @@ static inline void efm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -169,7 +169,7 @@ static inline void efm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/eoss3/eoss3_start.c b/arch/arm/src/eoss3/eoss3_start.c
index 57a3a83aac7..cc7fecb1f8b 100644
--- a/arch/arm/src/eoss3/eoss3_start.c
+++ b/arch/arm/src/eoss3/eoss3_start.c
@@ -137,7 +137,7 @@ static inline void eoss3_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -167,7 +167,7 @@ static inline void eoss3_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c
index 681910d7761..8dc93e796f2 100644
--- a/arch/arm/src/imxrt/imxrt_start.c
+++ b/arch/arm/src/imxrt/imxrt_start.c
@@ -121,7 +121,7 @@ static inline void imxrt_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -151,7 +151,7 @@ static inline void imxrt_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index 13ea9f17538..5ee6c7f4a1f 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -133,7 +133,7 @@ static inline void kinetis_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -163,7 +163,7 @@ static inline void kinetis_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
index eeef875f147..c0599b4b06c 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
@@ -122,7 +122,7 @@ static inline void lpc17_40_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -152,7 +152,7 @@ static inline void lpc17_40_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c
index 06616a8b778..12dddcb9271 100644
--- a/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/arch/arm/src/lpc43xx/lpc43_start.c
@@ -190,7 +190,7 @@ static inline void lpc43_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -220,7 +220,7 @@ static inline void lpc43_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/lpc54xx/lpc54_start.c b/arch/arm/src/lpc54xx/lpc54_start.c
index ae659a41a75..ed4c7d85415 100644
--- a/arch/arm/src/lpc54xx/lpc54_start.c
+++ b/arch/arm/src/lpc54xx/lpc54_start.c
@@ -120,7 +120,7 @@ static inline void lpc54_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -148,7 +148,7 @@ static inline void lpc54_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/max326xx/common/max326_start.c b/arch/arm/src/max326xx/common/max326_start.c
index db36b6dd96b..6533fc5844a 100644
--- a/arch/arm/src/max326xx/common/max326_start.c
+++ b/arch/arm/src/max326xx/common/max326_start.c
@@ -120,7 +120,7 @@ static inline void max326_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -148,7 +148,7 @@ static inline void max326_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c
index 58edc37aef4..ae8dc168a8f 100644
--- a/arch/arm/src/nrf52/nrf52_start.c
+++ b/arch/arm/src/nrf52/nrf52_start.c
@@ -107,7 +107,7 @@ static inline void nrf52_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -135,7 +135,7 @@ static inline void nrf52_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c
index 14e90c95a81..fb10c1b5d93 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_start.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_start.c
@@ -160,7 +160,7 @@ static inline void s32k1xx_fpu_config(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -188,7 +188,7 @@ static inline void s32k1xx_fpu_config(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c
index c251498f012..00742626b79 100644
--- a/arch/arm/src/sam34/sam_start.c
+++ b/arch/arm/src/sam34/sam_start.c
@@ -135,7 +135,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -165,7 +165,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/samd5e5/sam_start.c b/arch/arm/src/samd5e5/sam_start.c
index 5dc64767dbb..6844378405c 100644
--- a/arch/arm/src/samd5e5/sam_start.c
+++ b/arch/arm/src/samd5e5/sam_start.c
@@ -137,7 +137,7 @@ static inline void sam_fpu_configure(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -167,7 +167,7 @@ static inline void sam_fpu_configure(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c
index f20eb01f7f6..8541e230a3c 100644
--- a/arch/arm/src/samv7/sam_start.c
+++ b/arch/arm/src/samv7/sam_start.c
@@ -132,7 +132,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -162,7 +162,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index 38c0330aa5f..78ff941d7f3 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -138,7 +138,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -168,7 +168,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c
index f5753f1b84c..4f06731367d 100644
--- a/arch/arm/src/stm32f7/stm32_start.c
+++ b/arch/arm/src/stm32f7/stm32_start.c
@@ -132,7 +132,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -162,7 +162,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c
index 9da6a4dfa09..0f7b7623599 100644
--- a/arch/arm/src/stm32h7/stm32_start.c
+++ b/arch/arm/src/stm32h7/stm32_start.c
@@ -147,7 +147,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -177,7 +177,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c
index eacb5bd4c5c..cfec8507d6e 100644
--- a/arch/arm/src/stm32l4/stm32l4_start.c
+++ b/arch/arm/src/stm32l4/stm32l4_start.c
@@ -147,7 +147,7 @@ static inline void stm32l4_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -177,7 +177,7 @@ static inline void stm32l4_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c
index 689fb2bc515..0a903bd12d8 100644
--- a/arch/arm/src/stm32l5/stm32l5_start.c
+++ b/arch/arm/src/stm32l5/stm32l5_start.c
@@ -150,7 +150,7 @@ static inline void stm32l5_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -180,7 +180,7 @@ static inline void stm32l5_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_start.c b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
index 58846d7cbc7..6df9cdb6470 100644
--- a/arch/arm/src/tiva/cc13xx/cc13xx_start.c
+++ b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
@@ -134,7 +134,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -164,7 +164,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_start.c b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
index ae42409ce78..bda364e2cf6 100644
--- a/arch/arm/src/tiva/common/lmxx_tm4c_start.c
+++ b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
@@ -125,7 +125,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -155,7 +155,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c
index 5b400704a81..17a044da7ff 100644
--- a/arch/arm/src/xmc4/xmc4_start.c
+++ b/arch/arm/src/xmc4/xmc4_start.c
@@ -156,7 +156,7 @@ static inline void xmc4_fpu_config(void)
    */
 
   regval = getcontrol();
-  regval |= (1 << 2);
+  regval |= CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@@ -186,7 +186,7 @@ static inline void xmc4_fpu_config(void)
    */
 
   regval = getcontrol();
-  regval &= ~(1 << 2);
+  regval &= ~CONTROL_FPCA;
   setcontrol(regval);
 
   /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend