Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-21 04:52:02 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

In order to get PHY interrupts, they must be enabled at the PHY (still don't get PHY interrupts)

Browse Source
This commit is contained in:
Gregory Nutt
2014-08-17 13:03:18 -06:00
parent 5ba42680ac
commit e04ab2bcfc
9 changed files with 382 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/nuttx/net/gmii.h
+23 -1
View File
@@ -73,7 +73,7 @@
/* Extended Registers: Registers 16-31 may be used for vendor specific abilities */
/* Micrel KSZ9021/31 Vendor Specific Register Addresses */
/* Micrel KSZ9021/31 Vendor Specific Register Addresses **************************************/
#define GMII_KSZ90x1_RLPBK 17 /* Remote loopback, LED mode */
#define GMII_KSZ90x1_LINKMD 18 /* LinkMD(c) cable diagnostic */
@@ -269,6 +269,28 @@
/* Extend Register - Data Write Register (16-bit data value) */
/* Extend Register - Data Read Register (16-bit data value) */
/* Micrel KSZ9021/31 Vendor Specific Register Bit Definitions ********************************/
/* KSZ8021/31 Register 27: Interrupt control/status */
#define GMII_KSZ90x1_INT_JEN (1 << 15) /* Jabber interrupt enable */
#define GMII_KSZ90x1_INT_REEN (1 << 14) /* Receive error interrupt enable */
#define GMII_KSZ90x1_INT_PREN (1 << 13) /* Page received interrupt enable */
#define GMII_KSZ90x1_INT_PDFEN (1 << 12) /* Parallel detect fault interrupt enable */
#define GMII_KSZ90x1_INT_LPAEN (1 << 11) /* Link partner acknowledge interrupt enable */
#define GMII_KSZ90x1_INT_LDEN (1 << 10) /* Link down fault interrupt enable */
#define GMII_KSZ90x1_INT_RFEN (1 << 9) /* Remote fault interrupt enable */
#define GMII_KSZ90x1_INT_LUEN (1 << 8) /* Link up interrupt enable */
#define GMII_KSZ90x1_INT_J (1 << 7) /* Jabber interrupt */
#define GMII_KSZ90x1_INT_RE (1 << 6) /* Receive error interrupt */
#define GMII_KSZ90x1_INT_PR (1 << 5) /* Page received interrupt */
#define GMII_KSZ90x1_INT_PDF (1 << 4) /* Parallel detect fault interrupt */
#define GMII_KSZ90x1_INT_LPA (1 << 3) /* Link partner acknowledge interrupt */
#define GMII_KSZ90x1_INT_LD (1 << 2) /* Link down fault interrupt */
#define GMII_KSZ90x1_INT_RF (1 << 1) /* Remote fault interrupt */
#define GMII_KSZ90x1_INT_LU (1 << 0) /* Link up interrupt */
/*********************************************************************************************
* Type Definitions
*********************************************************************************************/
include/nuttx/net/mii.h
+20
View File
@@ -487,6 +487,26 @@
/* Bits 5-15: Reserved */
#define KSZ8081_DRCTRL_PLLOFF (1 << 4) /* Bit 4: Turn PLL off in EDPD mode */
/* Bits 0-3: Reserved */
/* KSZ8051/81 Register 0x1b: Interrupt control/status */
#define MII_KSZ80x1_INT_JEN (1 << 15) /* Jabber interrupt enable */
#define MII_KSZ80x1_INT_REEN (1 << 14) /* Receive error interrupt enable */
#define MII_KSZ80x1_INT_PREN (1 << 13) /* Page received interrupt enable */
#define MII_KSZ80x1_INT_PDFEN (1 << 12) /* Parallel detect fault interrupt enable */
#define MII_KSZ80x1_INT_LPAEN (1 << 11) /* Link partner acknowledge interrupt enable */
#define MII_KSZ80x1_INT_LDEN (1 << 10) /* Link down fault interrupt enable */
#define MII_KSZ80x1_INT_RFEN (1 << 9) /* Remote fault interrupt enable */
#define MII_KSZ80x1_INT_LUEN (1 << 8) /* Link up interrupt enable */
#define MII_KSZ80x1_INT_J (1 << 7) /* Jabber interrupt */
#define MII_KSZ80x1_INT_RE (1 << 6) /* Receive error interrupt */
#define MII_KSZ80x1_INT_PR (1 << 5) /* Page received interrupt */
#define MII_KSZ80x1_INT_PDF (1 << 4) /* Parallel detect fault interrupt */
#define MII_KSZ80x1_INT_LPA (1 << 3) /* Link partner acknowledge interrupt */
#define MII_KSZ80x1_INT_LD (1 << 2) /* Link down fault interrupt */
#define MII_KSZ80x1_INT_RF (1 << 1) /* Remote fault interrupt */
#define MII_KSZ80x1_INT_LU (1 << 0) /* Link up interrupt */
/* KSZ8051/81 Register 0x1e: PHY Control 1 */
/* Bits 10-15: Reserved */
#define MII_PHYCTRL1_ENPAUSE (1 << 9) /* Bit 9: Enable pause */