diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index 7fa5bd94607..12d71876406 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/stm32l4/chip.h * - * Copyright (C) 2015 Sebastien Lorquet. All rights reserved. + * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. * Author: Sebastien Lorquet * * Redistribution and use in source and binary forms, with or without @@ -87,7 +87,7 @@ # define STM32L4_NSAI 2 /* SAI1-2 */ # define STM32L4_NSDMMC 1 /* SDMMC interface */ # define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NGPIO 8 /* 11 GPIO ports, GPIOA-H */ +# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ # define STM32L4_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */ # define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ # define STM32L4_NCRC 1 /* CRC */ diff --git a/arch/arm/src/imx6/imx_clockconfig.c b/arch/arm/src/imx6/imx_clockconfig.c index a4d6b9a433e..f2610067ea7 100644 --- a/arch/arm/src/imx6/imx_clockconfig.c +++ b/arch/arm/src/imx6/imx_clockconfig.c @@ -66,6 +66,12 @@ void imx_clockconfig(void) * from SDRAM. In this case, some bootloader logic has already configured * clocking and SDRAM. We are pretty much committed to using things the * way that the bootloader has left them. + * + * Clocking will be configured at 792 MHz initially when started via + * U-Boot. The Linux kernel will uses the CPU frequency scaling code + * which will switch the processor frequency between 400 MHz and 1GHz based + * on load and temperature. For now, NuttX simply leaves the clocking at + * 792MHz. */ #ifndef CONFIG_IMX6_BOOT_SDRAM diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h index 74f2882fad5..2e72915e82b 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h @@ -37,10 +37,15 @@ #define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_GPIO_H /************************************************************************************ - * Pre-processor Definitions + * Included Files ************************************************************************************/ -#define STM32L4_NGPIO_PORTS (8) +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /* Register Offsets *****************************************************************/ @@ -57,7 +62,7 @@ /* Register Addresses ***************************************************************/ -#if STM32L4_NGPIO_PORTS > 0 +#if STM32L4_NPORTS > 0 # define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -70,7 +75,7 @@ # define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 1 +#if STM32L4_NPORTS > 1 # define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -83,7 +88,7 @@ # define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 2 +#if STM32L4_NPORTS > 2 # define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -96,7 +101,7 @@ # define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 3 +#if STM32L4_NPORTS > 3 # define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -109,7 +114,7 @@ # define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 4 +#if STM32L4_NPORTS > 4 # define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -122,7 +127,7 @@ # define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 5 +#if STM32L4_NPORTS > 5 # define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -135,7 +140,7 @@ # define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 6 +#if STM32L4_NPORTS > 6 # define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET) @@ -148,7 +153,7 @@ # define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET) #endif -#if STM32L4_NGPIO_PORTS > 7 +#if STM32L4_NPORTS > 7 # define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET) # define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET) # define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 9f8be7fe6d5..8ae6efdb118 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -48,6 +48,7 @@ #include #include +#include #include "up_arch.h" @@ -58,43 +59,35 @@ # include "chip/stm32l4_syscfg.h" #endif -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Public Data ****************************************************************************/ /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L4_NGPIO_PORTS] = +const uint32_t g_gpiobase[STM32L4_NPORTS] = { -#if STM32L4_NGPIO_PORTS > 0 +#if STM32L4_NPORTS > 0 STM32L4_GPIOA_BASE, #endif -#if STM32L4_NGPIO_PORTS > 1 +#if STM32L4_NPORTS > 1 STM32L4_GPIOB_BASE, #endif -#if STM32L4_NGPIO_PORTS > 2 +#if STM32L4_NPORTS > 2 STM32L4_GPIOC_BASE, #endif -#if STM32L4_NGPIO_PORTS > 3 +#if STM32L4_NPORTS > 3 STM32L4_GPIOD_BASE, #endif -#if STM32L4_NGPIO_PORTS > 4 +#if STM32L4_NPORTS > 4 STM32L4_GPIOE_BASE, #endif -#if STM32L4_NGPIO_PORTS > 5 +#if STM32L4_NPORTS > 5 STM32L4_GPIOF_BASE, #endif -#if STM32L4_NGPIO_PORTS > 6 +#if STM32L4_NPORTS > 6 STM32L4_GPIOG_BASE, #endif -#if STM32L4_NGPIO_PORTS > 7 +#if STM32L4_NPORTS > 7 STM32L4_GPIOH_BASE, #endif }; @@ -158,7 +151,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L4_NGPIO_PORTS) + if (port >= STM32L4_NPORTS) { return -EINVAL; } @@ -402,7 +395,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NGPIO_PORTS) + if (port < STM32L4_NPORTS) { /* Get the port base address */ @@ -443,7 +436,7 @@ bool stm32l4_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NGPIO_PORTS) + if (port < STM32L4_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 88f82323c53..185af4810fb 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -50,6 +50,7 @@ #endif #include +#include #include "chip.h" @@ -255,7 +256,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L4_NGPIO_PORTS]; +EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; /************************************************************************************ * Public Function Prototypes diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index f5e776a2ddc..30e02f3b1c9 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -39,6 +39,9 @@ * Included Files ****************************************************************************/ +#include +#include + #include "stm32l4_pwr.h" #include "stm32l4_flash.h" @@ -178,27 +181,27 @@ static inline void rcc_enableahb2(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NGPIO > 0 +#if STM32L4_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NGPIO > 16 +#if STM32L4_NPORTS > 16 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NGPIO > 32 +#if STM32L4_NPORTS > 32 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NGPIO > 48 +#if STM32L4_NPORTS > 48 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NGPIO > 64 +#if STM32L4_NPORTS > 64 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NGPIO > 80 +#if STM32L4_NPORTS > 80 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NGPIO > 96 +#if STM32L4_NPORTS > 96 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NGPIO > 112 +#if STM32L4_NPORTS > 112 | RCC_AHB2ENR_GPIOHEN #endif );