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https://github.com/apache/nuttx.git
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Mirtoo: Switch to SPI mode 1
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4872 42af7a65-404d-4744-a932-0658087f49c3
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@@ -865,3 +865,17 @@ Where <subdir> is one of the following:
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CONFIG_NSH_DISABLE_SH=y
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CONFIG_NSH_DISABLE_SH=y
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CONFIG_NSH_DISABLE_TEST=y
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CONFIG_NSH_DISABLE_TEST=y
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CONFIG_NSH_DISABLE_WGET=y
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CONFIG_NSH_DISABLE_WGET=y
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NOTES: (1) It takes many seconds to boot the sytem using the NXFFS
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file system because the entire FLASH must be verified on power up.
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(2) FAT does not have this delay and this configuration can be
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modified to use the (larger) FAT file system as described below:
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fat:
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There is no FAT configuration, but the nxffx configuration can be used
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to support the FAT FS if the following changes are made to the NuttX
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configuration file:
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CONFIG_FS_NXFFS=n
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CONFIG_FS_FAT=y
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CONFIG_NSH_DISABLE_MKFATFS=n
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@@ -169,8 +169,8 @@ CONFIG_PIC32MX_IOPORTC=y
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# Mirtoo Board Settings
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# Mirtoo Board Settings
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#
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#
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CONFIG_MTD_SST25=n
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CONFIG_MTD_SST25=n
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#CONFIG_SST25_SPIMODE
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CONFIG_SST25_SPIMODE=1
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#CONFIG_SST25_SPIFREQUENCY
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CONFIG_SST25_SPIFREQUENCY=20000000
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CONFIG_SST25_SECTOR512=n
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CONFIG_SST25_SECTOR512=n
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#
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#
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@@ -169,9 +169,9 @@ CONFIG_PIC32MX_IOPORTC=y
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# Mirtoo Board Settings
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# Mirtoo Board Settings
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#
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#
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CONFIG_MTD_SST25=y
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CONFIG_MTD_SST25=y
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#CONFIG_SST25_SPIMODE
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CONFIG_SST25_SPIMODE=1
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#CONFIG_SST25_SPIFREQUENCY
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CONFIG_SST25_SPIFREQUENCY=20000000
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CONFIG_SST25_SECTOR512=y
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CONFIG_SST25_SECTOR512=n
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#
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#
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# PIC32MX Configuration Settings
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# PIC32MX Configuration Settings
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+4
-4
@@ -60,7 +60,7 @@
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* Pre-processor Definitions
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* Pre-processor Definitions
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************************************************************************************/
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Configuration ********************************************************************/
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/* Per the data sheet, MP25P10 parts can be driven with either SPI mode 0 (CPOL=0 and
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/* Per the data sheet, the SST25 parts can be driven with either SPI mode 0 (CPOL=0 and
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* CPHA=0) or mode 3 (CPOL=1 and CPHA=1). But I have heard that other devices can
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* CPHA=0) or mode 3 (CPOL=1 and CPHA=1). But I have heard that other devices can
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* operated in mode 0 or 1. So you may need to specify CONFIG_SST25_SPIMODE to
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* operated in mode 0 or 1. So you may need to specify CONFIG_SST25_SPIMODE to
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* select the best mode for your device. If CONFIG_SST25_SPIMODE is not defined,
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* select the best mode for your device. If CONFIG_SST25_SPIMODE is not defined,
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@@ -397,8 +397,6 @@ static void sst25_waitwritecomplete(struct sst25_dev_s *priv)
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}
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}
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while ((status & SST25_SR_BUSY) != 0);
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while ((status & SST25_SR_BUSY) != 0);
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#endif
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#endif
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fvdbg("Complete\n");
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}
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}
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/************************************************************************************
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/************************************************************************************
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@@ -946,11 +944,13 @@ static int sst25_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
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#ifdef CONFIG_SST25_SECTOR512
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#ifdef CONFIG_SST25_SECTOR512
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geo->blocksize = (1 << SST25_SECTOR_SHIFT);
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geo->blocksize = (1 << SST25_SECTOR_SHIFT);
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geo->erasesize = (1 << SST25_SECTOR_SHIFT);
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geo->neraseblocks = priv->nsectors << (priv->sectorshift - );
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#else
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#else
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geo->blocksize = (1 << priv->sectorshift);
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geo->blocksize = (1 << priv->sectorshift);
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#endif
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geo->erasesize = (1 << priv->sectorshift);
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geo->erasesize = (1 << priv->sectorshift);
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geo->neraseblocks = priv->nsectors;
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geo->neraseblocks = priv->nsectors;
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#endif
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ret = OK;
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ret = OK;
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fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
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fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
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