arch/arm64: add cache enable and disable function

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>

arch/arm64/src/common/arm64_cache.c

@@ -308,6 +308,48 @@ void up_invalidate_icache_all(void)
   __ic_ialluis();
 }
 
+/****************************************************************************
+ * Name: up_enable_icache
+ *
+ * Description:
+ *   Enable the I-Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void up_enable_icache(void)
+{
+  uint64_t value = read_sysreg(sctlr_el1);
+  write_sysreg((value | SCTLR_I_BIT), sctlr_el1);
+  ARM64_ISB();
+}
+
+/****************************************************************************
+ * Name: up_disable_icache
+ *
+ * Description:
+ *   Disable the I-Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void up_disable_icache(void)
+{
+  uint64_t value = read_sysreg(sctlr_el1);
+  write_sysreg((value & ~SCTLR_I_BIT), sctlr_el1);
+  ARM64_ISB();
+}
+
 /****************************************************************************
  * Name: up_invalidate_dcache
  *
@@ -373,8 +415,8 @@ void up_invalidate_dcache_all(void)
 
 size_t up_get_dcache_linesize(void)
 {
-  uint64_t  ctr_el0;
+  uint64_t ctr_el0;
-  uint32_t  dminline;
+  uint32_t dminline;
 
   if (g_dcache_line_size != 0)
     {
@@ -453,6 +495,48 @@ void up_clean_dcache_all(void)
   arm64_dcache_all(CACHE_OP_WB);
 }
 
+/****************************************************************************
+ * Name: up_enable_dcache
+ *
+ * Description:
+ *   Enable the D-Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void up_enable_dcache(void)
+{
+  uint64_t value = read_sysreg(sctlr_el1);
+  write_sysreg((value | SCTLR_C_BIT), sctlr_el1);
+  ARM64_ISB();
+}
+
+/****************************************************************************
+ * Name: up_disable_dcache
+ *
+ * Description:
+ *   Disable the D-Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void up_disable_dcache(void)
+{
+  uint64_t value = read_sysreg(sctlr_el1);
+  write_sysreg((value & ~SCTLR_C_BIT), sctlr_el1);
+  ARM64_ISB();
+}
+
 /****************************************************************************
  * Name: up_flush_dcache
  *

arch/arm64/src/common/arm64_cpustart.c

@@ -93,7 +93,7 @@ static inline void local_delay(void)
     }
 }
 
-#ifdef CONFIG_ARCH_HAVE_MMU
+#if defined (CONFIG_ARCH_HAVE_MMU) || defined (CONFIG_ARCH_HAVE_MPU)
 static void flush_boot_params(void)
 {
   uintptr_t flush_start;
@@ -104,11 +104,6 @@ static void flush_boot_params(void)
 
   up_flush_dcache(flush_start, flush_end);
 }
-#else
-static void flush_boot_params(void)
-{
-  /* TODO: Flush at MPU platform */
-}
 #endif
 
 static void arm64_smp_init_top(void *arg)

arch/arm64/src/common/arm64_mpu.c

@@ -99,7 +99,7 @@ void arm64_core_mpu_enable(void)
   uint64_t val;
 
   val   = read_sysreg(sctlr_el1);
-  val   |= SCTLR_M_BIT;
+  val   |= (SCTLR_M_BIT | SCTLR_C_BIT);
   write_sysreg(val, sctlr_el1);
   ARM64_DSB();
   ARM64_ISB();
@@ -118,7 +118,7 @@ void arm64_core_mpu_disable(void)
   ARM64_DMB();
 
   val   = read_sysreg(sctlr_el1);
-  val   &= ~SCTLR_M_BIT;
+  val   &= ~(SCTLR_M_BIT | SCTLR_C_BIT);
   write_sysreg(val, sctlr_el1);
   ARM64_DSB();
   ARM64_ISB();

arch/arm64/src/common/arm64_mpu.h

@@ -202,13 +202,23 @@
     .mair_idx = MPU_MAIR_INDEX_DEVICE,                    \
   }
 
-#define REGION_RAM_ATTR                                   \
+#ifdef CONFIG_SMP
-  {                                                       \
+#  define REGION_RAM_ATTR                                        \
-    /* AP, XN, SH */                                      \
+    {                                                            \
-    .rbar = NOT_EXEC | P_RW_U_NA_MSK | NON_SHAREABLE_MSK, \
+      /* AP, XN, SH */                                           \
-    /* Cache-ability */                                   \
+      .rbar = (NOT_EXEC | P_RW_U_NA_MSK | INNER_SHAREABLE_MSK) , \
-    .mair_idx = MPU_MAIR_INDEX_SRAM,                      \
+      /* Cache-ability */                                        \
-  }
+      .mair_idx = MPU_MAIR_INDEX_SRAM,                           \
+    }
+#else
+#  define REGION_RAM_ATTR                                   \
+    {                                                       \
+      /* AP, XN, SH */                                      \
+      .rbar = NOT_EXEC | P_RW_U_NA_MSK | NON_SHAREABLE_MSK, \
+      /* Cache-ability */                                   \
+      .mair_idx = MPU_MAIR_INDEX_SRAM,                      \
+    }
+#endif
 
 #define REGION_RAM_TEXT_ATTR                   \
   {                                            \
@@ -232,11 +242,11 @@ struct arm64_mpu_region_attr
 {
   /* Attributes belonging to PRBAR */
 
-  uint8_t rbar : 5;
+  uint8_t rbar;
 
   /* MAIR index for attribute indirection */
 
-  uint8_t mair_idx : 3;
+  uint8_t mair_idx;
 };
 
 /* Region definition data structure */

boards/arm64/fvp-v8r/fvp-armv8r/scripts/fvp_cfg_smp.txt

@@ -22,4 +22,4 @@ bp.pl011_uart3.unbuffered_output=1
 bp.terminal_3.start_telnet=0
 bp.vis.disable_visualisation=1
 bp.vis.rate_limit-enable=0
-cache_state_modelled=0
+cache_state_modelled=1