mirror of
https://github.com/apache/nuttx.git
synced 2026-06-01 07:45:16 +08:00
arch/arm: Move FPU initialization to common place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
committed by
Petro Karashchenko
Petro Karashchenko
parent
7660b3b1c4
commit
df5a8a53ae
@@ -34,7 +34,6 @@
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#include "chip.h"
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#include "chip.h"
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#include "arm.h"
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#include "arm.h"
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#include "mmu.h"
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#include "mmu.h"
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#include "fpu.h"
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#include "arm_internal.h"
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#include "arm_internal.h"
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#include "a1x_lowputc.h"
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#include "a1x_lowputc.h"
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#include "a1x_boot.h"
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#include "a1x_boot.h"
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@@ -300,11 +299,9 @@ void arm_boot(void)
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a1x_copyvectorblock();
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a1x_copyvectorblock();
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#ifdef CONFIG_ARCH_FPU
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/* Initialize the FPU */
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/* Initialize the FPU */
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arm_fpuconfig();
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arm_fpuconfig();
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#endif
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#ifdef CONFIG_BOOT_SDRAM_DATA
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#ifdef CONFIG_BOOT_SDRAM_DATA
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/* This setting is inappropriate for the A1x because the code is *always*
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/* This setting is inappropriate for the A1x because the code is *always*
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@@ -38,7 +38,6 @@
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#include "chip.h"
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#include "chip.h"
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#include "arm.h"
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#include "arm.h"
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#include "mmu.h"
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#include "mmu.h"
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#include "fpu.h"
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#include "arm_internal.h"
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#include "arm_internal.h"
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#include "am335x_clockconfig.h"
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#include "am335x_clockconfig.h"
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#include "am335x_wdog.h"
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#include "am335x_wdog.h"
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@@ -402,11 +401,9 @@ void arm_boot(void)
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am335x_clockconfig();
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am335x_clockconfig();
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#ifdef CONFIG_ARCH_FPU
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/* Initialize the FPU */
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/* Initialize the FPU */
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arm_fpuconfig();
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arm_fpuconfig();
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#endif
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/* Disable CPU Watchdog */
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/* Disable CPU Watchdog */
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@@ -1,77 +0,0 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/fpu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_A_FPU_H
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#define __ARCH_ARM_SRC_ARMV7_A_FPU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arm_fpuconfig
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*
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* Description:
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* Configure the FPU. Enables access to CP10 and CP11
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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void arm_fpuconfig(void);
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_ARMV7_A_FPU_H */
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@@ -0,0 +1,117 @@
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/****************************************************************************
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* arch/arm/src/armv7-m/arm_fpuconfig.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "nvic.h"
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#include "arm_internal.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_fpuconfig
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*
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* Description:
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* Configure the FPU. Relative bit settings:
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*
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* CPACR: Enables access to CP10 and CP11
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* CONTROL.FPCA: Determines whether the FP extension is active in the
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* current context:
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* FPCCR.ASPEN: Enables automatic FP state preservation, then the
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* processor sets this bit to 1 on successful completion of any FP
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* instruction.
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* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
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* done, the processor reserves space on the stack for the FP state,
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* but does not save that state information to the stack.
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*
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* Software must not change the value of the ASPEN bit or LSPEN bit while
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* either:
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*
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* - the CPACR permits access to CP10 and CP11, that give access to the FP
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* extension, or
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* - the CONTROL.FPCA bit is set to 1
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*
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****************************************************************************/
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#ifndef CONFIG_ARMV7M_LAZYFPU
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void arm_fpuconfig(void)
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{
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uint32_t regval;
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/* Set CONTROL.FPCA so that we always get the extended context frame
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* with the volatile FP registers stacked above the basic context.
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*/
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regval = getcontrol();
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regval |= CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
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* are going to turn on CONTROL.FPCA for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
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}
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#else
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void arm_fpuconfig(void)
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{
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uint32_t regval;
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/* Clear CONTROL.FPCA so that we do not get the extended context frame
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* with the volatile FP registers stacked in the saved context.
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*/
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regval = getcontrol();
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regval &= ~CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
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* are going to keep CONTROL.FPCA off for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
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}
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#endif
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@@ -1,77 +0,0 @@
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/****************************************************************************
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* arch/arm/src/armv7-r/fpu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_R_FPU_H
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#define __ARCH_ARM_SRC_ARMV7_R_FPU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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|
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arm_fpuconfig
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*
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* Description:
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* Configure the FPU. Enables access to CP10 and CP11
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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void arm_fpuconfig(void);
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_ARMV7_R_FPU_H */
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@@ -0,0 +1,117 @@
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/****************************************************************************
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* arch/arm/src/armv8-m/arm_fpuconfig.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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|
* contributor license agreements. See the NOTICE file distributed with
|
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|
* this work for additional information regarding copyright ownership. The
|
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|
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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|
* "License"); you may not use this file except in compliance with the
|
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|
* License. You may obtain a copy of the License at
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|
*
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|
* http://www.apache.org/licenses/LICENSE-2.0
|
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|
*
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|
* Unless required by applicable law or agreed to in writing, software
|
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|
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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|
* License for the specific language governing permissions and limitations
|
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|
* under the License.
|
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|
*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "nvic.h"
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#include "arm_internal.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
|
||||||
|
* Name: arm_fpuconfig
|
||||||
|
*
|
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|
* Description:
|
||||||
|
* Configure the FPU. Relative bit settings:
|
||||||
|
*
|
||||||
|
* CPACR: Enables access to CP10 and CP11
|
||||||
|
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
||||||
|
* current context:
|
||||||
|
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
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|
* processor sets this bit to 1 on successful completion of any FP
|
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|
* instruction.
|
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|
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
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|
* done, the processor reserves space on the stack for the FP state,
|
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|
* but does not save that state information to the stack.
|
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|
*
|
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|
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
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|
* either:
|
||||||
|
*
|
||||||
|
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
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|
* extension, or
|
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|
* - the CONTROL.FPCA bit is set to 1
|
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|
*
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****************************************************************************/
|
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#ifndef CONFIG_ARMV8M_LAZYFPU
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void arm_fpuconfig(void)
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{
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uint32_t regval;
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|
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/* Set CONTROL.FPCA so that we always get the extended context frame
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* with the volatile FP registers stacked above the basic context.
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*/
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regval = getcontrol();
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regval |= CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
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|
* are going to turn on CONTROL.FPCA for all contexts.
|
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|
*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
void arm_fpuconfig(void)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
|
||||||
|
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
||||||
|
* with the volatile FP registers stacked in the saved context.
|
||||||
|
*/
|
||||||
|
|
||||||
|
regval = getcontrol();
|
||||||
|
regval &= ~CONTROL_FPCA;
|
||||||
|
setcontrol(regval);
|
||||||
|
|
||||||
|
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
||||||
|
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
||||||
|
* are going to keep CONTROL.FPCA off for all contexts.
|
||||||
|
*/
|
||||||
|
|
||||||
|
regval = getreg32(NVIC_FPCCR);
|
||||||
|
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
||||||
|
putreg32(regval, NVIC_FPCCR);
|
||||||
|
|
||||||
|
/* Enable full access to CP10 and CP11 */
|
||||||
|
|
||||||
|
regval = getreg32(NVIC_CPACR);
|
||||||
|
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
||||||
|
putreg32(regval, NVIC_CPACR);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -440,9 +440,11 @@ void arm_vectorfiq(void);
|
|||||||
/* Floating point unit ******************************************************/
|
/* Floating point unit ******************************************************/
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
#ifdef CONFIG_ARCH_FPU
|
||||||
|
void arm_fpuconfig(void);
|
||||||
void arm_savefpu(uint32_t *regs);
|
void arm_savefpu(uint32_t *regs);
|
||||||
void arm_restorefpu(const uint32_t *regs);
|
void arm_restorefpu(const uint32_t *regs);
|
||||||
#else
|
#else
|
||||||
|
# define arm_fpuconfig()
|
||||||
# define arm_savefpu(regs)
|
# define arm_savefpu(regs)
|
||||||
# define arm_restorefpu(regs)
|
# define arm_restorefpu(regs)
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@@ -62,6 +62,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
||||||
|
|||||||
@@ -73,7 +73,6 @@
|
|||||||
volatile static spinlock_t g_appdsp_boot;
|
volatile static spinlock_t g_appdsp_boot;
|
||||||
|
|
||||||
extern int arm_pause_handler(int irq, void *c, FAR void *arg);
|
extern int arm_pause_handler(int irq, void *c, FAR void *arg);
|
||||||
extern void fpuconfig(void);
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
@@ -104,7 +103,7 @@ static void appdsp_boot(void)
|
|||||||
|
|
||||||
/* Setup FPU */
|
/* Setup FPU */
|
||||||
|
|
||||||
fpuconfig();
|
arm_fpuconfig();
|
||||||
|
|
||||||
/* Clear SW_INT for APP_DSP(cpu) */
|
/* Clear SW_INT for APP_DSP(cpu) */
|
||||||
|
|
||||||
|
|||||||
@@ -110,97 +110,6 @@ extern uint32_t _vectors[];
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
# ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
void fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
# else
|
|
||||||
|
|
||||||
void fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
# endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: _start
|
* Name: _start
|
||||||
*
|
*
|
||||||
@@ -269,7 +178,7 @@ void __start(void)
|
|||||||
|
|
||||||
/* Initialize the FPU (if configured) */
|
/* Initialize the FPU (if configured) */
|
||||||
|
|
||||||
fpuconfig();
|
arm_fpuconfig();
|
||||||
|
|
||||||
#ifdef CONFIG_ARMV7M_ITMSYSLOG
|
#ifdef CONFIG_ARMV7M_ITMSYSLOG
|
||||||
/* Perform ARMv7-M ITM SYSLOG initialization */
|
/* Perform ARMv7-M ITM SYSLOG initialization */
|
||||||
|
|||||||
@@ -58,6 +58,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
||||||
|
|||||||
@@ -70,14 +70,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void efm32_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -102,96 +94,6 @@ static inline void efm32_fpuconfig(void);
|
|||||||
# define showprogress(c)
|
# define showprogress(c)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: efm32_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void efm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void efm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define efm32_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -212,7 +114,7 @@ void __start(void)
|
|||||||
/* Configure the uart so that we can get debug output as soon as possible */
|
/* Configure the uart so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
efm32_clockconfig();
|
efm32_clockconfig();
|
||||||
efm32_fpuconfig();
|
arm_fpuconfig();
|
||||||
efm32_lowsetup();
|
efm32_lowsetup();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|
||||||
|
|||||||
@@ -56,6 +56,10 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
|
|||||||
CMN_CSRCS += arm_checkstack.c
|
CMN_CSRCS += arm_checkstack.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
|
endif
|
||||||
|
|
||||||
CHIP_CSRCS = eoss3_start.c eoss3_gpio.c eoss3_lowputc.c eoss3_clockconfig.c
|
CHIP_CSRCS = eoss3_start.c eoss3_gpio.c eoss3_lowputc.c eoss3_clockconfig.c
|
||||||
CHIP_CSRCS += eoss3_irq.c
|
CHIP_CSRCS += eoss3_irq.c
|
||||||
CHIP_CSRCS += eoss3_serial.c
|
CHIP_CSRCS += eoss3_serial.c
|
||||||
|
|||||||
@@ -64,14 +64,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void eoss3_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -100,97 +92,6 @@ static inline void eoss3_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: eoss3_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void eoss3_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void eoss3_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define eoss3_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -219,10 +120,7 @@ void __start(void)
|
|||||||
|
|
||||||
eoss3_clockconfig();
|
eoss3_clockconfig();
|
||||||
|
|
||||||
/* Unclear what needs to happen here to make RENODE happy. */
|
arm_fpuconfig();
|
||||||
#if 1
|
|
||||||
eoss3_fpuconfig();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
eoss3_lowsetup();
|
eoss3_lowsetup();
|
||||||
|
|
||||||
|
|||||||
@@ -39,7 +39,6 @@
|
|||||||
#include "arm.h"
|
#include "arm.h"
|
||||||
#include "mmu.h"
|
#include "mmu.h"
|
||||||
#include "scu.h"
|
#include "scu.h"
|
||||||
#include "fpu.h"
|
|
||||||
#include "arm_internal.h"
|
#include "arm_internal.h"
|
||||||
#include "imx_config.h"
|
#include "imx_config.h"
|
||||||
#include "imx_clockconfig.h"
|
#include "imx_clockconfig.h"
|
||||||
@@ -443,12 +442,10 @@ void arm_boot(void)
|
|||||||
imx_clockconfig();
|
imx_clockconfig();
|
||||||
PROGRESS('I');
|
PROGRESS('I');
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
/* Initialize the FPU */
|
/* Initialize the FPU */
|
||||||
|
|
||||||
arm_fpuconfig();
|
arm_fpuconfig();
|
||||||
PROGRESS('J');
|
PROGRESS('J');
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Perform board-specific memory initialization, This must include
|
/* Perform board-specific memory initialization, This must include
|
||||||
* initialization of board-specific memory resources (e.g., SDRAM)
|
* initialization of board-specific memory resources (e.g., SDRAM)
|
||||||
|
|||||||
@@ -35,7 +35,6 @@
|
|||||||
#include "sctlr.h"
|
#include "sctlr.h"
|
||||||
#include "smp.h"
|
#include "smp.h"
|
||||||
#include "scu.h"
|
#include "scu.h"
|
||||||
#include "fpu.h"
|
|
||||||
#include "gic.h"
|
#include "gic.h"
|
||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
@@ -247,11 +246,9 @@ void arm_cpu_boot(int cpu)
|
|||||||
|
|
||||||
arm_enable_smp(cpu);
|
arm_enable_smp(cpu);
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
/* Initialize the FPU */
|
/* Initialize the FPU */
|
||||||
|
|
||||||
arm_fpuconfig();
|
arm_fpuconfig();
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
|
/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
|
||||||
|
|
||||||
|
|||||||
@@ -72,6 +72,7 @@ CMN_CSRCS += arm_cache.c
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# Required i.MX RT files
|
# Required i.MX RT files
|
||||||
|
|||||||
@@ -65,14 +65,6 @@
|
|||||||
* here.
|
* here.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void imxrt_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -83,98 +75,6 @@ static inline void imxrt_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: imxrt_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
*
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void imxrt_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void imxrt_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define imxrt_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: imxrt_tcmenable
|
* Name: imxrt_tcmenable
|
||||||
*
|
*
|
||||||
@@ -286,7 +186,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
imxrt_clockconfig();
|
imxrt_clockconfig();
|
||||||
imxrt_fpuconfig();
|
arm_fpuconfig();
|
||||||
imxrt_lowsetup();
|
imxrt_lowsetup();
|
||||||
|
|
||||||
/* Enable/disable tightly coupled memories */
|
/* Enable/disable tightly coupled memories */
|
||||||
|
|||||||
@@ -76,6 +76,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
||||||
|
|||||||
@@ -40,14 +40,6 @@
|
|||||||
|
|
||||||
#include "kinetis_start.h"
|
#include "kinetis_start.h"
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void kinetis_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -96,96 +88,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: kinetis_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void kinetis_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void kinetis_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define kinetis_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -258,7 +160,7 @@ void __start(void)
|
|||||||
* configuration).
|
* configuration).
|
||||||
*/
|
*/
|
||||||
|
|
||||||
kinetis_fpuconfig();
|
arm_fpuconfig();
|
||||||
kinetis_lowsetup();
|
kinetis_lowsetup();
|
||||||
#ifdef USE_EARLYSERIALINIT
|
#ifdef USE_EARLYSERIALINIT
|
||||||
kinetis_earlyserialinit();
|
kinetis_earlyserialinit();
|
||||||
|
|||||||
@@ -74,6 +74,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# Required LPC17xx files
|
# Required LPC17xx files
|
||||||
|
|||||||
@@ -86,96 +86,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
|
|||||||
# define showprogress(c)
|
# define showprogress(c)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: lpc17_40_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void lpc17_40_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void lpc17_40_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define lpc17_40_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -213,7 +123,7 @@ void __start(void)
|
|||||||
/* Configure the uart so that we can get debug output as soon as possible */
|
/* Configure the uart so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
lpc17_40_clockconfig();
|
lpc17_40_clockconfig();
|
||||||
lpc17_40_fpuconfig();
|
arm_fpuconfig();
|
||||||
lpc17_40_lowsetup();
|
lpc17_40_lowsetup();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|
||||||
|
|||||||
@@ -62,6 +62,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c
|
CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c
|
||||||
|
|||||||
@@ -83,7 +83,7 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -153,97 +153,6 @@ static inline void lpc43_enabuffering(void)
|
|||||||
# define lpc43_enabuffering()
|
# define lpc43_enabuffering()
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: lpc43_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void lpc43_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void lpc43_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define lpc43_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -316,7 +225,7 @@ void __start(void)
|
|||||||
|
|
||||||
/* Initialize the FPU (if configured) */
|
/* Initialize the FPU (if configured) */
|
||||||
|
|
||||||
lpc43_fpuconfig();
|
arm_fpuconfig();
|
||||||
showprogress('D');
|
showprogress('D');
|
||||||
|
|
||||||
/* Perform early serial initialization */
|
/* Perform early serial initialization */
|
||||||
|
|||||||
@@ -62,6 +62,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c
|
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c
|
||||||
|
|||||||
@@ -80,97 +80,6 @@ static const struct pll_setup_s g_initial_pll_setup =
|
|||||||
.ahbdiv = SYSCON_AHBCLKDIV_DIV(BOARD_AHBCLKDIV)
|
.ahbdiv = SYSCON_AHBCLKDIV_DIV(BOARD_AHBCLKDIV)
|
||||||
};
|
};
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Functions
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: lpc54_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
static inline void lpc54_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
static inline void lpc54_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define lpc54_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -234,7 +143,7 @@ void __start(void)
|
|||||||
|
|
||||||
/* Initialize the FPU (if configured) */
|
/* Initialize the FPU (if configured) */
|
||||||
|
|
||||||
lpc54_fpuconfig();
|
arm_fpuconfig();
|
||||||
showprogress('D');
|
showprogress('D');
|
||||||
|
|
||||||
/* Perform early serial initialization */
|
/* Perform early serial initialization */
|
||||||
|
|||||||
@@ -60,6 +60,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# Common MAX326XX Source Files
|
# Common MAX326XX Source Files
|
||||||
|
|||||||
@@ -80,97 +80,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = IDLE_STACK;
|
const uintptr_t g_idle_topstack = IDLE_STACK;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Functions
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: max326_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
static inline void max326_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
static inline void max326_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define max326_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -239,7 +148,7 @@ void __start(void)
|
|||||||
|
|
||||||
/* Initialize the FPU (if configured) */
|
/* Initialize the FPU (if configured) */
|
||||||
|
|
||||||
max326_fpuconfig();
|
arm_fpuconfig();
|
||||||
showprogress('E');
|
showprogress('E');
|
||||||
|
|
||||||
/* Perform early serial initialization */
|
/* Perform early serial initialization */
|
||||||
|
|||||||
@@ -70,6 +70,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_utils.c
|
CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_utils.c
|
||||||
|
|||||||
@@ -71,93 +71,6 @@
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: nrf52_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
static inline void nrf52_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
static inline void nrf52_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define nrf52_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -227,7 +140,7 @@ void __start(void)
|
|||||||
|
|
||||||
/* Initialize the FPU (if configured) */
|
/* Initialize the FPU (if configured) */
|
||||||
|
|
||||||
nrf52_fpuconfig();
|
arm_fpuconfig();
|
||||||
|
|
||||||
#ifdef CONFIG_NRF52_FLASH_PREFETCH
|
#ifdef CONFIG_NRF52_FLASH_PREFETCH
|
||||||
nrf_nvmc_enable_icache(true);
|
nrf_nvmc_enable_icache(true);
|
||||||
|
|||||||
@@ -38,6 +38,10 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
|||||||
CMN_CSRCS += arm_pthread_start.c
|
CMN_CSRCS += arm_pthread_start.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
|
endif
|
||||||
|
|
||||||
# Source files common to all S32K1xx chip families.
|
# Source files common to all S32K1xx chip families.
|
||||||
|
|
||||||
CHIP_CSRCS = s32k1xx_start.c s32k1xx_lowputc.c s32k1xx_clockconfig.c
|
CHIP_CSRCS = s32k1xx_start.c s32k1xx_lowputc.c s32k1xx_clockconfig.c
|
||||||
|
|||||||
@@ -124,93 +124,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
|
|||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: s32k1xx_fpu_config
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
static inline void s32k1xx_fpu_config(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
static inline void s32k1xx_fpu_config(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define s32k1xx_fpu_config()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: s32k1xx_cache_config
|
* Name: s32k1xx_cache_config
|
||||||
*
|
*
|
||||||
@@ -339,7 +252,7 @@ void __start(void)
|
|||||||
|
|
||||||
/* Initialize the FPU (if configured) */
|
/* Initialize the FPU (if configured) */
|
||||||
|
|
||||||
s32k1xx_fpu_config();
|
arm_fpuconfig();
|
||||||
showprogress('C');
|
showprogress('C');
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)
|
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)
|
||||||
|
|||||||
@@ -66,6 +66,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
|
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
|
||||||
|
|||||||
@@ -71,10 +71,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
|
|||||||
* Private Function prototypes
|
* Private Function prototypes
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void sam_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARMV7M_STACKCHECK
|
#ifdef CONFIG_ARMV7M_STACKCHECK
|
||||||
/* We need to get r10 set before we can allow instrumentation calls */
|
/* We need to get r10 set before we can allow instrumentation calls */
|
||||||
|
|
||||||
@@ -99,96 +95,6 @@ void __start(void) noinstrument_function;
|
|||||||
# define showprogress(c)
|
# define showprogress(c)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: sam_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void sam_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void sam_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define sam_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -257,7 +163,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
sam_clockconfig();
|
sam_clockconfig();
|
||||||
sam_fpuconfig();
|
arm_fpuconfig();
|
||||||
sam_lowsetup();
|
sam_lowsetup();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|
||||||
|
|||||||
@@ -38,7 +38,6 @@
|
|||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "arm.h"
|
#include "arm.h"
|
||||||
#include "mmu.h"
|
#include "mmu.h"
|
||||||
#include "fpu.h"
|
|
||||||
#include "arm_internal.h"
|
#include "arm_internal.h"
|
||||||
#include "hardware/sam_wdt.h"
|
#include "hardware/sam_wdt.h"
|
||||||
#include "hardware/sam_aximx.h"
|
#include "hardware/sam_aximx.h"
|
||||||
@@ -445,11 +444,9 @@ void arm_boot(void)
|
|||||||
|
|
||||||
sam_clockconfig();
|
sam_clockconfig();
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
/* Initialize the FPU */
|
/* Initialize the FPU */
|
||||||
|
|
||||||
arm_fpuconfig();
|
arm_fpuconfig();
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Perform board-specific initialization, This must include:
|
/* Perform board-specific initialization, This must include:
|
||||||
*
|
*
|
||||||
|
|||||||
@@ -56,6 +56,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
|
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
|
||||||
|
|||||||
@@ -101,96 +101,6 @@ void __start(void) noinstrument_function;
|
|||||||
# define showprogress(c)
|
# define showprogress(c)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: sam_fpu_configure
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void sam_fpu_configure(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void sam_fpu_configure(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define sam_fpu_configure()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -258,7 +168,7 @@ void __start(void)
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
sam_clock_initialize();
|
sam_clock_initialize();
|
||||||
sam_fpu_configure();
|
arm_fpuconfig();
|
||||||
sam_lowsetup();
|
sam_lowsetup();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|
||||||
|
|||||||
@@ -61,6 +61,7 @@ CMN_CSRCS += arm_cache.c
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||||
|
|||||||
@@ -78,14 +78,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void sam_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -96,96 +88,6 @@ static inline void sam_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: sam_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void sam_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void sam_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define sam_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: sam_tcmenable
|
* Name: sam_tcmenable
|
||||||
*
|
*
|
||||||
@@ -296,7 +198,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
sam_clockconfig();
|
sam_clockconfig();
|
||||||
sam_fpuconfig();
|
arm_fpuconfig();
|
||||||
sam_gpioinit();
|
sam_gpioinit();
|
||||||
sam_lowsetup();
|
sam_lowsetup();
|
||||||
|
|
||||||
|
|||||||
@@ -70,6 +70,7 @@ endif
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
|
||||||
|
|||||||
@@ -67,14 +67,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void stm32_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -103,96 +95,6 @@ static inline void stm32_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: stm32_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void stm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void stm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define stm32_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -224,7 +126,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
stm32_clockconfig();
|
stm32_clockconfig();
|
||||||
stm32_fpuconfig();
|
arm_fpuconfig();
|
||||||
stm32_lowsetup();
|
stm32_lowsetup();
|
||||||
stm32_gpioinit();
|
stm32_gpioinit();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|||||||
@@ -61,6 +61,7 @@ CMN_CSRCS += arm_cache.c
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||||
|
|||||||
@@ -79,14 +79,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void stm32_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -97,96 +89,6 @@ static inline void stm32_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: stm32_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void stm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void stm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define stm32_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: stm32_tcmenable
|
* Name: stm32_tcmenable
|
||||||
*
|
*
|
||||||
@@ -302,7 +204,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
stm32_clockconfig();
|
stm32_clockconfig();
|
||||||
stm32_fpuconfig();
|
arm_fpuconfig();
|
||||||
stm32_lowsetup();
|
stm32_lowsetup();
|
||||||
|
|
||||||
/* Enable/disable tightly coupled memories */
|
/* Enable/disable tightly coupled memories */
|
||||||
|
|||||||
@@ -58,8 +58,10 @@ endif
|
|||||||
CMN_CSRCS += arm_vectors.c
|
CMN_CSRCS += arm_vectors.c
|
||||||
|
|
||||||
CMN_CSRCS += arm_cache.c
|
CMN_CSRCS += arm_cache.c
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
||||||
|
|||||||
@@ -84,10 +84,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
|
|||||||
* Private Function prototypes
|
* Private Function prototypes
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void stm32_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: showprogress
|
* Name: showprogress
|
||||||
*
|
*
|
||||||
@@ -112,96 +108,6 @@ static inline void stm32_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: stm32_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void stm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void stm32_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define stm32_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: stm32_tcmenable
|
* Name: stm32_tcmenable
|
||||||
*
|
*
|
||||||
@@ -317,7 +223,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
stm32_clockconfig();
|
stm32_clockconfig();
|
||||||
stm32_fpuconfig();
|
arm_fpuconfig();
|
||||||
stm32_lowsetup();
|
stm32_lowsetup();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|
||||||
|
|||||||
@@ -55,6 +55,7 @@ CMN_CSRCS += arm_vectors.c
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||||
|
|||||||
@@ -75,14 +75,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void stm32l4_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -111,96 +103,6 @@ static inline void stm32l4_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: stm32l4_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV7M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void stm32l4_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void stm32l4_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define stm32l4_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -246,7 +148,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
stm32l4_clockconfig();
|
stm32l4_clockconfig();
|
||||||
stm32l4_fpuconfig();
|
arm_fpuconfig();
|
||||||
stm32l4_lowsetup();
|
stm32l4_lowsetup();
|
||||||
stm32l4_gpioinit();
|
stm32l4_gpioinit();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|||||||
@@ -60,6 +60,7 @@ CMN_CSRCS += arm_vectors.c
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||||
|
|||||||
@@ -77,14 +77,6 @@
|
|||||||
|
|
||||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
static inline void stm32l5_fpuconfig(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -113,97 +105,6 @@ static inline void stm32l5_fpuconfig(void);
|
|||||||
void __start(void) noinstrument_function;
|
void __start(void) noinstrument_function;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: stm32l5_fpuconfig
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Configure the FPU. Relative bit settings:
|
|
||||||
*
|
|
||||||
* CPACR: Enables access to CP10 and CP11
|
|
||||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
|
||||||
* current context:
|
|
||||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
|
||||||
* processor sets this bit to 1 on successful completion of any FP
|
|
||||||
* instruction.
|
|
||||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
|
||||||
* done, the processor reserves space on the stack for the FP state,
|
|
||||||
* but does not save that state information to the stack.
|
|
||||||
*
|
|
||||||
* Software must not change the value of the ASPEN bit or LSPEN bit while
|
|
||||||
* either:
|
|
||||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
|
||||||
* extension, or
|
|
||||||
* - the CONTROL.FPCA bit is set to 1
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_FPU
|
|
||||||
#ifndef CONFIG_ARMV8M_LAZYFPU
|
|
||||||
|
|
||||||
static inline void stm32l5_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
|
||||||
* with the volatile FP registers stacked above the basic context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval |= CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to turn on CONTROL.FPCA for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
static inline void stm32l5_fpuconfig(void)
|
|
||||||
{
|
|
||||||
uint32_t regval;
|
|
||||||
|
|
||||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
|
||||||
* with the volatile FP registers stacked in the saved context.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getcontrol();
|
|
||||||
regval &= ~CONTROL_FPCA;
|
|
||||||
setcontrol(regval);
|
|
||||||
|
|
||||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
|
||||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
|
||||||
* are going to keep CONTROL.FPCA off for all contexts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_FPCCR);
|
|
||||||
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
|
|
||||||
putreg32(regval, NVIC_FPCCR);
|
|
||||||
|
|
||||||
/* Enable full access to CP10 and CP11 */
|
|
||||||
|
|
||||||
regval = getreg32(NVIC_CPACR);
|
|
||||||
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
|
|
||||||
putreg32(regval, NVIC_CPACR);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
# define stm32l5_fpuconfig()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -249,7 +150,7 @@ void __start(void)
|
|||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
stm32l5_clockconfig();
|
stm32l5_clockconfig();
|
||||||
stm32l5_fpuconfig();
|
arm_fpuconfig();
|
||||||
stm32l5_lowsetup();
|
stm32l5_lowsetup();
|
||||||
stm32l5_gpioinit();
|
stm32l5_gpioinit();
|
||||||
showprogress('A');
|
showprogress('A');
|
||||||
|
|||||||
@@ -60,6 +60,7 @@ CMN_CSRCS += arm_vectors.c
|
|||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||||
CMN_ASRCS += arm_fpu.S
|
CMN_ASRCS += arm_fpu.S
|
||||||
|
CMN_CSRCS += arm_fpuconfig.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user