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arm_secure_irq: fix NVIC_IRQ_DBGMONITOR un-secure set failed

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NVIC_DEMCR.SDME is a read-only bit

Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
ligd
2022-06-09 12:13:05 +08:00
committed by Petro Karashchenko
parent 3db8c2b6a6
commit df365008b2
2 changed files with 7 additions and 3 deletions
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arch/arm/src/armv8-m/arm_secure_irq.c
+2 -3
View File
@@ -63,9 +63,8 @@ void up_secure_irq(int irq, bool secure)
break; break;
case NVIC_IRQ_DBGMONITOR: case NVIC_IRQ_DBGMONITOR:
regaddr = NVIC_DEMCR; regaddr = NVIC_DAUTHCTRL;
regbit = NVIC_DEMCR_SDME; regbit = NVIC_DAUTHCTRL_SPIDENSEL;
secure = !secure;
break; break;
default: default:
arch/arm/src/armv8-m/nvic.h
+5
View File
@@ -823,6 +823,11 @@
#define NVIC_DSCEMCR_CLR_MON_PEND (1 << 17) /* Bit 17: Clear monitor pend */ #define NVIC_DSCEMCR_CLR_MON_PEND (1 << 17) /* Bit 17: Clear monitor pend */
#define NVIC_DSCEMCR_CLR_MON_REQ (1 << 19) /* Bit 19: Clear monitor request */ #define NVIC_DSCEMCR_CLR_MON_REQ (1 << 19) /* Bit 19: Clear monitor request */
/* Debug Authentication Control Register (DAUTHCTRL) */
#define NVIC_DAUTHCTRL_SPIDENSEL (1 << 0) /* Bit 0: Secure invasive debug enable select */
#define NVIC_DAUTHCTRL_INTSPIDEN (1 << 1) /* Bit 1: Internal Secure invasive debug enable */
/* Floating-Point Context Control Register (FPCCR) */ /* Floating-Point Context Control Register (FPCCR) */
#define NVIC_FPCCR_LSPACT (1 << 0) /* Bit 0: Lazy state preservation active */ #define NVIC_FPCCR_LSPACT (1 << 0) /* Bit 0: Lazy state preservation active */