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arch/arm/src/s32k1xx/s32k1xx_clockconfig.c and related files: Fix confusion about who decrements the rster value. Some dividers may have a function range of 1..8 but the register value is 0..7. There were several places where values were getting decremented twice: Once by higher up logic and once by the register access logic. A such dividers were reviewed and, hopefully, all were fixed.

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This commit is contained in:
Gregory Nutt
2019-08-19 13:07:45 -06:00
parent 425a2d1b2c
commit df1294906d
5 changed files with 61 additions and 94 deletions
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boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
+9 -9
View File
@@ -126,17 +126,17 @@ const struct clock_configuration_s g_initial_clkconfig =
{
.rccr = /* RCCR - Run Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
.divslow = 2, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
},
.vccr = /* VCCR - VLPR Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_4, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 1, /* DIVBUS, range 1..16 */
.divcore = 2 /* DIVCORE, range 1..16 */
},
/* .altclk */
.initialize = true, /* Initialize */
@@ -147,7 +147,7 @@ const struct clock_configuration_s g_initial_clkconfig =
.clockout = /* Clock Out configuration. */
{
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
.divider = SIM_CLKOUT_DIV_BY_1, /* CLKOUTDIV */
.divider = 1, /* CLKOUTDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = false, /* CLKOUTEN */
},
boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
+13 -13
View File
@@ -138,24 +138,24 @@ const struct clock_configuration_s g_initial_clkconfig =
{
.rccr = /* RCCR - Run Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
.divslow = 2, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
},
.vccr = /* VCCR - VLPR Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_4, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 1, /* DIVBUS, range 1..16 */
.divcore = 2 /* DIVCORE, range 1..16 */
},
.hccr =
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_4, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
},
/* .altclk */
.initialize = true, /* Initialize */
@@ -166,7 +166,7 @@ const struct clock_configuration_s g_initial_clkconfig =
.clockout = /* Clock Out configuration. */
{
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
.divider = SIM_CLKOUT_DIV_BY_1, /* CLKOUTDIV */
.divider = 1, /* CLKOUTDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = false, /* CLKOUTEN */
},