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arch/arm/src/stm32/stm32_spi.c: TI Synchronous Serial Frame Format. The SPI macros on STM32 MCUs do support the Texas Instruments Synchronous Serial Frame Format protocol (TI protocol). Defined a new SPIDEV_MODETI and add support for it in stm32_spi.c.

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This commit is contained in:
Michael Jung
2019-08-25 09:07:09 -06:00
committed by Gregory Nutt
parent b395cde043
commit decd07725f
2 changed files with 36 additions and 2 deletions
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arch/arm/src/stm32/stm32_spi.c
+34 -1
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@@ -1095,7 +1095,8 @@ static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16_t setbits,
* *
************************************************************************************/ ************************************************************************************/
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_SPI_DMA) defined(CONFIG_STM32_SPI_DMA)
static void spi_modifycr2(FAR struct stm32_spidev_s *priv, uint16_t setbits, static void spi_modifycr2(FAR struct stm32_spidev_s *priv, uint16_t setbits,
uint16_t clrbits) uint16_t clrbits)
@@ -1311,6 +1312,13 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
clrbits = 0; clrbits = 0;
break; break;
#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */
case SPIDEV_MODETI:
setbits = 0;
clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
break;
#endif
default: default:
return; return;
} }
@@ -1319,6 +1327,31 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
spi_modifycr1(priv, setbits, clrbits); spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0); spi_modifycr1(priv, SPI_CR1_SPE, 0);
#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */
switch (mode)
{
case SPIDEV_MODE0:
case SPIDEV_MODE1:
case SPIDEV_MODE2:
case SPIDEV_MODE3:
setbits = 0;
clrbits = SPI_CR2_FRF;
break;
case SPIDEV_MODETI:
setbits = SPI_CR2_FRF;
clrbits = 0;
break;
default:
return;
}
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr2(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
#endif
/* Save the mode so that subsequent re-configurations will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
include/nuttx/spi/spi.h
+2 -1
View File
@@ -537,7 +537,8 @@ enum spi_mode_e
SPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */ SPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */
SPIDEV_MODE1, /* CPOL=0 CHPHA=1 */ SPIDEV_MODE1, /* CPOL=0 CHPHA=1 */
SPIDEV_MODE2, /* CPOL=1 CHPHA=0 */ SPIDEV_MODE2, /* CPOL=1 CHPHA=0 */
SPIDEV_MODE3 /* CPOL=1 CHPHA=1 */ SPIDEV_MODE3, /* CPOL=1 CHPHA=1 */
SPIDEV_MODETI, /* CPOL=0 CPHA=1 TI Synchronous Serial Frame Format */
}; };
#ifdef CONFIG_SPI_HWFEATURES #ifdef CONFIG_SPI_HWFEATURES