diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h index 93d241f328f..cf5cd52e563 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h @@ -132,7 +132,8 @@ #define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */ /* 0x40021400 - 0x40021fff: Reserved */ #define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */ -#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x4002203f: Flash memory I/F (Bank 0)*/ +#define STM32_FLASHIF1_BASE 0x40022040 /* 0x40022024 - 0x400223ff: Flash memory I/F (Bank 1)*/ #define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: CRC */ /* 0x40023400 - 0x40027fff: Reserved */ #define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h index be3dbaf590b..a8c720e98a0 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h @@ -133,7 +133,8 @@ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ #define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ #define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ -#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x4002203f: Flash memory I/F (Bank 0) */ +#define STM32_FLASHIF1_BASE 0x40022040 /* 0x40022000-0x400223ff: Flash memory I/F (Bank 1) */ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ #define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h index 8c85ff6af3d..dabceda3cec 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h @@ -122,7 +122,8 @@ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ #define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ -#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x4002203f: Flash memory I/F (Bank 0) */ +#define STM32_FLASHIF1_BASE 0x40022040 /* 0x40022000-0x400223ff: Flash memory I/F (Bank 1) */ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ #define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h index 10daaaae18a..c86ee530b83 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h @@ -133,7 +133,8 @@ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ #define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ #define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ -#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x4002203f: Flash memory I/F (Bank 0) */ +#define STM32_FLASHIF1_BASE 0x40022040 /* 0x40022000-0x400223ff: Flash memory I/F (Bank 1) */ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ #define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ diff --git a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c b/arch/arm/src/stm32/stm32f10xxf30xx_flash.c index a7c85b24002..521344afc47 100644 --- a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c +++ b/arch/arm/src/stm32/stm32f10xxf30xx_flash.c @@ -73,9 +73,15 @@ #define FLASH_OPTKEY2 0x4c5d6e7f #define FLASH_ERASEDVALUE 0xff -#if !defined(STM32_FLASH_DUAL_BANK) +#if defined(STM32_FLASH_DUAL_BANK) +/* Bank 0 is 512Kb; Bank 1 is up to 512Kb */ + +# define STM32_FLASH_BANK0_NPAGES (512 * 1024 / STM32_FLASH_PAGESIZE) +# define STM32_FLASH_BANK1_NPAGES (STM32_FLASH_NPAGES - STM32_FLASH_BANK0_NPAGES) +#else +/* Bank 0 is up to 512Kb; Bank 1 is not present */ + # define STM32_FLASH_BANK0_NPAGES STM32_FLASH_NPAGES -# define STM32_FLASH_BANK0_BASE STM32_FLASH_BASE #endif /************************************************************************************ @@ -140,9 +146,9 @@ static void flash_lock(uintptr_t base) void stm32_flash_unlock(void) { sem_lock(); - flash_unlock(STM32_FLASH_BANK0_BASE); + flash_unlock(STM32_FLASHIF_BASE); #if defined(STM32_FLASH_DUAL_BANK) - flash_unlock(STM32_FLASH_BANK1_BASE); + flash_unlock(STM32_FLASHIF1_BASE); #endif sem_unlock(); } @@ -150,9 +156,9 @@ void stm32_flash_unlock(void) void stm32_flash_lock(void) { sem_lock(); - flash_lock(STM32_FLASH_BANK0_BASE); + flash_lock(STM32_FLASHIF_BASE); #if defined(STM32_FLASH_DUAL_BANK) - flash_lock(STM32_FLASH_BANK1_BASE); + flash_lock(STM32_FLASHIF1_BASE); #endif sem_unlock(); } @@ -246,12 +252,12 @@ ssize_t up_progmem_eraseblock(size_t block) if (block >= STM32_FLASH_BANK0_NPAGES) { - base = STM32_FLASH_BANK1_BASE; + base = STM32_FLASHIF1_BASE; } else #endif { - base = STM32_FLASH_BANK0_BASE; + base = STM32_FLASHIF_BASE; } sem_lock(); @@ -306,12 +312,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) if (page >= STM32_FLASH_BANK0_NPAGES) { - base = STM32_FLASH_BANK1_BASE; + base = STM32_FLASHIF1_BASE; } else #endif { - base = STM32_FLASH_BANK0_BASE; + base = STM32_FLASHIF_BASE; } /* STM32 requires half-word access */