diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
index c50a992bc19..894200a9c61 100644
--- a/arch/arm/src/armv7-a/arm_gicv2.c
+++ b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -84,8 +84,8 @@ void arm_gic0_initialize(void)
 
   /* A processor in Secure State sets:
    *
-   * 1. Which interrupts are non-secure (ICDISR).
-   *    REVISIT: Which bit state corresponds to secure?
+   * 1. Which interrupts are non-secure (ICDISR).  All set to zero (group
+   *    0).
    * 2. Trigger mode of the SPI (ICDICFR). All fields set to 11->Edge
    *    sensitive.
    * 3. Innterrupt Clear-Enable (ICDICER)
@@ -108,7 +108,7 @@ void arm_gic0_initialize(void)
 
   /* Registers with 8-bits per interrupt */
 
-  for (irq = GIC_IRQ_SPI; irq < nlines; irq += 8)
+  for (irq = GIC_IRQ_SPI; irq < nlines; irq += 4)
     {
       putreg32(0x80808080, GIC_ICDIPR(irq));   /* SPI priority */
       putreg32(0x01010101, GIC_ICDIPTR(irq));  /* SPI on CPU0 */
diff --git a/arch/arm/src/armv7-a/arm_gicv2_dump.c b/arch/arm/src/armv7-a/arm_gicv2_dump.c
index 1791540fe50..9e4dfa340f1 100644
--- a/arch/arm/src/armv7-a/arm_gicv2_dump.c
+++ b/arch/arm/src/armv7-a/arm_gicv2_dump.c
@@ -227,9 +227,9 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
 static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
 {
   lowsyslog(LOG_INFO, "  Distributor Registers:\n");
-  lowsyslog(LOG_INFO, "       DCR: %08x   ICTR: %08x   IIDR: %08x  PPISR: %08x\n",
+  lowsyslog(LOG_INFO, "       DCR: %08x   ICTR: %08x   IIDR: %08x\n",
         getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
-        getreg32(GIC_ICDIIDR), getreg32(GIC_ICDPPISR));
+        getreg32(GIC_ICDIIDR));
 
   if (all)
     {
@@ -240,7 +240,7 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
       arm_gic_dump4("IPR", GIC_ICDIPR(0), nlines);
       arm_gic_dump4("IPTR", GIC_ICDIPTR(0), nlines);
       arm_gic_dump16("ICFR", GIC_ICDICFR(0), nlines);
-      arm_gic_dump32("SPISR", GIC_ICDSPISR(0), nlines);
+      arm_gic_dump32("PPSIR/SPISR", GIC_ICDPPISR, nlines);
       arm_gic_dump32("NSACR", GIC_ICDNSACR(0), nlines);
       arm_gic_dump8("SCPR/SSPR", GIC_ICDSCPR(0), nlines);
     }
diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h
index 153f74dd90d..45f8a606cbe 100644
--- a/arch/arm/src/armv7-a/gic.h
+++ b/arch/arm/src/armv7-a/gic.h
@@ -184,12 +184,10 @@
 
 /* 0x0d00-0x0dfc: Implementation defined */
 /* PPI Status Register: 0x0d00 */
-
-#define GIC_ICDPPISR_OFFSET        0x0d00    /* PPI Status Register */
-
 /* SPI Status Registers: 0x0d04-0x0d1c */
 
-#define GIC_ICDSPISR_OFFSET(n)     (0x0d04 + GIC_OFFSET32(n))
+#define GIC_ICDPPISR_OFFSET        0x0d00    /* PPI Status Register */
+#define GIC_ICDSPISR_OFFSET(n)     (0x0d00 + GIC_OFFSET32(n))
 
 /* 0x0d80-0x0dfc: Reserved */
 /* Non-secure Access Control Registers, optional: 00xe00-0x0efc */
@@ -290,7 +288,7 @@
 #define GIC_ICCICRU_FIQBYPDISGRP1  (1 << 5)  /* Bit 5:  FIQ disabled for CPU Group 1*/
 #define GIC_ICCICRU_IRQBYPDISGRP1  (1 << 6)  /* Bit 6:  IRQ disabled for CPU Group 1*/
                                              /* Bits 7-8: Reserved */
-#define GIC_ICCICRU_EOIMODENS      (1 << 9)  /* Bit 6:  Control EIOIR access (non-secure) */
+#define GIC_ICCICRU_EOIMODENS      (1 << 9)  /* Bit 9:  Control EIOIR access (non-secure) */
                                              /* Bits 10-31: Reserved */
 /* CPU Interface Control Register -- with security extensions, secure copy */