mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 00:14:22 +08:00
Completes coding of the PWM module
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4200 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -96,19 +96,13 @@
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#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
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#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
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#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
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#ifdef CONFIG_STM32_STM32F10XX
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# define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
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#endif
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#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
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#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
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#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
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#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
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#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
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#ifdef CONFIG_STM32_STM32F10XX
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# define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit) */
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#endif
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#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit) */
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#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
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#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
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@@ -130,16 +124,12 @@
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# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
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# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
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# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
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# ifdef CONFIG_STM32_STM32F10XX
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# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
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# endif
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# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
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# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
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# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
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# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
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# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
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# ifdef CONFIG_STM32_STM32F10XX
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# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
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# endif
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# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
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# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
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# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
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#endif
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@@ -157,16 +147,12 @@
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# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
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# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
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# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
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# ifdef CONFIG_STM32_STM32F10XX
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# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
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# endif
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# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
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# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
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# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
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# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
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# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
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# ifdef CONFIG_STM32_STM32F10XX
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# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
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# endif
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# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
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# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
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# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
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#endif
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@@ -402,29 +388,23 @@
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/* Control register 2 */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */
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# define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */
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#endif
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#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */
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#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */
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#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */
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#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
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#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT)
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# define ATIM_CR2_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
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# define ATIM_CR2_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
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# define ATIM_CR2_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
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# define ATIM_CR2_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
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#define ATIM_CR2_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
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#define ATIM_CR2_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
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#define ATIM_CR2_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
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#define ATIM_CR2_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
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#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
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# define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
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# define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
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# define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
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# define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
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# define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
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# define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
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#endif
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#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
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#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
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#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
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#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
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#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
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#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
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#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
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/* Slave mode control register */
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@@ -667,27 +647,15 @@
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#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
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#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */
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#endif
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#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */
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#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output Polarity */
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#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
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#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */
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#endif
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#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */
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#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output Polarity */
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#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
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#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
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#endif
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#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
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#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output Polarity */
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#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
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#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
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@@ -698,29 +666,25 @@
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/* Repetition counter register */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_RCR_REP_SHIFT (0) /* Bits 7-0: Repetition Counter Value */
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# define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
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#endif
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#define ATIM_RCR_REP_SHIFT (0) /* Bits 7-0: Repetition Counter Value */
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#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
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/* Break and dead-time register */
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#ifdef CONFIG_STM32_STM32F10XX
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# define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
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# define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT)
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# define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
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# define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT)
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# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
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# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
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# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
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# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
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# define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
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# define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
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# define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
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# define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
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# define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
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# define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
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#endif
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#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
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#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT)
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#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
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#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT)
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# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
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# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
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# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
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# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
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#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
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#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
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#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
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#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
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#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
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#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
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/* DMA control register */
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@@ -843,7 +807,7 @@
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#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag (TIM2-5 only) */
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#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag (TIM2-5 only) */
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/* Event generation register (TIM2-5 and TIM9-14) (TIM2-5 and TIM9-14) */
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/* Event generation register (TIM2-5 and TIM9-14) */
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#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
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#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */
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+548
-69
File diff suppressed because it is too large
Load Diff
@@ -49,7 +49,6 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/stm32_tim.h"
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/************************************************************************************
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* Pre-processor Definitions
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@@ -76,12 +75,6 @@
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#ifndef CONFIG_STM32_TIM5
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# undef CONFIG_STM32_TIM5_PWM
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#endif
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#ifndef CONFIG_STM32_TIM6
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# undef CONFIG_STM32_TIM6_PWM
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#endif
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#ifndef CONFIG_STM32_TIM7
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# undef CONFIG_STM32_TIM7_PWM
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#endif
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#ifndef CONFIG_STM32_TIM8
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# undef CONFIG_STM32_TIM8_PWM
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#endif
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@@ -104,6 +97,228 @@
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# undef CONFIG_STM32_TIM14_PWM
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#endif
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/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
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#undef CONFIG_STM32_TIM6_PWM
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#undef CONFIG_STM32_TIM7_PWM
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/* Check if PWM support for any channel is enabled. */
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#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
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defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \
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defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
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defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
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defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
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defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM)
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#include <arch/board/board.h>
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#include "chip/stm32_tim.h"
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/* For each timer that is enabled for PWM usage, we need the following additional
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* configuration settings:
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*
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* CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
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* PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the case
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* where there are multiple pin selections, the correct setting must be provided
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* in the arch/board/board.h file.
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*
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* NOTE: The STM32 timers are each capable of generating different signals on
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* each of the four channels with different duty cycles. That capability is
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* not supported by this driver: Only one output channel per timer.
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*/
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#ifdef CONFIG_STM32_TIM1_PWM
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# if !defined(CONFIG_STM32_TIM1_CHANNEL)
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# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM1_CHANNEL == 1
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# define PWM_TIM1_PINCFG GPIO_TIM1_CH1
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# elif CONFIG_STM32_TIM1_CHANNEL == 2
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# define PWM_TIM1_PINCFG GPIO_TIM1_CH2
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# elif CONFIG_STM32_TIM1_CHANNEL == 3
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# define PWM_TIM1_PINCFG GPIO_TIM1_CH3
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# elif CONFIG_STM32_TIM1_CHANNEL == 4
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# define PWM_TIM1_PINCFG GPIO_TIM1_CH4
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# else
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# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
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# endif
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#endif
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#ifdef CONFIG_STM32_TIM2_PWM
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# if !defined(CONFIG_STM32_TIM2_CHANNEL)
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# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM2_CHANNEL == 1
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# define PWM_TIM2_PINCFG GPIO_TIM2_CH1
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# elif CONFIG_STM32_TIM2_CHANNEL == 2
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# define PWM_TIM2_PINCFG GPIO_TIM2_CH2
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# elif CONFIG_STM32_TIM2_CHANNEL == 3
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# define PWM_TIM2_PINCFG GPIO_TIM2_CH3
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# elif CONFIG_STM32_TIM2_CHANNEL == 4
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# define PWM_TIM2_PINCFG GPIO_TIM2_CH4
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# else
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# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
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# endif
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#endif
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#ifdef CONFIG_STM32_TIM3_PWM
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# if !defined(CONFIG_STM32_TIM3_CHANNEL)
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# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM3_CHANNEL == 1
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# define PWM_TIM3_PINCFG GPIO_TIM3_CH1
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# elif CONFIG_STM32_TIM3_CHANNEL == 2
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# define PWM_TIM3_PINCFG GPIO_TIM3_CH2
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# elif CONFIG_STM32_TIM3_CHANNEL == 3
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# define PWM_TIM3_PINCFG GPIO_TIM3_CH3
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# elif CONFIG_STM32_TIM3_CHANNEL == 4
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# define PWM_TIM3_PINCFG GPIO_TIM3_CH4
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# else
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# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
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# endif
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#endif
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#ifdef CONFIG_STM32_TIM4_PWM
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# if !defined(CONFIG_STM32_TIM4_CHANNEL)
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# error "CONFIG_STM32_TIM4_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM4_CHANNEL == 1
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# define PWM_TIM4_PINCFG GPIO_TIM4_CH1
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# elif CONFIG_STM32_TIM4_CHANNEL == 2
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# define PWM_TIM4_PINCFG GPIO_TIM4_CH2
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# elif CONFIG_STM32_TIM4_CHANNEL == 3
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# define PWM_TIM4_PINCFG GPIO_TIM4_CH3
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# elif CONFIG_STM32_TIM4_CHANNEL == 4
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# define PWM_TIM4_PINCFG GPIO_TIM4_CH4
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# else
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# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL"
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# endif
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#endif
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#ifdef CONFIG_STM32_TIM5_PWM
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# if !defined(CONFIG_STM32_TIM5_CHANNEL)
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# error "CONFIG_STM32_TIM5_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM5_CHANNEL == 1
|
||||
# define PWM_TIM5_PINCFG GPIO_TIM5_CH1
|
||||
# elif CONFIG_STM32_TIM5_CHANNEL == 2
|
||||
# define PWM_TIM5_PINCFG GPIO_TIM5_CH2
|
||||
# elif CONFIG_STM32_TIM5_CHANNEL == 3
|
||||
# define PWM_TIM5_PINCFG GPIO_TIM5_CH3
|
||||
# elif CONFIG_STM32_TIM5_CHANNEL == 4
|
||||
# define PWM_TIM5_PINCFG GPIO_TIM5_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM8_PWM
|
||||
# if !defined(CONFIG_STM32_TIM8_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM8_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM8_CHANNEL == 1
|
||||
# define PWM_TIM8_PINCFG GPIO_TIM8_CH1
|
||||
# elif CONFIG_STM32_TIM8_CHANNEL == 2
|
||||
# define PWM_TIM8_PINCFG GPIO_TIM8_CH2
|
||||
# elif CONFIG_STM32_TIM8_CHANNEL == 3
|
||||
# define PWM_TIM8_PINCFG GPIO_TIM8_CH3
|
||||
# elif CONFIG_STM32_TIM8_CHANNEL == 4
|
||||
# define PWM_TIM8_PINCFG GPIO_TIM8_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM9_PWM
|
||||
# if !defined(CONFIG_STM32_TIM9_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM9_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM9_CHANNEL == 1
|
||||
# define PWM_TIM9_PINCFG GPIO_TIM9_CH1
|
||||
# elif CONFIG_STM32_TIM9_CHANNEL == 2
|
||||
# define PWM_TIM9_PINCFG GPIO_TIM9_CH2
|
||||
# elif CONFIG_STM32_TIM9_CHANNEL == 3
|
||||
# define PWM_TIM9_PINCFG GPIO_TIM9_CH3
|
||||
# elif CONFIG_STM32_TIM9_CHANNEL == 4
|
||||
# define PWM_TIM9_PINCFG GPIO_TIM9_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM10_PWM
|
||||
# if !defined(CONFIG_STM32_TIM10_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM10_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM10_CHANNEL == 1
|
||||
# define PWM_TIM10_PINCFG GPIO_TIM10_CH1
|
||||
# elif CONFIG_STM32_TIM10_CHANNEL == 2
|
||||
# define PWM_TIM10_PINCFG GPIO_TIM10_CH2
|
||||
# elif CONFIG_STM32_TIM10_CHANNEL == 3
|
||||
# define PWM_TIM10_PINCFG GPIO_TIM10_CH3
|
||||
# elif CONFIG_STM32_TIM10_CHANNEL == 4
|
||||
# define PWM_TIM10_PINCFG GPIO_TIM10_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM11_PWM
|
||||
# if !defined(CONFIG_STM32_TIM11_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM11_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM11_CHANNEL == 1
|
||||
# define PWM_TIM11_PINCFG GPIO_TIM11_CH1
|
||||
# elif CONFIG_STM32_TIM11_CHANNEL == 2
|
||||
# define PWM_TIM11_PINCFG GPIO_TIM11_CH2
|
||||
# elif CONFIG_STM32_TIM11_CHANNEL == 3
|
||||
# define PWM_TIM11_PINCFG GPIO_TIM11_CH3
|
||||
# elif CONFIG_STM32_TIM11_CHANNEL == 4
|
||||
# define PWM_TIM11_PINCFG GPIO_TIM11_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM12_PWM
|
||||
# if !defined(CONFIG_STM32_TIM12_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM12_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM12_CHANNEL == 1
|
||||
# define PWM_TIM12_PINCFG GPIO_TIM12_CH1
|
||||
# elif CONFIG_STM32_TIM12_CHANNEL == 2
|
||||
# define PWM_TIM12_PINCFG GPIO_TIM12_CH2
|
||||
# elif CONFIG_STM32_TIM12_CHANNEL == 3
|
||||
# define PWM_TIM12_PINCFG GPIO_TIM12_CH3
|
||||
# elif CONFIG_STM32_TIM12_CHANNEL == 4
|
||||
# define PWM_TIM12_PINCFG GPIO_TIM12_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM13_PWM
|
||||
# if !defined(CONFIG_STM32_TIM13_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM13_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM13_CHANNEL == 1
|
||||
# define PWM_TIM13_PINCFG GPIO_TIM13_CH1
|
||||
# elif CONFIG_STM32_TIM13_CHANNEL == 2
|
||||
# define PWM_TIM13_PINCFG GPIO_TIM13_CH2
|
||||
# elif CONFIG_STM32_TIM13_CHANNEL == 3
|
||||
# define PWM_TIM13_PINCFG GPIO_TIM13_CH3
|
||||
# elif CONFIG_STM32_TIM13_CHANNEL == 4
|
||||
# define PWM_TIM13_PINCFG GPIO_TIM13_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM14_PWM)
|
||||
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
|
||||
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
|
||||
# elif CONFIG_STM32_TIM14_CHANNEL == 1
|
||||
# define PWM_TIM14_PINCFG GPIO_TIM14_CH1
|
||||
# elif CONFIG_STM32_TIM14_CHANNEL == 2
|
||||
# define PWM_TIM14_PINCFG GPIO_TIM14_CH2
|
||||
# elif CONFIG_STM32_TIM14_CHANNEL == 3
|
||||
# define PWM_TIM14_PINCFG GPIO_TIM14_CH3
|
||||
# elif CONFIG_STM32_TIM14_CHANNEL == 4
|
||||
# define PWM_TIM14_PINCFG GPIO_TIM14_CH4
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
@@ -151,4 +366,5 @@ EXTERN FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_STM32_TIMx_PWM */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */
|
||||
|
||||
@@ -162,7 +162,7 @@ static void rtc_dumpregs(FAR const char *msg)
|
||||
rtclldbg(" BK0: %08x\n", getreg32(STM32_RTC_BK0R));
|
||||
}
|
||||
#else
|
||||
# define tc_dumpregs(msg)
|
||||
# define rtc_dumpregs(msg)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -492,8 +492,6 @@ STM3210E-EVAL-specific Configuration Options
|
||||
CONFIG_STM32_TIM3_PWM
|
||||
CONFIG_STM32_TIM4_PWM
|
||||
CONFIG_STM32_TIM5_PWM
|
||||
CONFIG_STM32_TIM6_PWM
|
||||
CONFIG_STM32_TIM7_PWM
|
||||
CONFIG_STM32_TIM8_PWM
|
||||
|
||||
CONFIG_STM32_TIM1_ADC
|
||||
@@ -514,7 +512,16 @@ STM3210E-EVAL-specific Configuration Options
|
||||
CONFIG_STM32_TIM7_DAC
|
||||
CONFIG_STM32_TIM8_DAC
|
||||
|
||||
Alternate pin mappings (should not be used with the STM3210E-EVAL board):
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings:
|
||||
|
||||
CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
|
||||
NOTE: The STM32 timers are each capable of generating different signals on
|
||||
each of the four channels with different duty cycles. That capability is
|
||||
not supported by this driver: Only one output channel per timer.
|
||||
|
||||
Alternate pin mappings (should not be used with the STM3210E-EVAL board):
|
||||
|
||||
CONFIG_STM32_TIM1_FULL_REMAP
|
||||
CONFIG_STM32_TIM1_PARTIAL_REMAP
|
||||
|
||||
@@ -371,8 +371,6 @@ STM3240G-EVAL-specific Configuration Options
|
||||
CONFIG_STM32_TIM3_PWM
|
||||
CONFIG_STM32_TIM4_PWM
|
||||
CONFIG_STM32_TIM5_PWM
|
||||
CONFIG_STM32_TIM6_PWM
|
||||
CONFIG_STM32_TIM7_PWM
|
||||
CONFIG_STM32_TIM8_PWM
|
||||
CONFIG_STM32_TIM9_PWM
|
||||
CONFIG_STM32_TIM10_PWM
|
||||
@@ -399,6 +397,15 @@ STM3240G-EVAL-specific Configuration Options
|
||||
CONFIG_STM32_TIM7_DAC
|
||||
CONFIG_STM32_TIM8_DAC
|
||||
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings:
|
||||
|
||||
CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
|
||||
NOTE: The STM32 timers are each capable of generating different signals on
|
||||
each of the four channels with different duty cycles. That capability is
|
||||
not supported by this driver: Only one output channel per timer.
|
||||
|
||||
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
|
||||
|
||||
CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
|
||||
+3
-3
@@ -115,7 +115,7 @@
|
||||
struct pwm_info_s
|
||||
{
|
||||
uint32_t frequency; /* Frequency of the pulse train */
|
||||
b16_t duty; /* Duty of the pulse train, "1" to "0" duration */
|
||||
ub16_t duty; /* Duty of the pulse train, "1" to "0" duration */
|
||||
};
|
||||
|
||||
/* This type is used to return pulse counts */
|
||||
@@ -211,7 +211,7 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* "Upper-Half" ADC Driver Interfaces
|
||||
* "Upper-Half" PWM Driver Interfaces
|
||||
****************************************************************************/
|
||||
/****************************************************************************
|
||||
* Name: pwm_register
|
||||
@@ -241,7 +241,7 @@ extern "C" {
|
||||
int pwm_register(FAR const char *path, FAR struct pwm_lowerhalf_s *dev);
|
||||
|
||||
/****************************************************************************
|
||||
* Platform-Independent "Lower-Half" ADC Driver Interfaces
|
||||
* Platform-Independent "Lower-Half" PWM Driver Interfaces
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
|
||||
Reference in New Issue
Block a user