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Fix QEMU timer interrupts

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3387 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-03-16 17:17:58 +00:00
parent e58d1dcbde
commit dcd258ba4a
3 changed files with 17 additions and 9 deletions
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arch/x86/include/i486/arch.h
+3 -3
View File
@@ -121,7 +121,7 @@
#define PIC2_OCW2 0xa0 #define PIC2_OCW2 0xa0
# define PIC_OCW2_ACT_SHIFT (0) # define PIC_OCW2_ACT_SHIFT (0)
# define PIC_OCW2_ACT_SHIFT (7 << PIC_OCW2_ACT_SHIFT) # define PIC_OCW2_ACT_MASK (7 << PIC_OCW2_ACT_SHIFT)
# define PIC1_OCW2_ACT_IRQ0 (0 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 0 */ # define PIC1_OCW2_ACT_IRQ0 (0 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 0 */
# define PIC1_OCW2_ACT_IRQ1 (1 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 1 */ # define PIC1_OCW2_ACT_IRQ1 (1 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 1 */
# define PIC1_OCW2_ACT_IRQ2 (2 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 2 */ # define PIC1_OCW2_ACT_IRQ2 (2 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 2 */
@@ -141,7 +141,7 @@
# define PIC2_OCW2_ACT_IRQ15 (7 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 15 */ # define PIC2_OCW2_ACT_IRQ15 (7 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 15 */
# define PIC_OCW2_EOI_SHIFT (5) # define PIC_OCW2_EOI_SHIFT (5)
# define PIC_OCW2_EOI_SHIFT (7 << PIC_OCW2_EOI_SHIFT) # define PIC_OCW2_EOI_MASK (7 << PIC_OCW2_EOI_SHIFT)
# define PIC_OCW2_EOI_AUTO (0 << PIC_OCW2_EOI_SHIFT) /* Rotate in Auto EOI Mode (Clear) */ # define PIC_OCW2_EOI_AUTO (0 << PIC_OCW2_EOI_SHIFT) /* Rotate in Auto EOI Mode (Clear) */
# define PIC_OCW2_EOI_NONSPEC (1 << PIC_OCW2_EOI_SHIFT) /* Non Specific EOI */ # define PIC_OCW2_EOI_NONSPEC (1 << PIC_OCW2_EOI_SHIFT) /* Non Specific EOI */
# define PIC_OCW2_EOI_SPEC (3 << PIC_OCW2_EOI_SHIFT) /* Specific EOI */ # define PIC_OCW2_EOI_SPEC (3 << PIC_OCW2_EOI_SHIFT) /* Specific EOI */
@@ -171,7 +171,7 @@
# define PIC_OCW3_POLLCMD (1 << 2) /* Poll command */ # define PIC_OCW3_POLLCMD (1 << 2) /* Poll command */
# define PIC_OCW3_ONE (1 << 3) /* Must be set to 1 */ # define PIC_OCW3_ONE (1 << 3) /* Must be set to 1 */
# define PIC_OCW3_SM_SHIFT (5) # define PIC_OCW3_SM_SHIFT (5)
# define PIC_OCW3_SM_SHIFT (3 << PIC_OCW3_SM_SHIFT) # define PIC_OCW3_SM_MASK (3 << PIC_OCW3_SM_SHIFT)
# define PIC_OCW3_RSM (2 << PIC_OCW3_SM_SHIFT) /* Reset Special Mask */ # define PIC_OCW3_RSM (2 << PIC_OCW3_SM_SHIFT) /* Reset Special Mask */
# define PIC_OCW3_SSM (3 << PIC_OCW3_SM_SHIFT) /* Set Special Mask */ # define PIC_OCW3_SSM (3 << PIC_OCW3_SM_SHIFT) /* Set Special Mask */
arch/x86/include/i486/irq.h
+11 -3
View File
@@ -135,9 +135,17 @@ static inline irqstate_t irqflags()
return flags; return flags;
} }
/* Get a sample of the FLAGS register, determine if interrupts are disabled */ /* Get a sample of the FLAGS register, determine if interrupts are disabled.
* If the X86_FLAGS_IF is cleared by cli, then interrupts are disabled. If
* if the X86_FLAGS_IF is set by sti, then interrupts are enable.
*/
static inline bool irqdisabled(irqstate_t flags) static inline bool irqdisabled(irqstate_t flags)
{
return ((flags & X86_FLAGS_IF) == 0);
}
static inline bool irqenabled(irqstate_t flags)
{ {
return ((flags & X86_FLAGS_IF) != 0); return ((flags & X86_FLAGS_IF) != 0);
} }
@@ -169,9 +177,9 @@ static inline irqstate_t irqsave(void)
static inline void irqrestore(irqstate_t flags) static inline void irqrestore(irqstate_t flags)
{ {
if (irqdisabled(flags)) if (irqenabled(flags))
{ {
irqdisable(); irqenable();
} }
} }
arch/x86/src/qemu/qemu_handlers.c
+3 -3
View File
@@ -178,16 +178,16 @@ uint32_t *irq_handler(uint32_t *regs)
* involved the slave. * involved the slave.
*/ */
if (irq >= 40) if (irq >= IRQ8)
{ {
/* Send reset signal to slave */ /* Send reset signal to slave */
idt_outb(0x20, 0xa0); idt_outb(PIC_OCW2_EOI_NONSPEC, PIC2_OCW2);
} }
/* Send reset signal to master */ /* Send reset signal to master */
idt_outb(0x20, 0x20); idt_outb(PIC_OCW2_EOI_NONSPEC, PIC1_OCW2);
/* Dispatch the interrupt */ /* Dispatch the interrupt */