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SAMV71: Add GPIO library support

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This commit is contained in:
Gregory Nutt
2015-03-08 19:12:30 -06:00
parent ed0fa0358c
commit dbb972b2f7
6 changed files with 663 additions and 38 deletions
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arch/arm/src/samv7/Make.defs
+4 -4
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@@ -38,7 +38,7 @@
HEAD_ASRC =
# Common ARM and Cortex-M3 files
# Common ARM and Cortex-M7 files
CMN_UASRCS =
CMN_UCSRCS =
@@ -88,13 +88,13 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
# Required SAM3/4 files
# Required SAMV7 files
CHIP_ASRCS =
CHIP_CSRCS = sam_start.c sam_clockconfig.c sam_irq.c sam_allocateheap.c
CHIP_CSRCS += sam_lowputc.c sam_serial.c
CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_gpio.c
# Configuration-dependent SAM3/4 files
# Configuration-dependent SAMV7 files
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
arch/arm/src/samv7/chip/sam_pio.h
+12 -2
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@@ -51,7 +51,17 @@
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* Configuration ************************************************************************/
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
#undef GPIO_HAVE_DELAYR
#define GPIO_HAVE_DRIVER 1
#define GPIO_HAVE_KEYPAD 1
/* Misc Helper Definitions **************************************************************/
#define PIOA (0)
#define PIOB (1)
#define PIOC (2)
@@ -508,7 +518,7 @@
#define PIO_KRCR_NBC_SHIFT (0) /* Bis 0-2: Number of Rows of the Keypad Matrix */
#define PIO_KRCR_NBC_MASK (7 << PIO_KRCR_NBC_SHIFT)
# define PIO_KRCR_NBC_MASK ((uint32_t)(n) << PIO_KRCR_NBC_SHIFT)
# define PIO_KRCR_NBC(n) ((uint32_t)(n) << PIO_KRCR_NBC_SHIFT)
#define PIO_KRCR_NBR_SHIFT (8) /* Bis 8-10: Number of Columns of the Keypad Matrix */
#define PIO_KRCR_NBR_MASK (7 << PIO_KRCR_NBR_SHIFT)
# define PIO_KRCR_NBR(n) ((uint32_t)(n) << PIO_KRCR_NBR_SHIFT)
arch/arm/src/samv7/chip/samv71_pinmap.h
+2 -2
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@@ -226,8 +226,8 @@
/* Programmable Clock Output */
#define GPIO_PCK0_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6)
#define GPIO_PCK0_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
#define GPIO_PCK0_2 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12)
#define GPIO_PCK0_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
#define GPIO_PCK1_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17)
#define GPIO_PCK1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21)
#define GPIO_PCK2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18)
@@ -308,7 +308,7 @@
#define GPIO_PWMC1_L2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN4)
#define GPIO_PWMC1_L2_2 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
#define GPIO_PWMC1_L3_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5)
#define GPIO_PWMC1_L3_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)
#define GPIO_PWMC1_L3_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)
/* Quad IO SPI (QSPI) */
arch/arm/src/samv7/sam_gpio.c
+575
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File diff suppressed because it is too large Load Diff
arch/arm/src/samv7/sam_gpio.h
+66 -26
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@@ -49,15 +49,6 @@
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
#undef GPIO_HAVE_DELAYR 1
#define GPIO_HAVE_DRIVER 1
#define GPIO_HAVE_KEYPAD 1
/* Bit-encoded input to sam_configgpio() ********************************************/
/* 32-bit Encoding:
@@ -67,7 +58,7 @@
/* Input/Output mode:
*
* .... .... MMM. .... .... .... .... ....
* .... .... MMM. .... .... .... .... ....
*/
#define GPIO_MODE_SHIFT (21) /* Bits 21-23: GPIO mode */
@@ -127,8 +118,9 @@
* .... .... .... .... .... D... .... ....
*/
#define GPIO_OUTPUT_SET (1 << 11) /* Bit 11: Initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
#define GPIO_OUTPUT_DRIVE (1 << 11) /* Bit 11: Initial value of output */
# define GPIO_OUTPUT_HIGH_DRIVE (1 << 11)
#define GPIO_OUTPUT_LOW_DRIVE (0)
/* This identifies the GPIO port:
*
@@ -187,24 +179,12 @@
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_GPIO
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
@@ -218,6 +198,66 @@ extern "C"
#define EXTERN extern
#endif
EXTERN const uintptr_t g_portchar[SAMV7_NPIO];
/************************************************************************************
* Inline Functions
************************************************************************************/
/****************************************************************************
* Name: sam_gpio_base
*
* Description:
* Return the base address of the GPIO register set
*
****************************************************************************/
static inline uintptr_t sam_gpio_base(gpio_pinset_t cfgset)
{
int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
DEBUGASSERT(port <SAMV7_NPIO);
return g_portchar[port];
}
/****************************************************************************
* Name: sam_gpio_port
*
* Description:
* Return the PIO port number
*
****************************************************************************/
static inline int sam_gpio_port(gpio_pinset_t cfgset)
{
return (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
}
/****************************************************************************
* Name: sam_gpio_pin
*
* Description:
* Return the PIO pin number
*
****************************************************************************/
static inline int sam_gpio_pin(gpio_pinset_t cfgset)
{
return (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
}
/****************************************************************************
* Name: sam_gpio_pinmask
*
* Description:
* Return the PIO pin bit maskt
*
****************************************************************************/
static inline int sam_gpio_pinmask(gpio_pinset_t cfgset)
{
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
arch/arm/src/samv7/sam_serial.c
+4 -4
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@@ -871,8 +871,8 @@ static int sam_setup(struct uart_dev_s *dev)
*/
divb3 = ((FAST_USART_CLOCK + (priv->baud << 3)) << 3) / (priv->baud << 4);
intpart = (divb3 >> 3);
fracpart = (divb3 & 7)
intpart = divb3 >> 3;
fracpart = divb3 & 7;
/* Retain the fast MR peripheral clock UNLESS unless using that clock
* would result in an excessively large divider.
@@ -885,8 +885,8 @@ static int sam_setup(struct uart_dev_s *dev)
/* Use the divided USART clock */
divb3 = ((FAST_USART_CLOCK + (priv->baud << 3)) << 3) / (priv->baud << 4);
intpart = (divb3 >> 3);
fracpart = (divb3 & 7)
intpart = divb3 >> 3;
fracpart = divb3 & 7;
/* Re-select the clock source */