diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h
index 814e5b8a1e1..43ae6a0bbcc 100644
--- a/arch/arm/src/armv7-a/gic.h
+++ b/arch/arm/src/armv7-a/gic.h
@@ -9,6 +9,9 @@
  *   Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
  *   0407I (ID091612).
  *
+ *   Includes some removed registers from the r2p2 version as well. ARM DDI
+ *   0407F (ID050110)
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -231,7 +234,7 @@
 #define GIC_ICCPMR_MASK            (15 << GIC_ICCPMR_SHIFT)
 #  define GIC_ICCPMR_VALUE(n)      ((uint32_t)(n) << GIC_ICCPMR_SHIFT)
                                              /* Bits 8-31: Reserved */
-/* Binary point Register */
+/* Binary point Register and liased Non-secure Binary Point Register */
 
 #define GIC_ICCBPR_SHIFT           (0)       /* Bits 0-2: Binary point */
 #define GIC_ICCBPR_MASK            (7 << GIC_ICCBPR_SHIFT)
@@ -276,10 +279,6 @@
 #  define GIC_ICCHPIR_CPUSRC(n)    ((uint32_t)(n) << GIC_ICCHPIR_CPUSRC_SHIFT)
                                              /* Bits 13-31: Reserved */
 
-/* Aliased Non-secure Binary Point Register */
-
-#define GIC_ICCABPR_
-
 /* CPU Interface Implementer ID Register */
 
 #define GIC_ICCIDR_IMPL_SHIFT      (0)       /* Bits 0-11:  Implementer */
diff --git a/arch/arm/src/armv7-a/mpcore.h b/arch/arm/src/armv7-a/mpcore.h
index 060fde7362d..3877e46021d 100644
--- a/arch/arm/src/armv7-a/mpcore.h
+++ b/arch/arm/src/armv7-a/mpcore.h
@@ -76,4 +76,3 @@
 #define MPCORE_ICD_VBASE   (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
 
 #endif /* __ARCH_ARM_SRC_ARMV7_A_MPCORE_H */
-