diff --git a/arch/arm/src/sama5/chip/sam_sfr.h b/arch/arm/src/sama5/chip/sam_sfr.h index ca6558e38c2..3359d5921b2 100644 --- a/arch/arm/src/sama5/chip/sam_sfr.h +++ b/arch/arm/src/sama5/chip/sam_sfr.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sama5/chip/sam_sfr.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -57,8 +57,19 @@ #define SAM_SFR_SECURE_OFFSET 0x0028 /* Security Configuration Register */ /* 0x002c: Reserved */ #define SAM_SFR_UTMICKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */ + +#ifdef ATSAMA5D4 +# define SAM_SFR_UTMIHSTRIM_OFFSET 0x0034 /* UTMI High Speed Trimming Register */ +# define SAM_SFR_UTMIFSTRIM_OFFSET 0x0038 /* UTMI Full Speed Trimming Register */ +# define SAM_SFR_UTMISWAP_OFFSET 0x003c /* UTMI DP/DM Pin Swapping Register */ +#endif + #define SAM_SFR_EBICFG_OFFSET 0x0040 /* EBI Configuration Register */ /* 0x0044-0x3ffc: Reserved */ +#ifdef ATSAMA5D4 +# define SAM_SFR_SN0_OFFSET 0x004c /* Serial Number 0 Register */ +# define SAM_SFR_SN1_OFFSET 0x0050 /* Serial Number 1 Register */ +#endif /* SFR Register Addresses ***********************************************************/ @@ -67,13 +78,28 @@ #define SAM_SFR_OHCIISR (SAM_SFR_VBASE+SAM_SFR_OHCIISR_OFFSET) #define SAM_SFR_SECURE (SAM_SFR_VBASE+SAM_SFR_SECURE_OFFSET) #define SAM_SFR_UTMICKTRIM (SAM_SFR_VBASE+SAM_SFR_UTMICKTRIM_OFFSET) + +#ifdef ATSAMA5D4 +# define SAM_SFR_UTMIHSTRIM (SAM_SFR_VBASE+SAM_SFR_UTMIHSTRIM_OFFSET) +# define SAM_SFR_UTMIFSTRIM (SAM_SFR_VBASE+SAM_SFR_UTMIFSTRIM_OFFSET) +# define SAM_SFR_UTMISWAP (SAM_SFR_VBASE+SAM_SFR_UTMISWAP_OFFSET) +#endif + #define SAM_SFR_EBICFG (SAM_SFR_VBASE+SAM_SFR_EBICFG_OFFSET) +#ifdef ATSAMA5D4 +# define SAM_SFR_SN0_OFFSET 0x004c /* Serial Number 0 Register */ +# define SAM_SFR_SN0_OFFSET 0x004c /* Serial Number 0 Register */ +# define SAM_SFR_SN1_OFFSET 0x0050 /* Serial Number 1 Register */ +# define SAM_SFR_SN1_OFFSET 0x0050 /* Serial Number 1 Register */ +#endif + /* SFR Register Bit Definitions *****************************************************/ -/* DDR Configuration register (undocumented, REVISIT) */ +/* DDR Configuration register */ -#define SFR_DDRCFG_DRQON (3 << 16) /* Force DDR_DQ and DDR_DQS input buffer always on */ +#define SFR_FDQIEN (1 << 16) /* Force DDR_DQ input buffer always on */ +#define SFR_FDQSIEN (1 << 17) /* Force DDR_DQS input buffer always on */ /* OHCI Interrupt Configuration Register */ @@ -105,6 +131,60 @@ # define SFR_UTMICKTRIM_FREQ_24MHZ (2 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 24 MHz reference clock */ # define SFR_UTMICKTRIM_FREQ_48MHZ (3 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 48 MHz reference clock */ +#ifdef ATSAMA5D4 +# define SFR_UTMICKTRIM_VBG_SHIFT (16) /* Bits 16-19: UTMI Band Gap Voltage Trimming */ +# define SFR_UTMICKTRIM_VBG_MASK (15 << SFR_UTMICKTRIM_VBG_SHIFT) +# define SFR_UTMICKTRIM_VBG(n) ((uint32_t)(n) << SFR_UTMICKTRIM_VBG_SHIFT) +#endif + +#ifdef ATSAMA5D4 +/* UTMI High Speed Trimming Register */ + +# define SFR_UTMIHSTRIM_SQUELCH_SHIFT (0) /* Bits 0-2: UTMI HS SQUELCH Voltage Trimming */ +# define SFR_UTMIHSTRIM_SQUELCH_MASK (7 << SFR_UTMIHSTRIM_SQUELCH_SHIFT) +# define SFR_UTMIHSTRIM_SQUELCH(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SQUELCH_SHIFT) +# define SFR_UTMIHSTRIM_DISC_SHIFT (4) /* Bits 4-6: UTMI Disconnect Voltage Trimming */ +# define SFR_UTMIHSTRIM_DISC_MASK (7 << SFR_UTMIHSTRIM_DISC_SHIFT) +# define SFR_UTMIHSTRIM_DISC(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_DISC_SHIFT) +# define SFR_UTMIHSTRIM_SLOPE0_SHIFT (8) /* Bits 8-10: UTMI HS PORT0 Transceiver Slope Trimming */ +# define SFR_UTMIHSTRIM_SLOPE0_MASK (7 << SFR_UTMIHSTRIM_SLOPE0_SHIFT) +# define SFR_UTMIHSTRIM_SLOPE0(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE0_SHIFT) +# define SFR_UTMIHSTRIM_SLOPE1_SHIFT (12) /* Bits 12-14: UTMI HS PORT1 Transceiver Slope Trimming */ +# define SFR_UTMIHSTRIM_SLOPE1_MASK (7 << SFR_UTMIHSTRIM_SLOPE1_SHIFT) +# define SFR_UTMIHSTRIM_SLOPE1(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE1_SHIFT) +# define SFR_UTMIHSTRIM_SLOPE2_SHIFT (16) /* Bits 16-18: UTMI HS PORT2 Transceiver Slope Trimming */ +# define SFR_UTMIHSTRIM_SLOPE2_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIHSTRIM_SLOPE2(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +#endif + +#ifdef ATSAMA5D4 +/* UTMI Full Speed Trimming Register */ + +# define SFR_UTMIFSTRIM_RISE_SHIFT (0) /* Bits 0-2: FS Transceiver Output Rising Slope Trimming */ +# define SFR_UTMIFSTRIM_RISE_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_RISE(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_FALL_SHIFT (4) /* Bits 4-6: FS Transceiver Output Falling Slope Trimming */ +# define SFR_UTMIFSTRIM_FALL_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_FALL(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_XCVR_SHIFT (8) /* Bits 8-9: FS Transceiver Crossover Voltage Trimming */ +# define SFR_UTMIFSTRIM_XCVR_MASK (3 << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_XCVR(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_ZN_SHIFT (16) /* Bits 16-18: FS Transceiver NMOS Impedance Trimming */ +# define SFR_UTMIFSTRIM_ZN_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_ZN(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_ZP_SHIFT (20) /* Bits 20-22: FS Transceiver PMOS Impedance Trimming */ +# define SFR_UTMIFSTRIM_ZP_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +# define SFR_UTMIFSTRIM_ZP(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT) +#endif + +#ifdef ATSAMA5D4 +/* UTMI DP/DM Pin Swapping Register */ + +# define SFR_UTMISWAP_PORT0 (1 << 0) /* Bit 0: PORT 0 DP/DM Pin Swapping */ +# define SFR_UTMISWAP_PORT1 (1 << 1) /* Bit 1: PORT 1 DP/DM Pin Swapping */ +# define SFR_UTMISWAP_PORT2 (1 << 2) /* Bit 2: PORT 2 DP/DM Pin Swapping */ +#endif + /* EBI Configuration Register */ #define SFR_EBICFG_DRIVE_LOW (0) /* LOW Low drive level */ @@ -129,6 +209,14 @@ #define SFR_EBICFG_PULL1_MASK (3 << SFR_EBICFG_PULL1_SHIFT) # define SFR_EBICFG_PULL1(n) ((n) << SFR_EBICFG_PULL1_SHIFT) #define SFR_EBICFG_SCH1 (1 << 12) /* Bit 12: EBI Pins Schmitt Trigger */ -#define SFR_EBICFG_BMS (1 << 16) /* Bit 16: BMS Sampled Value (Read Only) */ + +#ifdef ATSAMA5D3 +# define SFR_EBICFG_BMS (1 << 16) /* Bit 16: BMS Sampled Value (Read Only) */ +#endif + +#ifdef ATSAMA5D4 +/* Serial Number 0 Register (32-bit value) */ +/* Serial Number 1 Register (32-bit value) */ +#endif #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H */ diff --git a/configs/sama5d3-xplained/src/sam_sdram.c b/configs/sama5d3-xplained/src/sam_sdram.c index 8190d7cca74..abd75d66641 100644 --- a/configs/sama5d3-xplained/src/sam_sdram.c +++ b/configs/sama5d3-xplained/src/sam_sdram.c @@ -206,10 +206,10 @@ void sam_sdram_config(void) regval |= MPDDRC_HS_AUTOREFRESH_CAL; putreg32(regval, SAM_MPDDRC_HS); - /* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ + /* Force DDR_DQ and DDR_DQS input buffer always on */ regval = getreg32(SAM_SFR_DDRCFG); - regval |= SFR_DDRCFG_DRQON; + regval |= SFR_FDQIEN | SFR_FDQSIEN; putreg32(regval, SAM_SFR_DDRCFG); /* Configure the slave offset register */ @@ -235,11 +235,9 @@ void sam_sdram_config(void) regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); putreg32(regval, SAM_MPDDRC_IO_CALIBR); - /* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits - * (undocumented) - */ + /* Force DDR_DQ and DDR_DQS input buffer always on */ - putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); + putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG); /* Step 1: Program the memory device type * diff --git a/configs/sama5d3x-ek/src/sam_sdram.c b/configs/sama5d3x-ek/src/sam_sdram.c index 080ed9a1292..184c5cbda4b 100644 --- a/configs/sama5d3x-ek/src/sam_sdram.c +++ b/configs/sama5d3x-ek/src/sam_sdram.c @@ -205,10 +205,10 @@ void sam_sdram_config(void) regval |= MPDDRC_HS_AUTOREFRESH_CAL; putreg32(regval, SAM_MPDDRC_HS); - /* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ + /* Force DDR_DQ and DDR_DQS input buffer always on */ regval = getreg32(SAM_SFR_DDRCFG); - regval |= SFR_DDRCFG_DRQON; + regval |= SFR_FDQIEN | SFR_FDQSIEN; putreg32(regval, SAM_SFR_DDRCFG); /* Configure the slave offset register */ @@ -234,11 +234,9 @@ void sam_sdram_config(void) regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); putreg32(regval, SAM_MPDDRC_IO_CALIBR); - /* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits - * (undocumented) - */ + /* Force DDR_DQ and DDR_DQS input buffer always on */ - putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); + putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG); /* Step 1: Program the memory device type * diff --git a/configs/sama5d4-ek/src/sam_sdram.c b/configs/sama5d4-ek/src/sam_sdram.c index 44612e26429..3cb32800bf3 100644 --- a/configs/sama5d4-ek/src/sam_sdram.c +++ b/configs/sama5d4-ek/src/sam_sdram.c @@ -206,10 +206,10 @@ void sam_sdram_config(void) regval |= MPDDRC_HS_AUTOREFRESH_CAL; putreg32(regval, SAM_MPDDRC_HS); - /* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ + /* Force DDR_DQ and DDR_DQS input buffer always on */ regval = getreg32(SAM_SFR_DDRCFG); - regval |= SFR_DDRCFG_DRQON; + regval |= SFR_FDQIEN | SFR_FDQSIEN; putreg32(regval, SAM_SFR_DDRCFG); /* Configure the slave offset register */ @@ -235,11 +235,9 @@ void sam_sdram_config(void) regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); putreg32(regval, SAM_MPDDRC_IO_CALIBR); - /* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits - * (undocumented) - */ + /* Force DDR_DQ and DDR_DQS input buffer always on */ - putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); + putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG); /* Step 1: Program the memory device type *