diff --git a/arch/arm/src/lpc54xx/Kconfig b/arch/arm/src/lpc54xx/Kconfig index 5786354be4b..21794488d7b 100644 --- a/arch/arm/src/lpc54xx/Kconfig +++ b/arch/arm/src/lpc54xx/Kconfig @@ -226,3 +226,7 @@ config LPC54_USART9 select USART9_SERIALDRIVER endmenu # LPC54xx Peripheral Selection + +config LPC54_GPIOIRQ + bool "Support GPIO Interrupts" + default n diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs index 73ae2df80ae..8b41da6fcab 100644 --- a/arch/arm/src/lpc54xx/Make.defs +++ b/arch/arm/src/lpc54xx/Make.defs @@ -82,6 +82,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_serial.c +CHIP_CSRCS += lpc54_gpio.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += lpc54_timerisr.c diff --git a/arch/arm/src/lpc54xx/chip/LPC546x_memorymap.h b/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h similarity index 83% rename from arch/arm/src/lpc54xx/chip/LPC546x_memorymap.h rename to arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h index bad4be389f6..9468714b60d 100644 --- a/arch/arm/src/lpc54xx/chip/LPC546x_memorymap.h +++ b/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h @@ -106,36 +106,36 @@ /* APB Bridge 0 */ -#define LP54_SYSCON_BASE 0x40000000 /* Syscon */ -#define LP54_IOCON_BASE 0x40001000 /* IOCON */ -#define LP54_GINT0_BASE 0x40002000 /* GINT0 */ -#define LP54_GINT1_BASE 0x40003000 /* GINT1 */ -#define LP54_PINT_BASE 0x40004000 /* Pin Interrupts (PINT) */ -#define LP54_MUX_BASE 0x40005000 /* Input muxes */ -#define LP54_CTIMER0_BASE 0x40008000 /* CTIMER0 */ -#define LP54_CTIMER1_BASE 0x40009000 /* CTIMER1 */ -#define LP54_WDT_BASE 0x4000c000 /* WDT */ -#define LP54_MRT_BASE 0x4000d000 /* MRT */ -#define LP54_MTICK_BASE 0x4000e000 /* Micro-Tick */ -#define LP54_EEPROMC_BASE 0x40014000 /* EEPROM controller */ -#define LP54_OTP_BASE 0x40016000 /* OTP controller */ +#define LPC54_SYSCON_BASE 0x40000000 /* Syscon */ +#define LPC54_IOCON_BASE 0x40001000 /* IOCON */ +#define LPC54_GINT0_BASE 0x40002000 /* GINT0 */ +#define LPC54_GINT1_BASE 0x40003000 /* GINT1 */ +#define LPC54_PINT_BASE 0x40004000 /* Pin Interrupts (PINT) */ +#define LPC54_MUX_BASE 0x40005000 /* Input muxes */ +#define LPC54_CTIMER0_BASE 0x40008000 /* CTIMER0 */ +#define LPC54_CTIMER1_BASE 0x40009000 /* CTIMER1 */ +#define LPC54_WDT_BASE 0x4000c000 /* WDT */ +#define LPC54_MRT_BASE 0x4000d000 /* MRT */ +#define LPC54_MTICK_BASE 0x4000e000 /* Micro-Tick */ +#define LPC54_EEPROMC_BASE 0x40014000 /* EEPROM controller */ +#define LPC54_OTP_BASE 0x40016000 /* OTP controller */ /* APB Bridge 1 */ -#define LP54_OSYSCON_BASE 0x40020000 /* Other system registers */ -#define LP54_CTIMER2_BASE 0x40028000 /* CTIMER2 */ -#define LP54_RTC_BASE 0x4002c000 /* RTC */ -#define LP54_RIT_BASE 0x4002d000 /* RIT */ -#define LP54_FLASHC_BASE 0x40034000 /* Flash controller */ -#define LP54_SMARCARD0_BASE 0x40036000 /* Smart card 0 */ -#define LP54_SMARCARD1_BASE 0x40037000 /* Smart card 1 */ -#define LP54_RNG_BASE 0x4003a000 /* RNG */ +#define LPC54_OSYSCON_BASE 0x40020000 /* Other system registers */ +#define LPC54_CTIMER2_BASE 0x40028000 /* CTIMER2 */ +#define LPC54_RTC_BASE 0x4002c000 /* RTC */ +#define LPC54_RIT_BASE 0x4002d000 /* RIT */ +#define LPC54_FLASHC_BASE 0x40034000 /* Flash controller */ +#define LPC54_SMARCARD0_BASE 0x40036000 /* Smart card 0 */ +#define LPC54_SMARCARD1_BASE 0x40037000 /* Smart card 1 */ +#define LPC54_RNG_BASE 0x4003a000 /* RNG */ /* Asynchronous APB bridge */ -#define LP54_ASYSCON_BASE 0x40040000 /* Asynchronous Syscon */ -#define LP54_CTIMER3_BASE 0x40048000 /* CTIMER3 */ -#define LP54_CTIMER4_BASE 0x40049000 /* CTIMER4 */ +#define LPC54_ASYSCON_BASE 0x40040000 /* Asynchronous Syscon */ +#define LPC54_CTIMER3_BASE 0x40048000 /* CTIMER3 */ +#define LPC54_CTIMER4_BASE 0x40049000 /* CTIMER4 */ /**************************************************************************************************** * Public Types diff --git a/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h b/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h index ff0301ea699..e1c5badc150 100644 --- a/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h +++ b/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h @@ -43,6 +43,10 @@ #include #include "chip/lpc54_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* Register offsets *****************************************************************/ #define LPC54_FLEXCOMM_PSELID_OFFSET 0x0ff8 /* Peripheral Select /Flexcomm Interface ID */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_gpio.h b/arch/arm/src/lpc54xx/chip/lpc54_gpio.h new file mode 100644 index 00000000000..f9fbcc2a2bd --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_gpio.h @@ -0,0 +1,108 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define LPC54_GPIO_PORT0 0 +#define LPC54_GPIO_PORT1 1 +#define LPC54_GPIO_PORT2 2 +#define LPC54_GPIO_PORT3 3 +#define LPC54_GPIO_PORT4 4 +#define LPC54_GPIO_PORT5 5 +#define LPC54_GPIO_NPORTS 6 + +/* Register offsets *****************************************************************/ +/* Byte and word access to individual pins */ + +#define LPC54_GPIO_B_OFFSET(p) (0x0000 + (p)) +#define LPC54_GPIO_W_OFFSET(p) (0x1000 + ((p) << 2)) + +/* Word access to individual port regisers */ + +#define LPC54_GPIO_PORT_OFFSET(n) ((n) << 2) +#define LPC54_GPIO_DIR_OFFSET(n) (0x2000 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_MASK_OFFSET(n) (0x2080 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_PIN_OFFSET(n) (0x2100 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_MPIN_OFFSET(n) (0x2180 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_SET_OFFSET(n) (0x2200 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_CLR_OFFSET(n) (0x2280 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_NOT_OFFSET(n) (0x2300 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIRSET_OFFSET(n) (0x2380 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIRCLR_OFFSET(n) (0x2400 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIRNOT_OFFSET(n) (0x2480 + LPC54_GPIO_PORT_OFFSET(n)) + +/* Register addresses ***************************************************************/ + +/* Byte and word access to individual pins */ + +#define LPC54_GPIO_B(p) (LPC54_GPIO_BASE + LPC54_GPIO_B_OFFSET(p)) +#define LPC54_GPIO_W(p) (LPC54_GPIO_BASE + LPC54_GPIO_W_OFFSET(p)) + +/* Word access to individual port regisers */ + +#define LPC54_GPIO_PORT(n) (LPC54_GPIO_BASE + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIR(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIR_OFFSET(n)) +#define LPC54_GPIO_MASK(n) (LPC54_GPIO_BASE + LPC54_GPIO_MASK_OFFSET(n)) +#define LPC54_GPIO_PIN(n) (LPC54_GPIO_BASE + LPC54_GPIO_PIN_OFFSET(n)) +#define LPC54_GPIO_MPIN(n) (LPC54_GPIO_BASE + LPC54_GPIO_MPIN_OFFSET(n)) +#define LPC54_GPIO_SET(n) (LPC54_GPIO_BASE + LPC54_GPIO_SET_OFFSET(n)) +#define LPC54_GPIO_CLR(n) (LPC54_GPIO_BASE + LPC54_GPIO_CLR_OFFSET(n)) +#define LPC54_GPIO_NOT(n) (LPC54_GPIO_BASE + LPC54_GPIO_NOT_OFFSET(n)) +#define LPC54_GPIO_DIRSET(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIRSET_OFFSET(n)) +#define LPC54_GPIO_DIRCLR(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIRCLR_OFFSET(n)) +#define LPC54_GPIO_DIRNOT(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIRNOT_OFFSET(n)) + +/* Register bit definitions *********************************************************/ + +/* Port registers are all bit arrays with one bit corresponding each of the 32 pins + * of the port. + */ + +#define GPIO_PORT_BIT(n) (1 << ((n) & 31)) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_iocon.h b/arch/arm/src/lpc54xx/chip/lpc54_iocon.h new file mode 100644 index 00000000000..2787b0caa1f --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_iocon.h @@ -0,0 +1,378 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_iocon.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC54_IOCON_PIO_n_OFFSET(p) ((unsigned int)(p) << 2) +#define LPC54_IOCON_PIO_0_OFFSET (0x0000) /* IOCON Port(n) register 0 */ +#define LPC54_IOCON_PIO_1_OFFSET (0x0004) /* IOCON Port(n) register 1 */ +#define LPC54_IOCON_PIO_2_OFFSET (0x0008) /* IOCON Port(n) register 2 */ +#define LPC54_IOCON_PIO_3_OFFSET (0x000c) /* IOCON Port(n) register 3 */ +#define LPC54_IOCON_PIO_4_OFFSET (0x0010) /* IOCON Port(n) register 4 */ +#define LPC54_IOCON_PIO_5_OFFSET (0x0014) /* IOCON Port(n) register 5 */ +#define LPC54_IOCON_PIO_6_OFFSET (0x0018) /* IOCON Port(n) register 6 */ +#define LPC54_IOCON_PIO_7_OFFSET (0x001c) /* IOCON Port(n) register 7 */ +#define LPC54_IOCON_PIO_8_OFFSET (0x0020) /* IOCON Port(n) register 8 */ +#define LPC54_IOCON_PIO_9_OFFSET (0x0024) /* IOCON Port(n) register 9 */ +#define LPC54_IOCON_PIO_10_OFFSET (0x0028) /* IOCON Port(n) register 10 */ +#define LPC54_IOCON_PIO_11_OFFSET (0x002c) /* IOCON Port(n) register 11 */ +#define LPC54_IOCON_PIO_12_OFFSET (0x0030) /* IOCON Port(n) register 12 */ +#define LPC54_IOCON_PIO_13_OFFSET (0x0034) /* IOCON Port(n) register 13 */ +#define LPC54_IOCON_PIO_14_OFFSET (0x0038) /* IOCON Port(n) register 14 */ +#define LPC54_IOCON_PIO_15_OFFSET (0x003c) /* IOCON Port(n) register 15 */ +#define LPC54_IOCON_PIO_16_OFFSET (0x0040) /* IOCON Port(n) register 16 */ +#define LPC54_IOCON_PIO_17_OFFSET (0x0044) /* IOCON Port(n) register 17 */ +#define LPC54_IOCON_PIO_18_OFFSET (0x0048) /* IOCON Port(n) register 18 */ +#define LPC54_IOCON_PIO_19_OFFSET (0x004c) /* IOCON Port(n) register 19 */ +#define LPC54_IOCON_PIO_20_OFFSET (0x0050) /* IOCON Port(n) register 20 */ +#define LPC54_IOCON_PIO_21_OFFSET (0x0054) /* IOCON Port(n) register 21 */ +#define LPC54_IOCON_PIO_22_OFFSET (0x0058) /* IOCON Port(n) register 22 */ +#define LPC54_IOCON_PIO_23_OFFSET (0x005c) /* IOCON Port(n) register 23 */ +#define LPC54_IOCON_PIO_24_OFFSET (0x0060) /* IOCON Port(n) register 24 */ +#define LPC54_IOCON_PIO_25_OFFSET (0x0064) /* IOCON Port(n) register 25 */ +#define LPC54_IOCON_PIO_26_OFFSET (0x0068) /* IOCON Port(n) register 26 */ +#define LPC54_IOCON_PIO_27_OFFSET (0x006c) /* IOCON Port(n) register 27 */ +#define LPC54_IOCON_PIO_28_OFFSET (0x0070) /* IOCON Port(n) register 28 */ +#define LPC54_IOCON_PIO_29_OFFSET (0x0074) /* IOCON Port(n) register 29 */ +#define LPC54_IOCON_PIO_30_OFFSET (0x0078) /* IOCON Port(n) register 30 */ +#define LPC54_IOCON_PIO_31_OFFSET (0x007c) /* IOCON Port(n) register 31 */ + +/* Register addresses ***************************************************************/ + +#define LPC54_IOCON_PIO_BASE(b) (LPC54_IOCON_BASE + ((unsigned int)(b) << 7)) +#define LPC54_IOCON_PIO0_BASE (LPC54_IOCON_BASE + 0x0000) +#define LPC54_IOCON_PIO1_BASE (LPC54_IOCON_BASE + 0x0080) +#define LPC54_IOCON_PIO2_BASE (LPC54_IOCON_BASE + 0x0100) +#define LPC54_IOCON_PIO3_BASE (LPC54_IOCON_BASE + 0x0180) +#define LPC54_IOCON_PIO4_BASE (LPC54_IOCON_BASE + 0x0200) +#define LPC54_IOCON_PIO5_BASE (LPC54_IOCON_BASE + 0x0280) + +#define LPC54_IOCON_PIO(b,p) (LPC54_IOCON_PIO_BASE(b) + LPC54_IOCON_PIO_n_OFFSET(p)) + +#define LPC54_IOCON_PIO0_0 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO0_1 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO0_2 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO0_3 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO0_4 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO0_5 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO0_6 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO0_7 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO0_8 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO0_9 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO0_10 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO0_11 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO0_12 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO0_13 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO0_14 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO0_15 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO0_16 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO0_17 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO0_18 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO0_19 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO0_20 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO0_21 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO0_22 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO0_23 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO0_24 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO0_25 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO0_26 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO0_27 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO0_28 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO0_29 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO0_30 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO0_31 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO1_0 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO1_1 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO1_2 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO1_3 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO1_4 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO1_5 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO1_6 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO1_7 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO1_8 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO1_9 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO1_10 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO1_11 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO1_12 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO1_13 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO1_14 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO1_15 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO1_16 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO1_17 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO1_18 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO1_19 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO1_20 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO1_21 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO1_22 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO1_23 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO1_24 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO1_25 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO1_26 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO1_27 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO1_28 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO1_29 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO1_30 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO1_31 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO2_0 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO2_1 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO2_2 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO2_3 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO2_4 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO2_5 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO2_6 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO2_7 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO2_8 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO2_9 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO2_10 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO2_11 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO2_12 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO2_13 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO2_14 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO2_15 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO2_16 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO2_17 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO2_18 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO2_19 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO2_20 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO2_21 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO2_22 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO2_23 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO2_24 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO2_25 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO2_26 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO2_27 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO2_28 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO2_29 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO2_30 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO2_31 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO3_0 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO3_1 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO3_2 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO3_3 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO3_4 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO3_5 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO3_6 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO3_7 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO3_8 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO3_9 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO3_10 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO3_11 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO3_12 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO3_13 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO3_14 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO3_15 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO3_16 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO3_17 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO3_18 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO3_19 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO3_20 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO3_21 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO3_22 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO3_23 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO3_24 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO3_25 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO3_26 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO3_27 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO3_28 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO3_29 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO3_30 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO3_31 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO4_0 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO4_1 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO4_2 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO4_3 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO4_4 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO4_5 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO4_6 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO4_7 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO4_8 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO4_9 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO4_10 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO4_11 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO4_12 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO4_13 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO4_14 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO4_15 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO4_16 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO4_17 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO4_18 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO4_19 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO4_20 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO4_21 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO4_22 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO4_23 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO4_24 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO4_25 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO4_26 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO4_27 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO4_28 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO4_29 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO4_30 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO4_31 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO5_0 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO5_1 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO5_2 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO5_3 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO5_4 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO5_5 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO5_6 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO5_7 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO5_8 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO5_9 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO5_10 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO5_11 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO5_12 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO5_13 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO5_14 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO5_15 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO5_16 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO5_17 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO5_18 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO5_19 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO5_20 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO5_21 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO5_22 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO5_23 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO5_24 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO5_25 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO5_26 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO5_27 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO5_28 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO5_29 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO5_30 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO5_31 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_31_OFFSET) + +/* Register bit definitions *********************************************************/ +/* IOCON pin function select */ + +#define IOCON_FUNC_GPIO (0) +#define IOCON_FUNC_ALT1 (1) +#define IOCON_FUNC_ALT2 (2) +#define IOCON_FUNC_ALT3 (3) +#define IOCON_FUNC_ALT4 (4) +#define IOCON_FUNC_ALT5 (5) +#define IOCON_FUNC_ALT6 (6) +#define IOCON_FUNC_ALT7 (7) + +/* Pin modes */ + +#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ +#define IOCON_MODE_PULLDOWN (1) /* 01: pin has a pull-down resistor enabled */ +#define IOCON_MODE_PULLUP (2) /* 10: pin has a pull-up resistor enabled */ +#define IOCON_MODE_REPEATER (3) /* 11: pin has repeater mode enabled */ + +/* Bit field definitions */ + +#define IOCON_FUNC_SHIFT (0) /* Bits 0-3: Pin function. All types */ +#define IOCON_FUNC_MASK (15 << IOCON_FUNC_SHIFT) +# define IOCON_FUNC(n) ((uint32_t)(n) << IOCON_FUNC_SHIFT) +#define IOCON_MODE_SHIFT (4) /* Bits 4-5: Function mode. Types D,A */ +#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT) +# define IOCON_MODE(n) ((uint32_t)(n) << IOCON_MODE_SHIFT) +#define IOCON_I2CSLEW_SHIFT (6) /* Bit 6: I2C slew rate. Type I */ +#define IOCON_I2CSLEW_MASK (1 << IOCON_I2CSLEW_SHIFT) +# define IOCON_I2CSLEW_I2CMODE (0) +# define IOCON_I2CSLEW_GPIO IOCON_I2CSLEW_MASK +#define IOCON_INVERT_SHIFT (7) /* Bit 7: Input polarity. Types D,I,A */ +#define IOCON_INVERT_MASK (1 << IOCON_INVERT_SHIFT) +# define IOCON_INVERT IOCON_INVERT_MASK +#define IOCON_DIGIMODE_SHIFT (8) /* Bit 8: Analog/Digital mode. Types D,I,A */ +#define IOCON_DIGIMODE_MASK (1 << IOCON_DIGIMODE_SHIFT) +# define IOCON_DIGIMODE_ANALOG (0) +# define IOCON_DIGIMODE_DIGITAL IOCON_DIGIMODE_MASK +#define IOCON_FILTEROFF_SHIFT (9) /* Bit 9: Input glitch filter. Types D,I,A */ +#define IOCON_FILTEROFF_MASK (1 << IOCON_FILTEROFF_SHIFT) +# define IOCON_FILTEROFF_ON (0) +# define IOCON_FILTEROFF_OFF IOCON_FILTEROFF_MASK +#define IOCON_SLEW_SHIFT (10) /* Bit 10: Driver slew rate. Type D */ +#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT) +# define IOCON_SLEW_STANDARD (0) +# define IOCON_SLEW_FAST IOCON_SLEW_MASK +#define IOCON_I2CDRIVE_SHIFT (10) /* Bit 10: Sink capability of pin. Type I */ +#define IOCON_I2CDRIVE_MASK (1 << IOCON_I2CDRIVE_SHIFT) +# define IOCON_I2CDRIVE_LOW (0) +# define IOCON_I2CDRIVE_HIGH IOCON_I2CDRIVE_MASK +#define IOCON_OD_SHIFT (11) /* Bit 11: Open-drain mode. Types D,A */ +#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) +# define IOCON_OD_PUSHPULL (0) +# define IOCON_OD_OPENDRAIN IOCON_OD_MASK +#define IOCON_I2CFILTEROFF_SHIFT (11) /* Bit 11: I2C filter mode. Type I */ +#define IOCON_I2CFILTEROFF_MASK (1 << IOCON_I2CFILTEROFF_SHIFT) +# define IOCON_I2CFILTEROFF_ON (0) +# define IOCON_I2CFILTEROFF_OFF IOCON_I2CFILTEROFF_MASK + +/* Pin types by port */ + +#define IOCON_PIO0_TYPED_MASK (0x7f7e63ff) /* P0-9,13-14,17-22,24-30 */ +#define IOCON_PIO1_TYPED_MASK (0xfffffffe) /* P1-31 */ +#define IOCON_PIO2_TYPED_MASK (0xfffffffc) /* P2-31 */ +#define IOCON_PIO3_TYPED_MASK (0xfe000000) /* P25-31 */ +#define IOCON_PIO4_TYPED_MASK (0xffffffff) /* P0-31 */ +#define IOCON_PIO5_TYPED_MASK (0x000007ff) /* P0-10 */ + +#define IOCON_PIO0_TYPEI_MASK (0x00006000) /* P013-14 */ +#define IOCON_PIO1_TYPEI_MASK (0x00000000) /* None */ +#define IOCON_PIO2_TYPEI_MASK (0x00000000) /* None */ +#define IOCON_PIO3_TYPEI_MASK (0x00006000) /* P23-24 */ +#define IOCON_PIO4_TYPEI_MASK (0x00000000) /* None */ +#define IOCON_PIO5_TYPEI_MASK (0x00000000) /* None */ + +#define IOCON_PIO0_TYPEA_MASK (0x80831c00) /* p10-12,15-16,23,31 */ +#define IOCON_PIO1_TYPEA_MASK (0x00000001) /* p0 */ +#define IOCON_PIO2_TYPEA_MASK (0x00000003) /* p0-1 */ +#define IOCON_PIO3_TYPEA_MASK (0x00600000) /* p21-22 */ +#define IOCON_PIO4_TYPEA_MASK (0x00000000) /* None */ +#define IOCON_PIO5_TYPEA_MASK (0x00000000) /* None */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_pint.h b/arch/arm/src/lpc54xx/chip/lpc54_pint.h new file mode 100644 index 00000000000..06d60aa8670 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_pint.h @@ -0,0 +1,111 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/chip/lpc54_pint.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +#define LPC54_PINT_ISEL_OFFSET 0x0000 /* Pin interrupt mode */ +#define LPC54_PINT_IENR_OFFSET 0x0004 /* Pin interrupt level or rising edge interrupt enable */ +#define LPC54_PINT_SIENR_OFFSET 0x0008 /* Pin interrupt level or rising edge interrupt enable set */ +#define LPC54_PINT_CIENR_OFFSET 0x000c /* Pin interrupt level or rising edge interrupt enable clear */ +#define LPC54_PINT_IENF_OFFSET 0x0010 /* Pin interrupt active level or falling edge interrupt enable */ +#define LPC54_PINT_SIENF_OFFSET 0x0014 /* Pin interrupt active level or falling edge interrupt set */ +#define LPC54_PINT_CIENF_OFFSET 0x0018 /* Pin interrupt active level or falling edge interrupt clear */ +#define LPC54_PINT_RISE_OFFSET 0x001c /* Pin interrupt rising edge */ +#define LPC54_PINT_FALL_OFFSET 0x0020 /* Pin interrupt falling edge */ +#define LPC54_PINT_IST_OFFSET 0x0024 /* Pin interrupt status */ +#define LPC54_PINT_PMCTRL_OFFSET 0x0028 /* Pattern match interrupt control */ +#define LPC54_PINT_PMSRC_OFFSET 0x002c /* Pattern match interrupt bit-slice source */ +#define LPC54_PINT_PMCFG_OFFSET 0x0030 /* Pattern match interrupt bit slice configuration */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_PINT_ISEL (LPC54_PINT_BASE + LPC54_PINT_ISEL_OFFSET) +#define LPC54_PINT_IENR (LPC54_PINT_BASE + LPC54_PINT_IENR_OFFSET) +#define LPC54_PINT_SIENR (LPC54_PINT_BASE + LPC54_PINT_SIENR_OFFSET) +#define LPC54_PINT_CIENR (LPC54_PINT_BASE + LPC54_PINT_CIENR_OFFSET) +#define LPC54_PINT_IENF (LPC54_PINT_BASE + LPC54_PINT_IENF_OFFSET) +#define LPC54_PINT_SIENF (LPC54_PINT_BASE + LPC54_PINT_SIENF_OFFSET) +#define LPC54_PINT_CIENF (LPC54_PINT_BASE + LPC54_PINT_CIENF_OFFSET) +#define LPC54_PINT_RISE (LPC54_PINT_BASE + LPC54_PINT_RISE_OFFSET) +#define LPC54_PINT_FALL (LPC54_PINT_BASE + LPC54_PINT_FALL_OFFSET) +#define LPC54_PINT_IST (LPC54_PINT_BASE + LPC54_PINT_IST_OFFSET) +#define LPC54_PINT_PMCTRL (LPC54_PINT_BASE + LPC54_PINT_PMCTRL_OFFSET) +#define LPC54_PINT_PMSRC (LPC54_PINT_BASE + LPC54_PINT_PMSRC_OFFSET) +#define LPC54_PINT_PMCFG (LPC54_PINT_BASE + LPC54_PINT_PMCFG_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* Pin interrupt mode */ +#define PINT_ISEL_ +/* Pin interrupt level or rising edge interrupt enable */ +#define PINT_IENR_ +/* Pin interrupt level or rising edge interrupt enable set */ +#define PINT_SIENR_ +/* Pin interrupt level or rising edge interrupt enable clear */ +#define PINT_CIENR_ +/* Pin interrupt active level or falling edge interrupt enable */ +#define PINT_IENF_ +/* Pin interrupt active level or falling edge interrupt set */ +#define PINT_SIENF_ +/* Pin interrupt active level or falling edge interrupt clear */ +#define PINT_CIENF_ +/* Pin interrupt rising edge */ +#define PINT_RISE_ +/* Pin interrupt falling edge */ +#define PINT_FALL_ +/* Pin interrupt status */ +#define PINT_IST_ +/* Pattern match interrupt control */ +#define PINT_PMCTRL_ +/* Pattern match interrupt bit-slice source */ +#define PINT_PMSRC_ +/* Pattern match interrupt bit slice configuration */ +#define PINT_PMCFG_ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h b/arch/arm/src/lpc54xx/chip/lpc54_syscon.h index 43866ed304d..2a6e415bca1 100644 --- a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h +++ b/arch/arm/src/lpc54xx/chip/lpc54_syscon.h @@ -43,6 +43,10 @@ #include #include "chip/lpc54_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* Register offsets *************************************************************************/ /* Main system configuration */ @@ -187,141 +191,141 @@ /* Main system configuration */ -#define LPC54_SYSCON_AHBMATPRIO (LP54_SYSCON_BASE+LPC54_SYSCON_AHBMATPRIO_OFFSET) -#define LPC54_SYSCON_SYSTCKCAL (LP54_SYSCON_BASE+LPC54_SYSCON_SYSTCKCAL_OFFSET) -#define LPC54_SYSCON_NMISRC (LP54_SYSCON_BASE+LPC54_SYSCON_NMISRC_OFFSET) -#define LPC54_SYSCON_ASYNCAPBCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_ASYNCAPBCTRL_OFFSET) -#define LPC54_SYSCON_PIOPORCAP0 (LP54_SYSCON_BASE+LPC54_SYSCON_PIOPORCAP0_OFFSET) -#define LPC54_SYSCON_PIOPORCAP1 (LP54_SYSCON_BASE+LPC54_SYSCON_PIOPORCAP1_OFFSET) -#define LPC54_SYSCON_PIORESCAP0 (LP54_SYSCON_BASE+LPC54_SYSCON_PIORESCAP0_OFFSET) -#define LPC54_SYSCON_PIORESCAP1 (LP54_SYSCON_BASE+LPC54_SYSCON_PIORESCAP1_OFFSET) -#define LPC54_SYSCON_PRESETCTRL0 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL0_OFFSET) -#define LPC54_SYSCON_PRESETCTRL1 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL1_OFFSET) -#define LPC54_SYSCON_PRESETCTRL2 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL2_OFFSET) -#define LPC54_SYSCON_PRESETCTRLSET0 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET0_OFFSET) -#define LPC54_SYSCON_PRESETCTRLSET1 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET1_OFFSET) -#define LPC54_SYSCON_PRESETCTRLSET2 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET2_OFFSET) -#define LPC54_SYSCON_PRESETCTRLCLR0 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR0_OFFSET) -#define LPC54_SYSCON_PRESETCTRLCLR1 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR1_OFFSET) -#define LPC54_SYSCON_PRESETCTRLCLR2 (LP54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR2_OFFSET) -#define LPC54_SYSCON_SYSRSTSTAT (LP54_SYSCON_BASE+LPC54_SYSCON_SYSRSTSTAT_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRL0 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL0_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRL1 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL1_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRL2 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL2_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRLSET0 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET0_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRLSET1 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET1_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRLSET2 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET2_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRLCLR0 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR0_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRLCLR1 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR1_OFFSET) -#define LPC54_SYSCON_AHBCLKCTRLCLR2 (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR2_OFFSET) -#define LPC54_SYSCON_MAINCLKSELA (LP54_SYSCON_BASE+LPC54_SYSCON_MAINCLKSELA_OFFSET) -#define LPC54_SYSCON_MAINCLKSELB (LP54_SYSCON_BASE+LPC54_SYSCON_MAINCLKSELB_OFFSET) -#define LPC54_SYSCON_CLKOUTSELA (LP54_SYSCON_BASE+LPC54_SYSCON_CLKOUTSELA_OFFSET) -#define LPC54_SYSCON_SYSPLLCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_SYSPLLCLKSEL_OFFSET) -#define LPC54_SYSCON_AUDPLLCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLCLKSEL_OFFSET) -#define LPC54_SYSCON_SPIFICLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_SPIFICLKSEL_OFFSET) -#define LPC54_SYSCON_ADCCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_ADCCLKSEL_OFFSET) -#define LPC54_SYSCON_USB0CLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_USB0CLKSEL_OFFSET) -#define LPC54_SYSCON_USB1CLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_USB1CLKSEL_OFFSET) -#define LPC54_SYSCON_FCLKSEL0 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL0_OFFSET) -#define LPC54_SYSCON_FCLKSEL1 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL1_OFFSET) -#define LPC54_SYSCON_FCLKSEL2 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL2_OFFSET) -#define LPC54_SYSCON_FCLKSEL3 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL3_OFFSET) -#define LPC54_SYSCON_FCLKSEL4 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL4_OFFSET) -#define LPC54_SYSCON_FCLKSEL5 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL5_OFFSET) -#define LPC54_SYSCON_FCLKSEL6 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL6_OFFSET) -#define LPC54_SYSCON_FCLKSEL7 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL7_OFFSET) -#define LPC54_SYSCON_FCLKSEL8 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL8_OFFSET) -#define LPC54_SYSCON_FCLKSEL9 (LP54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL9_OFFSET) -#define LPC54_SYSCON_MCLKCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_MCLKCLKSEL_OFFSET) -#define LPC54_SYSCON_FRGCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_FRGCLKSEL_OFFSET) -#define LPC54_SYSCON_DMICCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_DMICCLKSEL_OFFSET) -#define LPC54_SYSCON_SCTCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_SCTCLKSEL_OFFSET) -#define LPC54_SYSCON_LCDCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_LCDCLKSEL_OFFSET) -#define LPC54_SYSCON_SDIOCLKSEL (LP54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKSEL_OFFSET) -#define LPC54_SYSCON_SYSTICKCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_SYSTICKCLKDIV_OFFSET) -#define LPC54_SYSCON_ARMTRCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_ARMTRCLKDIV_OFFSET) -#define LPC54_SYSCON_CAN0CLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_CAN0CLKDIV_OFFSET) -#define LPC54_SYSCON_CAN1CLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_CAN1CLKDIV_OFFSET) -#define LPC54_SYSCON_SC0CLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_SC0CLKDIV_OFFSET) -#define LPC54_SYSCON_SC1CLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_SC1CLKDIV_OFFSET) -#define LPC54_SYSCON_AHBCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_AHBCLKDIV_OFFSET) -#define LPC54_SYSCON_CLKOUTDIV (LP54_SYSCON_BASE+LPC54_SYSCON_CLKOUTDIV_OFFSET) -#define LPC54_SYSCON_FROHFDIV (LP54_SYSCON_BASE+LPC54_SYSCON_FROHFDIV_OFFSET) -#define LPC54_SYSCON_SPIFICLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_SPIFICLKDIV_OFFSET) -#define LPC54_SYSCON_ADCCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_ADCCLKDIV_OFFSET) -#define LPC54_SYSCON_USB0CLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_USB0CLKDIV_OFFSET) -#define LPC54_SYSCON_USB1CLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_USB1CLKDIV_OFFSET) -#define LPC54_SYSCON_FRGCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_FRGCTRL_OFFSET) -#define LPC54_SYSCON_DMICCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_DMICCLKDIV_OFFSET) -#define LPC54_SYSCON_MCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_MCLKDIV_OFFSET) -#define LPC54_SYSCON_LCDCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_LCDCLKDIV_OFFSET) -#define LPC54_SYSCON_SCTCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_SCTCLKDIV_OFFSET) -#define LPC54_SYSCON_EMCCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_EMCCLKDIV_OFFSET) -#define LPC54_SYSCON_SDIOCLKDIV (LP54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKDIV_OFFSET) -#define LPC54_SYSCON_FLASHCFG (LP54_SYSCON_BASE+LPC54_SYSCON_FLASHCFG_OFFSET) -#define LPC54_SYSCON_USB0CLKCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_USB0CLKCTRL_OFFSET) -#define LPC54_SYSCON_USB0CLKSTAT (LP54_SYSCON_BASE+LPC54_SYSCON_USB0CLKSTAT_OFFSET) -#define LPC54_SYSCON_FREQMECTRL (LP54_SYSCON_BASE+LPC54_SYSCON_FREQMECTRL_OFFSET) -#define LPC54_SYSCON_MCLKIO (LP54_SYSCON_BASE+LPC54_SYSCON_MCLKIO_OFFSET) -#define LPC54_SYSCON_USB1CLKCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_USB1CLKCTRL_OFFSET) -#define LPC54_SYSCON_USB1CLKSTAT (LP54_SYSCON_BASE+LPC54_SYSCON_USB1CLKSTAT_OFFSET) -#define LPC54_SYSCON_EMCSYSCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_EMCSYSCTRL_OFFSET) -#define LPC54_SYSCON_EMCDLYCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_EMCDLYCTRL_OFFSET) -#define LPC54_SYSCON_EMCDLYCAL (LP54_SYSCON_BASE+LPC54_SYSCON_EMCDLYCAL_OFFSET) -#define LPC54_SYSCON_ETHPHYSEL (LP54_SYSCON_BASE+LPC54_SYSCON_ETHPHYSEL_OFFSET) -#define LPC54_SYSCON_ETHSBDCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_ETHSBDCTRL_OFFSET) -#define LPC54_SYSCON_SDIOCLKCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKCTRL_OFFSET) -#define LPC54_SYSCON_FROCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_FROCTRL_OFFSET) -#define LPC54_SYSCON_SYSOSCCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_SYSOSCCTRL_OFFSET) -#define LPC54_SYSCON_WDTOSCCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_WDTOSCCTRL_OFFSET) -#define LPC54_SYSCON_RTCOSCCTRL_ (LP54_SYSCON_BASE+LPC54_SYSCON_RTCOSCCTRL_OFFSET) -#define LPC54_SYSCON_USBPLLCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_USBPLLCTRL_OFFSET) -#define LPC54_SYSCON_USBPLLSTAT (LP54_SYSCON_BASE+LPC54_SYSCON_USBPLLSTAT_OFFSET) -#define LPC54_SYSCON_SYSPLLCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_SYSPLLCTRL_OFFSET) -#define LPC54_SYSCON_SYSPLLSTAT (LP54_SYSCON_BASE+LPC54_SYSCON_SYSPLLSTAT_OFFSET) -#define LPC54_SYSCON_SYSPLLNDEC (LP54_SYSCON_BASE+LPC54_SYSCON_SYSPLLNDEC_OFFSET) -#define LPC54_SYSCON_SYSPLLPDEC (LP54_SYSCON_BASE+LPC54_SYSCON_SYSPLLPDEC_OFFSET) -#define LPC54_SYSCON_SYSPLLMDEC (LP54_SYSCON_BASE+LPC54_SYSCON_SYSPLLMDEC_OFFSET) -#define LPC54_SYSCON_AUDPLLCTRL (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLCTRL_OFFSET) -#define LPC54_SYSCON_AUDPLLSTAT (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLSTAT_OFFSET) -#define LPC54_SYSCON_AUDPLLNDEC (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLNDEC_OFFSET) -#define LPC54_SYSCON_AUDPLLPDEC (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLPDEC_OFFSET) -#define LPC54_SYSCON_AUDPLLMDEC (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLMDEC_OFFSET) -#define LPC54_SYSCON_AUDPLLFRAC (LP54_SYSCON_BASE+LPC54_SYSCON_AUDPLLFRAC_OFFSET) -#define LPC54_SYSCON_PDSLEEPCFG0 (LP54_SYSCON_BASE+LPC54_SYSCON_PDSLEEPCFG0_OFFSET) -#define LPC54_SYSCON_PDSLEEPCFG1 (LP54_SYSCON_BASE+LPC54_SYSCON_PDSLEEPCFG1_OFFSET) -#define LPC54_SYSCON_PDRUNCFG0 (LP54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFG0_OFFSET) -#define LPC54_SYSCON_PDRUNCFG1 (LP54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFG1_OFFSET) -#define LPC54_SYSCON_PDRUNCFGSET0 (LP54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGSET0_OFFSET) -#define LPC54_SYSCON_PDRUNCFGSET1 (LP54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGSET1_OFFSET) -#define LPC54_SYSCON_PDRUNCFGCLR0 (LP54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGCLR0_OFFSET) -#define LPC54_SYSCON_PDRUNCFGCLR1 (LP54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGCLR1_OFFSET) -#define LPC54_SYSCON_STARTER0 (LP54_SYSCON_BASE+LPC54_SYSCON_STARTER0_OFFSET) -#define LPC54_SYSCON_STARTER1 (LP54_SYSCON_BASE+LPC54_SYSCON_STARTER1_OFFSET) -#define LPC54_SYSCON_STARTERSET0 (LP54_SYSCON_BASE+LPC54_SYSCON_STARTERSET0_OFFSET) -#define LPC54_SYSCON_STARTERSET1 (LP54_SYSCON_BASE+LPC54_SYSCON_STARTERSET1_OFFSET) -#define LPC54_SYSCON_STARTERCLR0 (LP54_SYSCON_BASE+LPC54_SYSCON_STARTERCLR0_OFFSET) -#define LPC54_SYSCON_STARTERCLR1 (LP54_SYSCON_BASE+LPC54_SYSCON_STARTERCLR1_OFFSET) -#define LPC54_SYSCON_HWWAKE (LP54_SYSCON_BASE+LPC54_SYSCON_HWWAKE_OFFSET) -#define LPC54_SYSCON_AUTOCGOR (LP54_SYSCON_BASE+LPC54_SYSCON_AUTOCGOR_OFFSET) -#define LPC54_SYSCON_JTAGIDCODE (LP54_SYSCON_BASE+LPC54_SYSCON_JTAGIDCODE_OFFSET) -#define LPC54_SYSCON_DEVICE_ID0 (LP54_SYSCON_BASE+LPC54_SYSCON_DEVICE_ID0_OFFSET) -#define LPC54_SYSCON_DEVICE_ID1 (LP54_SYSCON_BASE+LPC54_SYSCON_DEVICE_ID1_OFFSET) +#define LPC54_SYSCON_AHBMATPRIO (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBMATPRIO_OFFSET) +#define LPC54_SYSCON_SYSTCKCAL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSTCKCAL_OFFSET) +#define LPC54_SYSCON_NMISRC (LPC54_SYSCON_BASE+LPC54_SYSCON_NMISRC_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_ASYNCAPBCTRL_OFFSET) +#define LPC54_SYSCON_PIOPORCAP0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIOPORCAP0_OFFSET) +#define LPC54_SYSCON_PIOPORCAP1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIOPORCAP1_OFFSET) +#define LPC54_SYSCON_PIORESCAP0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIORESCAP0_OFFSET) +#define LPC54_SYSCON_PIORESCAP1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PIORESCAP1_OFFSET) +#define LPC54_SYSCON_PRESETCTRL0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL0_OFFSET) +#define LPC54_SYSCON_PRESETCTRL1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL1_OFFSET) +#define LPC54_SYSCON_PRESETCTRL2 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRL2_OFFSET) +#define LPC54_SYSCON_PRESETCTRLSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET0_OFFSET) +#define LPC54_SYSCON_PRESETCTRLSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET1_OFFSET) +#define LPC54_SYSCON_PRESETCTRLSET2 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLSET2_OFFSET) +#define LPC54_SYSCON_PRESETCTRLCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR0_OFFSET) +#define LPC54_SYSCON_PRESETCTRLCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR1_OFFSET) +#define LPC54_SYSCON_PRESETCTRLCLR2 (LPC54_SYSCON_BASE+LPC54_SYSCON_PRESETCTRLCLR2_OFFSET) +#define LPC54_SYSCON_SYSRSTSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSRSTSTAT_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRL0 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL0_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRL1 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL1_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRL2 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRL2_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET0_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET1_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLSET2 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLSET2_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR0_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR1_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLCLR2 (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKCTRLCLR2_OFFSET) +#define LPC54_SYSCON_MAINCLKSELA (LPC54_SYSCON_BASE+LPC54_SYSCON_MAINCLKSELA_OFFSET) +#define LPC54_SYSCON_MAINCLKSELB (LPC54_SYSCON_BASE+LPC54_SYSCON_MAINCLKSELB_OFFSET) +#define LPC54_SYSCON_CLKOUTSELA (LPC54_SYSCON_BASE+LPC54_SYSCON_CLKOUTSELA_OFFSET) +#define LPC54_SYSCON_SYSPLLCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLCLKSEL_OFFSET) +#define LPC54_SYSCON_AUDPLLCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLCLKSEL_OFFSET) +#define LPC54_SYSCON_SPIFICLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SPIFICLKSEL_OFFSET) +#define LPC54_SYSCON_ADCCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_ADCCLKSEL_OFFSET) +#define LPC54_SYSCON_USB0CLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKSEL_OFFSET) +#define LPC54_SYSCON_USB1CLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKSEL_OFFSET) +#define LPC54_SYSCON_FCLKSEL0 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL0_OFFSET) +#define LPC54_SYSCON_FCLKSEL1 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL1_OFFSET) +#define LPC54_SYSCON_FCLKSEL2 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL2_OFFSET) +#define LPC54_SYSCON_FCLKSEL3 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL3_OFFSET) +#define LPC54_SYSCON_FCLKSEL4 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL4_OFFSET) +#define LPC54_SYSCON_FCLKSEL5 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL5_OFFSET) +#define LPC54_SYSCON_FCLKSEL6 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL6_OFFSET) +#define LPC54_SYSCON_FCLKSEL7 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL7_OFFSET) +#define LPC54_SYSCON_FCLKSEL8 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL8_OFFSET) +#define LPC54_SYSCON_FCLKSEL9 (LPC54_SYSCON_BASE+LPC54_SYSCON_FCLKSEL9_OFFSET) +#define LPC54_SYSCON_MCLKCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_MCLKCLKSEL_OFFSET) +#define LPC54_SYSCON_FRGCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_FRGCLKSEL_OFFSET) +#define LPC54_SYSCON_DMICCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_DMICCLKSEL_OFFSET) +#define LPC54_SYSCON_SCTCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SCTCLKSEL_OFFSET) +#define LPC54_SYSCON_LCDCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_LCDCLKSEL_OFFSET) +#define LPC54_SYSCON_SDIOCLKSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKSEL_OFFSET) +#define LPC54_SYSCON_SYSTICKCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSTICKCLKDIV_OFFSET) +#define LPC54_SYSCON_ARMTRCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_ARMTRCLKDIV_OFFSET) +#define LPC54_SYSCON_CAN0CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_CAN0CLKDIV_OFFSET) +#define LPC54_SYSCON_CAN1CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_CAN1CLKDIV_OFFSET) +#define LPC54_SYSCON_SC0CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SC0CLKDIV_OFFSET) +#define LPC54_SYSCON_SC1CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SC1CLKDIV_OFFSET) +#define LPC54_SYSCON_AHBCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_AHBCLKDIV_OFFSET) +#define LPC54_SYSCON_CLKOUTDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_CLKOUTDIV_OFFSET) +#define LPC54_SYSCON_FROHFDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_FROHFDIV_OFFSET) +#define LPC54_SYSCON_SPIFICLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SPIFICLKDIV_OFFSET) +#define LPC54_SYSCON_ADCCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_ADCCLKDIV_OFFSET) +#define LPC54_SYSCON_USB0CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKDIV_OFFSET) +#define LPC54_SYSCON_USB1CLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKDIV_OFFSET) +#define LPC54_SYSCON_FRGCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_FRGCTRL_OFFSET) +#define LPC54_SYSCON_DMICCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_DMICCLKDIV_OFFSET) +#define LPC54_SYSCON_MCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_MCLKDIV_OFFSET) +#define LPC54_SYSCON_LCDCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_LCDCLKDIV_OFFSET) +#define LPC54_SYSCON_SCTCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SCTCLKDIV_OFFSET) +#define LPC54_SYSCON_EMCCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCCLKDIV_OFFSET) +#define LPC54_SYSCON_SDIOCLKDIV (LPC54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKDIV_OFFSET) +#define LPC54_SYSCON_FLASHCFG (LPC54_SYSCON_BASE+LPC54_SYSCON_FLASHCFG_OFFSET) +#define LPC54_SYSCON_USB0CLKCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKCTRL_OFFSET) +#define LPC54_SYSCON_USB0CLKSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_USB0CLKSTAT_OFFSET) +#define LPC54_SYSCON_FREQMECTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_FREQMECTRL_OFFSET) +#define LPC54_SYSCON_MCLKIO (LPC54_SYSCON_BASE+LPC54_SYSCON_MCLKIO_OFFSET) +#define LPC54_SYSCON_USB1CLKCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKCTRL_OFFSET) +#define LPC54_SYSCON_USB1CLKSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_USB1CLKSTAT_OFFSET) +#define LPC54_SYSCON_EMCSYSCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCSYSCTRL_OFFSET) +#define LPC54_SYSCON_EMCDLYCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCDLYCTRL_OFFSET) +#define LPC54_SYSCON_EMCDLYCAL (LPC54_SYSCON_BASE+LPC54_SYSCON_EMCDLYCAL_OFFSET) +#define LPC54_SYSCON_ETHPHYSEL (LPC54_SYSCON_BASE+LPC54_SYSCON_ETHPHYSEL_OFFSET) +#define LPC54_SYSCON_ETHSBDCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_ETHSBDCTRL_OFFSET) +#define LPC54_SYSCON_SDIOCLKCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_SDIOCLKCTRL_OFFSET) +#define LPC54_SYSCON_FROCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_FROCTRL_OFFSET) +#define LPC54_SYSCON_SYSOSCCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSOSCCTRL_OFFSET) +#define LPC54_SYSCON_WDTOSCCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_WDTOSCCTRL_OFFSET) +#define LPC54_SYSCON_RTCOSCCTRL_ (LPC54_SYSCON_BASE+LPC54_SYSCON_RTCOSCCTRL_OFFSET) +#define LPC54_SYSCON_USBPLLCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_USBPLLCTRL_OFFSET) +#define LPC54_SYSCON_USBPLLSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_USBPLLSTAT_OFFSET) +#define LPC54_SYSCON_SYSPLLCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLCTRL_OFFSET) +#define LPC54_SYSCON_SYSPLLSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLSTAT_OFFSET) +#define LPC54_SYSCON_SYSPLLNDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLNDEC_OFFSET) +#define LPC54_SYSCON_SYSPLLPDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLPDEC_OFFSET) +#define LPC54_SYSCON_SYSPLLMDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_SYSPLLMDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLCTRL (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLCTRL_OFFSET) +#define LPC54_SYSCON_AUDPLLSTAT (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLSTAT_OFFSET) +#define LPC54_SYSCON_AUDPLLNDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLNDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLPDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLPDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLMDEC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLMDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLFRAC (LPC54_SYSCON_BASE+LPC54_SYSCON_AUDPLLFRAC_OFFSET) +#define LPC54_SYSCON_PDSLEEPCFG0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDSLEEPCFG0_OFFSET) +#define LPC54_SYSCON_PDSLEEPCFG1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDSLEEPCFG1_OFFSET) +#define LPC54_SYSCON_PDRUNCFG0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFG0_OFFSET) +#define LPC54_SYSCON_PDRUNCFG1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFG1_OFFSET) +#define LPC54_SYSCON_PDRUNCFGSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGSET0_OFFSET) +#define LPC54_SYSCON_PDRUNCFGSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGSET1_OFFSET) +#define LPC54_SYSCON_PDRUNCFGCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGCLR0_OFFSET) +#define LPC54_SYSCON_PDRUNCFGCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_PDRUNCFGCLR1_OFFSET) +#define LPC54_SYSCON_STARTER0 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTER0_OFFSET) +#define LPC54_SYSCON_STARTER1 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTER1_OFFSET) +#define LPC54_SYSCON_STARTERSET0 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERSET0_OFFSET) +#define LPC54_SYSCON_STARTERSET1 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERSET1_OFFSET) +#define LPC54_SYSCON_STARTERCLR0 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERCLR0_OFFSET) +#define LPC54_SYSCON_STARTERCLR1 (LPC54_SYSCON_BASE+LPC54_SYSCON_STARTERCLR1_OFFSET) +#define LPC54_SYSCON_HWWAKE (LPC54_SYSCON_BASE+LPC54_SYSCON_HWWAKE_OFFSET) +#define LPC54_SYSCON_AUTOCGOR (LPC54_SYSCON_BASE+LPC54_SYSCON_AUTOCGOR_OFFSET) +#define LPC54_SYSCON_JTAGIDCODE (LPC54_SYSCON_BASE+LPC54_SYSCON_JTAGIDCODE_OFFSET) +#define LPC54_SYSCON_DEVICE_ID0 (LPC54_SYSCON_BASE+LPC54_SYSCON_DEVICE_ID0_OFFSET) +#define LPC54_SYSCON_DEVICE_ID1 (LPC54_SYSCON_BASE+LPC54_SYSCON_DEVICE_ID1_OFFSET) /* Asynchronous system configuration */ -#define LPC54_SYSCON_ASYNCPRESETCTRL (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRL_OFFSET) -#define LPC54_SYSCON_ASYNCPRESETCTRLSET (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRLSET_OFFSET) -#define LPC54_SYSCON_ASYNCPRESETCTRLCLR (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRLCLR_OFFSET) -#define LPC54_SYSCON_ASYNCAPBCLKCTRL (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRL_OFFSET) -#define LPC54_SYSCON_ASYNCAPBCLKCTRLSET (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRLSET_OFFSET) -#define LPC54_SYSCON_ASYNCAPBCLKCTRLCLR (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRLCLR_OFFSET) -#define LPC54_SYSCON_ASYNCAPBCLKSELA (LP54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKSELA_OFFSET) +#define LPC54_SYSCON_ASYNCPRESETCTRL (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRL_OFFSET) +#define LPC54_SYSCON_ASYNCPRESETCTRLSET (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRLSET_OFFSET) +#define LPC54_SYSCON_ASYNCPRESETCTRLCLR (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCPRESETCTRLCLR_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKCTRL (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRL_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKCTRLSET (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRLSET_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKCTRLCLR (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKCTRLCLR_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKSELA (LPC54_ASYSCON_BASE+LPC54_SYSCON_ASYNCAPBCLKSELA_OFFSET) /* Other system configuration */ -#define LPC54_SYSCON_BODCTRL (LP54_OSYSCON_BASE+LPC54_SYSCON_BODCTRL_OFFSET) +#define LPC54_SYSCON_BODCTRL (LPC54_OSYSCON_BASE+LPC54_SYSCON_BODCTRL_OFFSET) /* Register bit definitions *****************************************************************/ diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.c b/arch/arm/src/lpc54xx/lpc54_gpio.c new file mode 100644 index 00000000000..a94ed297946 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_gpio.c @@ -0,0 +1,469 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_gpio.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip/lpc54_iocon.h" +#include "chip/lpc54_gpio.h" +#include "lpc54_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default input pin configuration */ + +#define PORTPIN_MASK (GPIO_PORT_MASK|GPIO_PIN_MASK) +#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP) + +/* Pin types */ + +#define PIN_TYPE_UNKNOWN 0 +#define PIN_TYPED (1 << 0) +#define PIN_TYPEI (1 << 1) +#define PIN_TYPEA (1 << 2) + +/* Helpers */ + +#define GPIO_PORTPIN_MASKGPIO_PORTPIN_MASK (GPIO_PORT_MASK | GPIO_PIN_MASK) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_typed_mask[LPC54_GPIO_NPORTS] = +{ + IOCON_PIO0_TYPED_MASK, + IOCON_PIO1_TYPED_MASK, + IOCON_PIO2_TYPED_MASK, + IOCON_PIO3_TYPED_MASK, + IOCON_PIO4_TYPED_MASK, + IOCON_PIO5_TYPED_MASK, +}; + +static const uint32_t g_typei_mask[LPC54_GPIO_NPORTS] = +{ + IOCON_PIO0_TYPEI_MASK, + IOCON_PIO1_TYPEI_MASK, + IOCON_PIO2_TYPEI_MASK, + IOCON_PIO3_TYPEI_MASK, + IOCON_PIO4_TYPEI_MASK, + IOCON_PIO5_TYPEI_MASK, +}; + +static const uint32_t g_typea_mask[LPC54_GPIO_NPORTS] = +{ + IOCON_PIO0_TYPEA_MASK, + IOCON_PIO1_TYPEA_MASK, + IOCON_PIO2_TYPEA_MASK, + IOCON_PIO3_TYPEA_MASK, + IOCON_PIO4_TYPEA_MASK, + IOCON_PIO5_TYPEA_MASK, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_pintype + * + * Description: + * Get the LPC548x IOCON register mask. + * + * Type D: FUNC MODE INVERT DIGIMODE FILTEROFF SLEW OD + * Type I: FUNC I2CSLEW INVERT DIGIMODE FILTEROFF I2CDRIVE I2CFILTEROFF + * Type A: FUNC MODE INVERT DIGIMODE FILTEROFF OD + * + ****************************************************************************/ + +static uint8_t lpc54_pintype(unsigned int port, unsigned int pin) +{ + uint8_t pintype = 0; + + if ((g_typed_mask[port] & (1 << pin)) != 0) + { + pintype |= PIN_TYPED; + } + + if ((g_typei_mask[port] & (1 << pin)) != 0) + { + pintype |= PIN_TYPEI; + } + + if ((g_typea_mask[port] & (1 << pin)) != 0) + { + pintype |= PIN_TYPEA; + } + + return pintype; +} + +/**************************************************************************** + * Name: lpc54_setpinfunction + * + * Description: + * Select pin function. + * + ****************************************************************************/ + +static void lpc54_setpinfunction(unsigned int port, unsigned int pin, + unsigned int value) +{ + uintptr_t regaddr; + uint32_t regval; + + regaddr = LPC54_IOCON_PIO(port, pin); + regval = getreg32(regaddr); + regval &= ~IOCON_FUNC_MASK; + regval |= (value << IOCON_FUNC_SHIFT); + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: lpc54_configinput + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void lpc54_configinput(lpc54_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t pinmask = (1 << pin); + + /* Set as input */ + + regaddr = LPC54_GPIO_DIR(port); + regval = getreg32(regaddr); + regval &= ~pinmask; + putreg32(regval, regaddr); + + /* Configure as GPIO */ + + lpc54_setpinfunction(port, pin, IOCON_FUNC_GPIO); +} + +/**************************************************************************** + * Name: lpc54_configinterrupt + * + * Description: + * Configure a GPIO interrupt pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void lpc54_configinterrupt(lpc54_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: lpc54_configoutput + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void lpc54_configoutput(lpc54_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uintptr_t regaddr; + uint32_t regval; + + /* Configure the pin as an output */ + + regaddr = LPC54_GPIO_DIR(port); + regval = getreg32(regaddr); + regval |= (1 << pin); + putreg32(regval, regaddr); + + /* Set the initial value of the output */ + + lpc54_gpio_write(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); +} + +/**************************************************************************** + * Name: lpc54_configalternate + * + * Description: + * Configure a GPIO alternate function pin based on bit-encoded description + * of the pin. + * + ****************************************************************************/ + +static inline void lpc54_configalternate(lpc54_pinset_t cfgset, + unsigned int port, unsigned int pin, + uint32_t alt) +{ + /* Select the alternate pin function */ + + lpc54_setpinfunction(port, pin, alt); +} + +/**************************************************************************** + * Name: lpc54_setiocon + * + * Description: + * Configure the pin IOCON register. + * + ****************************************************************************/ + +static void lpc54_setiocon(lpc54_pinset_t cfgset, unsigned int port, + unsigned int pin) +{ + uintptr_t regaddr; + uint32_t iocon; + uint8_t pintype; + + /* Configure pins for supported pin type(s): + * + * Type D: FUNC MODE INVERT DIGIMODE FILTEROFF SLEW OD + * Type I: FUNC I2CSLEW INVERT DIGIMODE FILTEROFF I2CDRIVE I2CFILTEROFF + * Type A: FUNC MODE INVERT DIGIMODE FILTEROFF OD + */ + + pintype = lpc54_pintype(port, pin); + iocon = IOCON_FUNC(IOCON_FUNC_GPIO); + + /* MODE: Type D and A only */ + + if ((pintype & (PIN_TYPED | PIN_TYPEA)) != 0) + { + uint32_t mode = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT; + iocon |= mode << IOCON_MODE_SHIFT; + } + + /* I2CSLEW: Type I only */ + + if ((pintype & PIN_TYPEI) != 0 && (cfgset & GPIO_I2CSLEW_MASK) != 0) + { + iocon |= IOCON_I2CSLEW_GPIO; + } + + /* INVERT: All types */ + + if ((cfgset & GPIO_INVERT_MASK) != 0) + { + iocon |= IOCON_INVERT; + } + + /* DIGIMODE: All types */ + + if ((cfgset & GPIO_DIGIMODE_MASK) != 0) + { + iocon |= IOCON_DIGIMODE_DIGITAL; + } + + /* FILTEROFF: All types */ + + if ((cfgset & GPIO_FILTEROFF_MASK) != 0) + { + iocon |= IOCON_FILTEROFF_OFF; + } + + /* SLEW: Type D only */ + + if ((pintype & PIN_TYPED) != 0 && (cfgset & GPIO_SLEW_MASK) != 0) + { + iocon |= IOCON_SLEW_FAST; + } + + /* I2CDRIVE: Type I only */ + + if ((pintype & PIN_TYPEI) != 0 && (cfgset & GPIO_I2CDRIVE_MASK) != 0) + { + iocon |= IOCON_I2CDRIVE_HIGH; + } + + /* OD: Type D and A only */ + + if ((pintype & (PIN_TYPED | PIN_TYPEA)) != 0 && + (cfgset & GPIO_OD_MASK) != 0) + { + iocon |= IOCON_OD_OPENDRAIN; + } + + /* I2CFILTEROFF: Type I only */ + + if ((pintype & PIN_TYPEI) != 0 && (cfgset & GPIO_I2CFILTEROFF_MASK) != 0) + { + iocon |= IOCON_I2CFILTEROFF_OFF; + } + + /* Now write the IOCON settings */ + + regaddr = LPC54_IOCON_PIO(port, pin); + putreg32(iocon, regaddr); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lpc54_gpio_config(lpc54_pinset_t cfgset) +{ + lpc54_pinset_t definput; + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < LPC54_GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for + * that pin. + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* First, configure the port as a generic input so that we have a + * known starting point and consistent behavior during the re- + * configuration. + */ + + definput = (cfgset & PORTPIN_MASK) | DEFAULT_INPUT; + lpc54_configinput(definput, port, pin); + + /* Set the IOCON bits */ + + lpc54_setiocon(definput, port, pin); + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + break; /* Already configured */ + + case GPIO_INTFE: /* GPIO interrupt falling edge */ + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + lpc54_configinterrupt(cfgset, port, pin); + break; + + case GPIO_OUTPUT: /* GPIO outpout pin */ + lpc54_configoutput(cfgset, port, pin); + break; + + case GPIO_ALT1: /* Alternate function 1 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1); + break; + + case GPIO_ALT2: /* Alternate function 2 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2); + break; + + case GPIO_ALT3: /* Alternate function 3 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3); + break; + + case GPIO_ALT4: /* Alternate function 4 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT4); + break; + + case GPIO_ALT5: /* Alternate function 5 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT5); + break; + + case GPIO_ALT6: /* Alternate function 6 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT6); + break; + + case GPIO_ALT7: /* Alternate function 7 */ + lpc54_configalternate(cfgset, port, pin, IOCON_FUNC_ALT7); + break; + + default: + return -EINVAL; + } + } + + return OK; +} + +/**************************************************************************** + * Name: lpc54_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lpc54_gpio_write(lpc54_pinset_t pinset, bool value) +{ + unsigned int portpin = pinset & GPIO_PIN_MASK; + putreg8((uint32_t)value, LPC54_GPIO_B(portpin)); +} + +/**************************************************************************** + * Name: lpc54_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lpc54_gpio_read(lpc54_pinset_t pinset) +{ + unsigned int portpin = pinset & GPIO_PIN_MASK; + return (bool)getreg8(LPC54_GPIO_B(portpin)); +} diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.h b/arch/arm/src/lpc54xx/lpc54_gpio.h new file mode 100644 index 00000000000..01c3212cc11 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_gpio.h @@ -0,0 +1,336 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_gpio.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_GPIO_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include + +#include "chip/lpc54_gpio.h" +#include "chip/lpc54_iocon.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Bit-encoded input to lpc54_gpio_config() ******************************************/ + +/* 32-Bit Encoding: .... .... TTTT TTTT FFFF ...V PPPN NNNN + * + * Special Pin Functions: TTTT TTTT + * Pin Function: FFFF + * Pin Mode bits: MM + * Open drain: O (output pins) + * Initial value: V (output pins) + * Port number: PPP (0-5) + * Pin number: NNNNN (0-31) + */ + +/* Special Pin Functions: + * For pins that have ADC/DAC, USB, I2C + * + * .... .... TTTT TTTT .... .... .... .... + */ + +#define GPIO_I2CSLEW_SHIFT (16) /* Bit 16: Controls slew rate of I2C pad */ +#define GPIO_I2CSLEW_MASK (1 << GPIO_I2CSLEW_SHIFT) +# define GPIO_I2CSLEW_I2C (0) +# define GPIO_I2CSLEW_GPIO GPIO_I2CSLEW_MASK + +#define GPIO_INVERT_SHIFT (17) /* Bit 17: Input polarity */ +#define GPIO_INVERT_MASK (1 << GPIO_INVERT_SHIFT) +# define GPIO_INVERT GPIO_INVERT_MASK + +#define GPIO_DIGIMODE_SHIFT (18) /* Bit 18: Select Analog/Digital mode */ +#define GPIO_DIGIMODE_MASK (1 << GPIO_DIGIMODE_SHIFT) +# define GPIO_MODE_ANALOG (0) +# define GPIO_MODE_DIGITAL GPIO_DIGIMODE_MASK + +#define GPIO_FILTEROFF_SHIFT (19) /* Bit 19: Controls input glitch filter */ +#define GPIO_FILTEROFF_MASK (1 << GPIO_FILTEROFF_SHIFT) +# define GPIO_FILTER_ON (0) +# define GPIO_FILTER_OFF GPIO_FILTEROFF_MASK + +#define GPIO_SLEW_SHIFT (20) /* Bit 20: Driver slew rate */ +#define GPIO_SLEW_MASK (1 << GPIO_SLEW_SHIFT) +# define GPIO_SLEW_STANDARD (0) +# define GPIO_SLEW_FAST GPIO_SLEW_MASK + +#define GPIO_I2CDRIVE_SHIFT (21) /* Bit 21: Driver slew rate */ +#define GPIO_I2CDRIVE_MASK (1 << GPIO_I2CDRIVE_SHIFT) +# define GPIO_I2CDRIVE_LOW (0) +# define GPIO_I2CDRIVE_HIGH GPIO_I2CDRIVE_MASK + +#define GPIO_OD_SHIFT (22) /* Bit 22: Controls open-drain mode */ +#define GPIO_OD_MASK (1 << GPIO_OD_SHIFT) +# define GPIO_PUSHPULL (0) +# define GPIO_OPENDRAIN GPIO_OD_MASK + +#define GPIO_I2CFILTEROFF_SHIFT (23) /* Bit 23: Configures I2C glitch filter */ +#define GPIO_I2CFILTEROFF_MASK (1 << GPIO_I2CFILTEROFF_SHIFT) +# define GPIO_I2C_FILTER_ON (0) +# define GPIO_I2C_FILTER_OFF GPIO_I2CFILTEROFF_MASK + +/* Pin Function bits: + * Only meaningful when the GPIO function is GPIO_PIN + * + * .... .... .... .... FFFF .... .... .... + */ + +#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */ +#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */ +# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */ +# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */ +# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO outpout pin */ +# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */ +# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */ +# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */ +# define GPIO_ALT4 (8 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 4 */ +# define GPIO_ALT5 (9 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 5 */ +# define GPIO_ALT6 (10 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 6 */ +# define GPIO_ALT7 (11 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 7 */ + +#define GPIO_EDGE_SHIFT (12) /* Bits 12-13: Interrupt edge bits */ +#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) + +#define GPIO_INOUT_MASK GPIO_OUTPUT +#define GPIO_FE_MASK GPIO_INTFE +#define GPIO_RE_MASK GPIO_INTRE + +#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT) +#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT) +#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) +#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) +#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0) +#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0) +#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) +#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0) +#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0) + +/* Pin Mode: MM + * + * .... .... .... .... .... MM.. .... .... + */ + +#define GPIO_MODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_FLOAT (IOCON_MODE_FLOAT << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDOWN (IOCON_MODE_PULLDOWN << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */ +# define GPIO_PULLUP (IOCON_MODE_PULLUP << GPIO_MODE_SHIFT) /* Pull-up resistor enabled */ +# define GPIO_REPEATER (IOCON_MODE_REPEATER << GPIO_MODE_SHIFT) /* Repeater mode enabled */ + +/* Initial value: V + */ + +#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */ +# define GPIO_VALUE_ONE GPIO_VALUE +# define GPIO_VALUE_ZERO (0) + +/* Port number: PPP (0-5) */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) + +/* Pin number: NNNNN (0-31) */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +typedef uint32_t lpc54_pinset_t; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: lpc54_gpio_irqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +void lpc54_gpio_irqinitialize(void); +#else +# define lpc54_gpio_irqinitialize() +#endif + +/************************************************************************************ + * Name: lpc54_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int lpc54_gpio_config(lpc54_pinset_t cfgset); + +/************************************************************************************ + * Name: lpc54_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void lpc54_gpio_write(lpc54_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: lpc54_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool lpc54_gpio_read(lpc54_pinset_t pinset); + +/************************************************************************************ + * Name: lpc54_gpio_irqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +void lpc54_gpio_irqenable(int irq); +#else +# define lpc54_gpio_irqenable(irq) +#endif + +/************************************************************************************ + * Name: lpc54_gpio_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +void lpc54_gpio_disable(int irq); +#else +# define lpc54_gpio_disable(irq) +#endif + +/************************************************************************************ + * Function: lpc54_gpio_dump + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int lpc54_gpio_dump(lpc54_pinset_t pinset, const char *msg); +#else +# define lpc54_gpio_dump(p,m) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_GPIO_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_irq.c b/arch/arm/src/lpc54xx/lpc54_irq.c index b282a1d442f..19b2c2f911b 100644 --- a/arch/arm/src/lpc54xx/lpc54_irq.c +++ b/arch/arm/src/lpc54xx/lpc54_irq.c @@ -370,15 +370,16 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC54_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif + #ifdef CONFIG_ARMV7M_USEBASEPRI lpc54_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif +#ifdef CONFIG_ARM_MPU /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ -#ifdef CONFIG_ARM_MPU irq_attach(LPC54_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(LPC54_IRQ_MEMFAULT); #endif @@ -399,20 +400,26 @@ void up_irqinitialize(void) lpc54_dumpnvic("initial", LPC54_IRQ_NIRQS); +#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI) /* If a debugger is connected, try to prevent it from catching hardfaults. * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal * operation. */ -#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI) regval = getreg32(NVIC_DEMCR); regval &= ~NVIC_DEMCR_VCHARDERR; putreg32(regval, NVIC_DEMCR); #endif - /* And finally, enable interrupts */ +#ifdef CONFIG_LPC54_GPIOIRQ + /* Initialize GPIO interrupts */ + + lpc54_gpio_irqinitialize(); +#endif #ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts */ + up_irq_enable(); #endif } diff --git a/configs/lpcxpresso-lpc54628/include/board.h b/configs/lpcxpresso-lpc54628/include/board.h index 6daaf643aef..2bad265e834 100644 --- a/configs/lpcxpresso-lpc54628/include/board.h +++ b/configs/lpcxpresso-lpc54628/include/board.h @@ -189,14 +189,20 @@ #define BOARD_D9 0 #define BOARD_D11 1 -#define BOARD_D12 2 -#define BOARD_NLEDS 3 +#ifndef CONFIG_ARCH_LEDS +# define BOARD_D12 2 +# define BOARD_NLEDS 3 +#else +# define BOARD_NLEDS 2 +#endif /* LED bits for use with board_userled_all() */ #define BOARD_D9_BIT (1 << BOARD_D9) #define BOARD_D11_BIT (1 << BOARD_D11) -#define BOARD_D12_BIT (1 << BOARD_D12) +#ifndef CONFIG_ARCH_LEDS +# define BOARD_D12_BIT (1 << BOARD_D12) +#endif /* These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is * defined. In that case, the usage by the board port is defined in @@ -215,6 +221,12 @@ #define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ #undef LED_IDLE /* Sleep mode indication not supported */ +/* After booting, LEDs D9 and D11 are avaible for use by the user. If the + * system booted properly, D9 and D11 should be OFF and D12 should be glowing + * to indicate that interrupts are occurring. If D12 is flash at 2Hz, then + * the system has crashed. + */ + /* Button definitions *******************************************************/ /* To be provided */ diff --git a/configs/lpcxpresso-lpc54628/src/Makefile b/configs/lpcxpresso-lpc54628/src/Makefile index 2a1bd0a8fcd..f305e1be1a0 100644 --- a/configs/lpcxpresso-lpc54628/src/Makefile +++ b/configs/lpcxpresso-lpc54628/src/Makefile @@ -36,7 +36,11 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc54_boot.c lpc54_bringup.c +CSRCS = lpc54_boot.c lpc54_bringup.c lpc54_userleds.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += lpc54_autoleds.c +endif ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc54_appinit.c diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c b/configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c new file mode 100644 index 00000000000..7dce4782d69 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + * + * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/lpc54_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * D9 D11 D12 + * LED_STARTED 0 OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF + * LED_STACKCREATED 3 OFF OFF OFF + * + * LED_INIRQ 4 NC NC ON (momentary) + * LED_SIGNAL 4 NC NC ON (momentary) + * LED_ASSERTION 4 NC NC ON (momentary) + * LED_PANIC 4 NC NC ON (2Hz flashing) + * LED_IDLE Sleep mode indication not supported + * + * After booting, LEDs D9 and D11 are avaible for use by the user. If the + * system booted properly, D9 and D11 should be OFF and D12 should be glowing + * to indicate that interrupts are occurring. If D12 is flash at 2Hz, then + * the system has crashed. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "lpc54_gpio.h" +#include "lpcxpresso-lpc54628.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + lpc54_gpio_config(GPIO_LED_D9); + lpc54_gpio_config(GPIO_LED_D11); + lpc54_gpio_config(GPIO_LED_D12); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + /* D9 and D11 are only changed during boot up states */ + + if ((unsigned int)led <= 3) + { + bool d9off = (led != 1); + bool d11off = (led != 2); + + lpc54_gpio_write(GPIO_LED_D9, d9off); /* Low illuminates */ + lpc54_gpio_write(GPIO_LED_D11, d11off); /* Low illuminates */ + lpc54_gpio_write(GPIO_LED_D12, true); /* Low illuminates */ + } + else + { + lpc54_gpio_write(GPIO_LED_D12, false); /* Low illuminates */ + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 4) + { + lpc54_gpio_write(GPIO_LED_D12, true); /* Low illuminates */ + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_boot.c b/configs/lpcxpresso-lpc54628/src/lpc54_boot.c index 3873d92bc8a..a6616884141 100644 --- a/configs/lpcxpresso-lpc54628/src/lpc54_boot.c +++ b/configs/lpcxpresso-lpc54628/src/lpc54_boot.c @@ -60,6 +60,11 @@ void lpc54_board_initialize(void) { +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif } /**************************************************************************** diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_userleds.c b/configs/lpcxpresso-lpc54628/src/lpc54_userleds.c new file mode 100644 index 00000000000..0710cc80427 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_userleds.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_userleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "lpc54_gpio.h" +#include "lpcxpresso-lpc54628.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#ifndef CONFIG_ARCH_LEDS + /* Configure LED GPIOs for output */ + + lpc54_gpio_config(GPIO_LED_D9); + lpc54_gpio_config(GPIO_LED_D11); + lpc54_gpio_config(GPIO_LED_D12); +#endif +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_D9) + { + lpc54_gpio_write(GPIO_LED_D9, !ledon); /* Low illuminates */ + } + else if (led == BOARD_D11) + { + lpc54_gpio_write(GPIO_LED_D11, !ledon); /* Low illuminates */ + } +#ifndef CONFIG_ARCH_LEDS + else if (led == BOARD_D12) + { + lpc54_gpio_write(GPIO_LED_D12, !ledon); /* Low illuminates */ + } +#endif +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + lpc54_gpio_write(GPIO_LED_D9, (ledset & BOARD_D9_BIT) == 0); + lpc54_gpio_write(GPIO_LED_D11, (ledset & BOARD_D11_BIT) == 0); +#ifndef CONFIG_ARCH_LEDS + lpc54_gpio_write(GPIO_LED_D12, (ledset & BOARD_D12_BIT) == 0); +#endif +} diff --git a/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h b/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h index ecc5148ba02..8575261aa03 100644 --- a/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h +++ b/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h @@ -46,8 +46,25 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* LED definitions **********************************************************/ -/* to be provided */ +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + */ + +#define GPIO_LED_D9 \ + (GPIO_PORT2 | GPIO_PIN2 | GPIO_VALUE_ONE | GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_PULLUP) + +#define GPIO_LED_D11 \ + (GPIO_PORT3 | GPIO_PIN3 | GPIO_VALUE_ONE | GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_PULLUP) + +#define GPIO_LED_D12 \ + (GPIO_PORT3 | GPIO_PIN14 | GPIO_VALUE_ONE | GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_PULLUP) /* Button definitions *******************************************************/ /* to be provided */