diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c
index 7d61e1b16f6..10df1da0211 100644
--- a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c
+++ b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c
@@ -155,13 +155,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure XOSC.
    */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
                                             ccfg_modeconf);
-#else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
-                                                  ccfg_modeconf);
-#endif
 
   /* Increased margin between digital supply voltage and VDD BOD during
    * standby. VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7)
@@ -216,11 +211,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure HPOSC. -Setup the LF clock.
    */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
-#else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
-#endif
 
   /* Allow AUX to power down */
 
@@ -316,11 +307,7 @@ void cc13xx_trim_device(void)
 
   /* Select correct CACHE mode and set correct CACHE configuration */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupSetCacheModeAccordingToCcfgSetting();
-#else
-  NOROM_SetupSetCacheModeAccordingToCcfgSetting();
-#endif
 
   /* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none
    * of the above. It is always assumed that the application will freeze the
diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
index b8aa90beae4..8c2a12e948e 100644
--- a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
+++ b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
@@ -264,13 +264,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure XOSC.
    */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
                                             ccfg_modeconf);
-#else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
-                                                  ccfg_modeconf);
-#endif
 
   /* Special shadow register trim propagation on first batch of devices */
 
@@ -460,11 +455,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure HPOSC. -Setup the LF clock.
    */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
-#else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
-#endif
 
   /* Set AUX into power down active mode */
 
@@ -537,11 +528,7 @@ void cc13xx_trim_device(void)
 
   /* Select correct CACHE mode and set correct CACHE configuration */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupSetCacheModeAccordingToCcfgSetting();
-#else
-  NOROM_SetupSetCacheModeAccordingToCcfgSetting();
-#endif
 
   /* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none
    * of the above. It is always assumed that the application will freeze the
diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
index f42a354493a..7c918411a3f 100644
--- a/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
+++ b/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
@@ -144,13 +144,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure XOSC.
    */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
                                             ccfg_modeconf);
-#else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
-                                                  ccfg_modeconf);
-#endif
 
   {
     uint32_t trimreg;
@@ -204,11 +199,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure HPOSC. -Setup the LF clock.
    */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
-#else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
-#endif
 
   /* Set AUX into power down active mode */
 
@@ -283,11 +274,7 @@ void cc13xx_trim_device(void)
 
   /* Select correct CACHE mode and set correct CACHE configuration */
 
-#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupSetCacheModeAccordingToCcfgSetting();
-#else
-  NOROM_SetupSetCacheModeAccordingToCcfgSetting();
-#endif
 
   /* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none
    * of the above. It is always assumed that the application will freeze the
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
index 1dbf5342781..bc9f17053c3 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
@@ -103,10 +103,7 @@
 #define TIVA_FLASH_CFG_BASE           0x50000000 /* CC26_DUMMY_COMP */
 #define TIVA_FCFG1_BASE               0x50001000 /* FCFG1 */
 #define TIVA_FCFG2_BASE               0x50002000 /* FCFG2 */
-#ifndef TIVA_CCFG_BASE
-#  define TIVA_CCFG_BASE              0x50003000 /* CCFG */
-#endif
-#define TIVA_CCFG_BASE_DEFAULT        0x50003000 /* CCFG */
+#define TIVA_CCFG_BASE                0x50003000 /* CCFG */
 #define TIVA_SSI0_NONBUF_BASE         0x60000000 /* SSI CPU nonbuf base */
 #define TIVA_UART0_NONBUF_BASE        0x60001000 /* UART CPU nonbuf base */
 #define TIVA_I2C0_NONBUF_BASE         0x60002000 /* I2C CPU nonbuf base */
diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h
index 32b718afc03..8d24ae96307 100644
--- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h
+++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h
@@ -113,10 +113,7 @@
 #define TIVA_FLASH_CFG_BASE           0x50000000 /* CC26_DUMMY_COMP */
 #define TIVA_FCFG1_BASE               0x50001000 /* FCFG1 */
 #define TIVA_FCFG2_BASE               0x50002000 /* FCFG2 */
-#ifndef TIVA_CCFG_BASE
-#  define TIVA_CCFG_BASE              0x50003000 /* CCFG */
-#endif
-#define TIVA_CCFG_BASE_DEFAULT        0x50003000 /* CCFG */
+#define TIVA_CCFG_BASE                0x50003000 /* CCFG */
 #define TIVA_SSI0_NONBUF_BASE         0x60000000 /* SSI CPU nonbuf base */
 #define TIVA_UART0_NONBUF_BASE        0x60001000 /* UART CPU nonbuf base */
 #define TIVA_I2C0_NONBUF_BASE         0x60002000 /* I2C CPU nonbuf base */