diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c
index d7514751fcd..893971ab6c9 100644
--- a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c
+++ b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/tiva/cc13xx/cc13x_start.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * This is a port of TI's setup.c file (revision 49363) which has a fully
@@ -125,7 +125,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
       regval = getreg32(TIVA_CCFG_MODE_CONF_1);
       regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
-      putreg8((uint8_t)regval, TIVA_ADI3_MASK4B + (ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
+      putreg8((uint8_t)regval, TIVA_ADI3_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
     }
 
   /* Enable for JTAG to be powered down(will still be powered on if debugger
@@ -149,7 +149,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure XOSC.
    */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
                                             ccfg_modeconf);
 #else
@@ -209,7 +209,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure HPOSC. -Setup the LF clock.
    */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
 #else
   NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
@@ -229,7 +229,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
   regval  = getreg32(TIVA_FLASH_CFG);
   regval |= FLASH_CFG_DIS_EFUSECLK;
-  putreg32(regval, TIVA_FLASH_CFG)
+  putreg32(regval, TIVA_FLASH_CFG);
 }
 
 /******************************************************************************
@@ -287,7 +287,7 @@ void cc13xx_trim_device(void)
 
   regval  = getreg32(TIVA_FLASH_CFG);
   regval &= ~FLASH_CFG_DIS_STANDBY;
-  putreg32(regval, TIVA_FLASH_CFG)
+  putreg32(regval, TIVA_FLASH_CFG);
 
   /* Clock must always be enabled for the semaphore module (due to ADI/DDI HW
    * workaround)
@@ -308,7 +308,7 @@ void cc13xx_trim_device(void)
 
   /* Select correct CACHE mode and set correct CACHE configuration */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupSetCacheModeAccordingToCcfgSetting();
 #else
   NOROM_SetupSetCacheModeAccordingToCcfgSetting();
diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
index f00940012df..b270cecb5fb 100644
--- a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
+++ b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
@@ -1,7 +1,7 @@
 /******************************************************************************
  * arch/arm/src/tiva/cc13xx/cc13x_start.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * This is a port of TI's setup.c file (revision 49363) which has a fully
@@ -54,6 +54,7 @@
 #include "hardware/tiva_aon_rtc.h"
 #include "hardware/tiva_adi2_refsys.h"
 #include "hardware/tiva_adi3_refsys.h"
+#include "hardware/tiva_adi4_aux.h"
 
 /******************************************************************************
  * Pre-processor Definitions
@@ -177,8 +178,8 @@ static void Step_VBG(int32_t target_signed)
             }
 
           ref_sysctl &= ~(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN |
-                          ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK)) |
-                          ((((uint32_t)current_signed) <<
+                          ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
+          ref_sysctl |= ((((uint32_t)current_signed) <<
                            ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT) &
                          ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
           putreg8(ref_sysctl, TIVA_ADI3_REFSYS_REFSYSCTL3);
@@ -223,7 +224,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
       regval = getreg32(TIVA_CCFG_MODE_CONF_1);
       regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
       putreg8((uint8_t)regval,
-              TIVA_ADI3_MASK4B + (ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
+              TIVA_ADI3_REFSYS_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
     }
 
   /* TBD - Temporarily removed for CC13x2 / CC26x2 */
@@ -237,7 +238,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
   regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
            (DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
-  putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (DDI0_OSC_CTL0_OFFSET << 1) + 4);
+  putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (TIVA_DDI0_OSC_CTL0_OFFSET << 1) + 4);
 
   /* Dummy read to ensure that the write has propagated */
 
@@ -257,7 +258,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure XOSC.
    */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
                                             ccfg_modeconf);
 #else
@@ -270,7 +271,6 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
   {
     uint32_t fusedata;
     uint32_t org_resetctl;
-    uint32_t regval;
     uint16_t regval16;
     uint8_t regval8;
 
@@ -295,7 +295,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
                (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_MASK) >>
                  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_SHIFT) <<
                 ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT));
-    putreg8(regval8, TIVA_ADI2_DIR + ADI2_REFSYS_SOCLDOCTL1_OFFSET);
+    putreg8(regval8, TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET);
 
     /* Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in
      * ADI2_REFSYS. Avoid using masked write access since bit field spans
@@ -306,7 +306,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
     regval8 = (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_MASK) >>
                 FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_SHIFT) <<
                ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT);
-    putreg8(regval8, TIVA_ADI2_DIR + ADI2_REFSYS_REFSYSCTL0_OFFSET);
+    putreg8(regval8, TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET);
 
     /* Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
      * ADI3_REFSYS
@@ -316,7 +316,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
                (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_MASK) >>
                  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_SHIFT) <<
                 ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT);
-    putreg16(regval16, TIVA_ADI3_MASK8B + (ADI3_REFSYS_REFSYSCTL2_OFFSET << 1));
+    putreg16(regval16, TIVA_ADI3_REFSYS_MASK8B +
+             (TIVA_ADI3_REFSYS_REFSYSCTL2_OFFSET << 1));
 
     /* Get TRIMBOD_EXTMODE or TRIMBOD_INTMODE from EFUSE shadow register in
      * FCFG1
@@ -325,8 +326,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
     fusedata = getreg32(TIVA_FCFG1_SHDW_ANA_TRIM);
 
     org_resetctl =
-      (getreg32(TIVA_AON_PMCTL_RESETCTL) &
-       ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK);
+      (getreg32(TIVA_AON_PMCTL_RESETCTL) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET);
 
     regval = (org_resetctl &
               ~(AON_PMCTL_RESETCTL_CLK_LOSS_EN | AON_PMCTL_RESETCTL_VDD_LOSS_EN |
@@ -357,7 +357,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
                           FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_SHIFT) <<
                          ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
             putreg16(regval16,
-                     TIVA_ADI3_MASK8B + (ADI3_REFSYS_REFSYSCTL1_OFFSET << 1));
+                     TIVA_ADI3_REFSYS_MASK8B +
+                     (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET << 1));
           }
         else
           {
@@ -370,7 +371,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
                           FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_SHIFT) <<
                          ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
             putreg16(regval16,
-                     TIVA_ADI3_MASK8B + (ADI3_REFSYS_REFSYSCTL1_OFFSET << 1));
+                     TIVA_ADI3_REFSYS_MASK8B +
+                     (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET << 1));
           }
 
         /* Load the new VDDS_BOD setting */
@@ -405,7 +407,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
     (void)getreg32(TIVA_AON_RTC_SYNCLF);
 
-    (void)getreg32(TIVA_AON_PMCTL_RESETCTL) = org_resetctl;
+    putreg32(org_resetctl, TIVA_AON_PMCTL_RESETCTL) ;
 
     /* Wait for xxx_LOSS_EN setting to propagate */
 
@@ -424,32 +426,32 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
     trimvalue = ((trimreg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_MASK) >>
                      FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_SHIFT);
 
-    regval8 = ((trimvalue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT) &
-               ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK);
-    putreg8(regval8, TIVA_AUX_ADI4_LPMBIAS);
+    regval8 = ((trimvalue << ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT) &
+               ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK);
+    putreg8(regval8, TIVA_ADI4_AUX_LPMBIAS);
 
     /* Set fixed LPM_BIAS values --- LPM_BIAS_BACKUP_EN = 1 and
      * LPM_BIAS_WIDTH_TRIM = 3
      */
 
     putreg8(ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
-           TIVA_ADI3_SET + ADI3_REFSYS_AUX_DEBUG_OFFSET);
+           TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_AUX_DEBUG_OFFSET);
 
     /* Set LPM_BIAS_WIDTH_TRIM = 3
      * Set mask (bits to be written) in [15:8]
      * Set value (in correct bit pos) in [7:0]
      */
 
-    regval16 = ((ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK << 8) |
-                (3 << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT));
-    putreg16(regval16, TIVA_AUX_ADI4_MASK8B + (ADI_4_AUX_COMP_OFFSET * 2));
+    regval16 = ((ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK << 8) |
+                (3 << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT));
+    putreg16(regval16, TIVA_ADI4_AUX_MASK8B + (TIVA_ADI4_AUX_COMP_OFFSET * 2));
   }
 
   /* Third part of trim done after cold reset and wakeup from shutdown:
    * -Configure HPOSC. -Setup the LF clock.
    */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
 #else
   NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
@@ -463,7 +465,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
   regval  = getreg32(TIVA_FLASH_CFG);
   regval |= FLASH_CFG_DIS_EFUSECLK;
-  putreg32(regval, TIVA_FLASH_CFG)
+  putreg32(regval, TIVA_FLASH_CFG);
 }
 
 /******************************************************************************
@@ -502,6 +504,7 @@ void cc13xx_trim_device(void)
 {
   uint32_t fcfg1_revision;
   uint32_t aon_sysresetctrl;
+  uint32_t regval;
 
   /* Get layout revision of the factory configuration area (Handle undefined
    * revision as revision = 0)
@@ -521,11 +524,11 @@ void cc13xx_trim_device(void)
 
   regval  = getreg32(TIVA_FLASH_CFG);
   regval &= ~FLASH_CFG_DIS_STANDBY;
-  putreg32(regval, TIVA_FLASH_CFG)
+  putreg32(regval, TIVA_FLASH_CFG);
 
   /* Select correct CACHE mode and set correct CACHE configuration */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupSetCacheModeAccordingToCcfgSetting();
 #else
   NOROM_SetupSetCacheModeAccordingToCcfgSetting();
@@ -601,18 +604,18 @@ void cc13xx_trim_device(void)
    * must be manually cleared
    */
 
-  if (((getreg32(TIVA_AON_PMCTL_RESETCTL) &
-        (AON_PMCTL_RESETCTL_BOOT_DET_1_MASK | AON_PMCTL_RESETCTL_BOOT_DET_0_MASK)) >>
-       AON_PMCTL_RESETCTL_BOOT_DET_0_SHIFT) == 1)
+  if ((getreg32(TIVA_AON_PMCTL_RESETCTL) &
+       (AON_PMCTL_RESETCTL_BOOT_DET_0 | AON_PMCTL_RESETCTL_BOOT_DET_1)) ==
+       AON_PMCTL_RESETCTL_BOOT_DET_0)
     {
-      aon_sysresetctrl = (getreg32(TIVA_AON_PMCTL_RESETCTL) &
-                          ~(AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_MASK |
-                            AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_MASK |
-                            AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK |
-                            AON_PMCTL_RESETCTL_BOOT_DET_0_SET_MASK |
-                            AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK));
+      aon_sysresetctrl  = getreg32(TIVA_AON_PMCTL_RESETCTL);
+      aon_sysresetctrl &= ~(AON_PMCTL_RESETCTL_BOOT_DET_1_CLR |
+                            AON_PMCTL_RESETCTL_BOOT_DET_0_CLR |
+                            AON_PMCTL_RESETCTL_BOOT_DET_1_SET |
+                            AON_PMCTL_RESETCTL_BOOT_DET_0_SET |
+                            AON_PMCTL_RESETCTL_MCU_WARM_RESET);
 
-      putreg32(aon_sysresetctrl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK,
+      putreg32(aon_sysresetctrl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET,
                TIVA_AON_PMCTL_RESETCTL);
       putreg32(aon_sysresetctrl, TIVA_AON_PMCTL_RESETCTL);
     }
diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
index 55b1603cbf9..e93c571039e 100644
--- a/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
+++ b/arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
@@ -1,7 +1,7 @@
 /******************************************************************************
  * arch/arm/src/tiva/cc13xx/cc13x_start.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * This is a port of TI's setup.c file (revision 49363) which has a fully
@@ -51,18 +51,7 @@
 #include "hardware/tiva_ddi0_osc.h"
 #include "hardware/tiva_aon_pmctl.h"
 #include "hardware/tiva_adi3_refsys.h"
-
-/******************************************************************************
- * Pre-processor Definitions
- ******************************************************************************/
-
-/* Temporarily adding these defines as they are missing in hw_adi_4_aux.h */
-
-#define ADI_4_AUX_LPMBIAS_OFFSET                  0x0000000e
-#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK      0x0000003f
-#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT     0
-#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT  3
-#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK   0x00000038
+#include "hardware/tiva_adi4_aux.h"
 
 /******************************************************************************
  * Private Functions
@@ -102,7 +91,8 @@ static void trim_wakeup_frompowerdown(void)
 
 static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 {
-  uint32_t ccfg_ModeConfReg;
+  uint32_t ccfg_modeconf;
+  uint32_t regval;
 
   /* Check in CCFG for alternative DCDC setting */
 
@@ -118,7 +108,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
       regval = getreg32(TIVA_CCFG_MODE_CONF_1);
       regval = (0xf0 | regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT);
       putreg8((uint8_t)regval,
-              TIVA_ADI3_MASK4B + (ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
+              TIVA_ADI3_REFSYS_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
     }
 
   /* TBD - Temporarily removed for CC13x2 / CC26x2 */
@@ -132,7 +122,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
   regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
           (DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
-  putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (DDI0_OSC_CTL0_OFFSET << 1) + 4);
+  putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (TIVA_DDI0_OSC_CTL0_OFFSET << 1) + 4);
 
   /* Dummy read to ensure that the write has propagated */
 
@@ -140,24 +130,24 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
   /* read the MODE_CONF register in CCFG */
 
-  ccfg_ModeConfReg = getreg32(TIVA_CCFG_MODE_CONF);
+  ccfg_modeconf = getreg32(TIVA_CCFG_MODE_CONF);
 
   /* First part of trim done after cold reset and wakeup from shutdown: -Adjust
    * the VDDR_TRIM_SLEEP value. -Configure DCDC.
    */
 
-  SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_ModeConfReg);
+  SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_modeconf);
 
   /* Second part of trim done after cold reset and wakeup from shutdown:
    * -Configure XOSC.
    */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
-                                            ccfg_ModeConfReg);
+                                            ccfg_modeconf);
 #else
   NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
-                                                  ccfg_ModeConfReg);
+                                                  ccfg_modeconf);
 #endif
 
   {
@@ -170,21 +160,21 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
     trimvalue = ((trimreg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_MASK) >>
                      FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_SHIFT);
 
-    regval = ((trimvalue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT) &
-              ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK);
-    putreg8((uint8_t)regval, TIVA_AUX_ADI4_LPMBIAS);
+    regval = ((trimvalue << ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT) &
+              ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK);
+    putreg8((uint8_t)regval, TIVA_ADI4_AUX_LPMBIAS);
 
     /* Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration */
 
     if (trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN)
       {
         putreg8(ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
-                TIVA_ADI3_SET + ADI3_REFSYS_AUX_DEBUG_OFFSET);
+                TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_AUX_DEBUG_OFFSET);
       }
     else
       {
         putreg8(ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
-                TIVA_ADI3_CLR + ADI3_REFSYS_AUX_DEBUG_OFFSET);
+                TIVA_ADI3_REFSYS_CLR + TIVA_ADI3_REFSYS_AUX_DEBUG_OFFSET);
       }
 
     /* Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration */
@@ -202,9 +192,10 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
        * Set value (in correct bit pos) in [7:0]
        */
 
-      regval16 = ((ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK << 8) |
-                  (trimwidth << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT));
-      putreg16(regval16, TIVA_AUX_ADI4_MASK8B + (ADI_4_AUX_COMP_OFFSET * 2));
+      regval16 = ((ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK << 8) |
+                  (trimwidth << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT));
+      putreg16(regval16,
+               TIVA_ADI4_AUX_MASK8B + (TIVA_ADI4_AUX_COMP_OFFSET * 2));
     }
   }
 
@@ -212,10 +203,10 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
    * -Configure HPOSC. -Setup the LF clock.
    */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
-  SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_ModeConfReg);
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
+  SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
 #else
-  NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_ModeConfReg);
+  NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
 #endif
 
   /* Set AUX into power down active mode */
@@ -226,7 +217,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
 
   regval  = getreg32(TIVA_FLASH_CFG);
   regval |= FLASH_CFG_DIS_EFUSECLK;
-  putreg32(regval, TIVA_FLASH_CFG)
+  putreg32(regval, TIVA_FLASH_CFG);
 }
 
 /******************************************************************************
@@ -265,6 +256,7 @@ void cc13xx_trim_device(void)
 {
   uint32_t fcfg1_revision;
   uint32_t aon_sysresetctrl;
+  uint32_t regval;
 
   /* Get layout revision of the factory configuration area (Handle undefined
    * revision as revision = 0)
@@ -286,11 +278,11 @@ void cc13xx_trim_device(void)
 
   regval  = getreg32(TIVA_FLASH_CFG);
   regval &= ~FLASH_CFG_DIS_STANDBY;
-  putreg32(regval, TIVA_FLASH_CFG)
+  putreg32(regval, TIVA_FLASH_CFG);
 
   /* Select correct CACHE mode and set correct CACHE configuration */
 
-#if TIVA_CCFG_BASE == CCFG_BASE_DEFAULT
+#if TIVA_CCFG_BASE == TIVA_CCFG_BASE_DEFAULT
   SetupSetCacheModeAccordingToCcfgSetting();
 #else
   NOROM_SetupSetCacheModeAccordingToCcfgSetting();
@@ -366,18 +358,18 @@ void cc13xx_trim_device(void)
    * must be manually cleared
    */
 
-  if (((getreg32(TIVA_AON_PMCTL_RESETCTL) &
-        (AON_PMCTL_RESETCTL_BOOT_DET_1_MASK | AON_PMCTL_RESETCTL_BOOT_DET_0_MASK)) >>
-       AON_PMCTL_RESETCTL_BOOT_DET_0_SHIFT) == 1)
+  if ((getreg32(TIVA_AON_PMCTL_RESETCTL) &
+       (AON_PMCTL_RESETCTL_BOOT_DET_0 | AON_PMCTL_RESETCTL_BOOT_DET_1)) ==
+       AON_PMCTL_RESETCTL_BOOT_DET_0)
     {
-      aon_sysresetctrl = (getreg32(TIVA_AON_PMCTL_RESETCTL) &
-                            ~(AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_MASK |
-                              AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_MASK |
-                              AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK |
-                              AON_PMCTL_RESETCTL_BOOT_DET_0_SET_MASK |
-                              AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK));
+      aon_sysresetctrl  = getreg32(TIVA_AON_PMCTL_RESETCTL);
+      aon_sysresetctrl &= ~(AON_PMCTL_RESETCTL_BOOT_DET_1_CLR |
+                            AON_PMCTL_RESETCTL_BOOT_DET_0_CLR |
+                            AON_PMCTL_RESETCTL_BOOT_DET_1_SET |
+                            AON_PMCTL_RESETCTL_BOOT_DET_0_SET |
+                            AON_PMCTL_RESETCTL_MCU_WARM_RESET);
 
-      putreg32(aon_sysresetctrl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK,
+      putreg32(aon_sysresetctrl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET,
                TIVA_AON_PMCTL_RESETCTL);
       putreg32(aon_sysresetctrl, TIVA_AON_PMCTL_RESETCTL);
     }
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
index 8f957161654..cbeb75b6526 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
@@ -78,6 +78,15 @@
 #define TIVA_ADI2_REFSYS_HPOSCCTL1                           (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET)
 #define TIVA_ADI2_REFSYS_HPOSCCTL2                           (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET)
 
+/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
+
+#define TIVA_ADI2_REFSYS_DIR                                 (TIVA_ADI2_BASE + TIVA_DDI_DIR_OFFSET)
+#define TIVA_ADI2_REFSYS_SET                                 (TIVA_ADI2_BASE + TIVA_DDI_SET_OFFSET)
+#define TIVA_ADI2_REFSYS_CLR                                 (TIVA_ADI2_BASE + TIVA_DDI_CLR_OFFSET)
+#define TIVA_ADI2_REFSYS_MASK4B                              (TIVA_ADI2_BASE + TIVA_DDI_MASK4B_OFFSET)
+#define TIVA_ADI2_REFSYS_MASK8B                              (TIVA_ADI2_BASE + TIVA_DDI_MASK8B_OFFSET)
+#define TIVA_ADI2_REFSYS_MASK16B                             (TIVA_ADI2_BASE + TIVA_DDI_MASK16B_OFFSET)
+
 /* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
 
 /* TIVA_ADI2_REFSYS_REFSYSCTL0 */
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
index a0274bc064a..e4fe23b7a48 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
@@ -80,6 +80,15 @@
 #define TIVA_ADI3_REFSYS_DCDCCTL4                             (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET)
 #define TIVA_ADI3_REFSYS_DCDCCTL5                             (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET)
 
+/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */
+
+#define TIVA_ADI3_REFSYS_DIR                                  (TIVA_ADI3_BASE + TIVA_DDI_DIR_OFFSET)
+#define TIVA_ADI3_REFSYS_SET                                  (TIVA_ADI3_BASE + TIVA_DDI_SET_OFFSET)
+#define TIVA_ADI3_REFSYS_CLR                                  (TIVA_ADI3_BASE + TIVA_DDI_CLR_OFFSET)
+#define TIVA_ADI3_REFSYS_MASK4B                               (TIVA_ADI3_BASE + TIVA_DDI_MASK4B_OFFSET)
+#define TIVA_ADI3_REFSYS_MASK8B                               (TIVA_ADI3_BASE + TIVA_DDI_MASK8B_OFFSET)
+#define TIVA_ADI3_REFSYS_MASK16B                              (TIVA_ADI3_BASE + TIVA_DDI_MASK16B_OFFSET)
+
 /* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
 
 /* TIVA_ADI3_REFSYS_SPARE0 */
@@ -171,7 +180,7 @@
 #  define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_DEFAULT              (0 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)  /* Default, about 1.63V */
 #  define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL              (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)  /* Typical voltage after trim voltage 1.71V */
 #  define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX                  (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */
-#  define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN               (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V
+#  define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN               (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V */
 #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT                  (5)       /* Bits 5-7:  Set charge and re-charge current level */
                                                                         /*            2's complement encoding */
 #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK                   (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
new file mode 100644
index 00000000000..3b9b4291fa9
--- /dev/null
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
@@ -0,0 +1,248 @@
+/********************************************************************************************************************
+ * arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Technical content derives from a TI header file that has a compatible BSD license:
+ *
+ *   Copyright (c) 2015-2017, Texas Instruments Incorporated
+ *   All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI4_AUX_H
+#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI4_AUX_H
+
+/********************************************************************************************************************
+ * Included Files
+ ********************************************************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/tiva_memorymap.h"
+
+/********************************************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************************************/
+
+/* ADI3 AUX Register Offsets ****************************************************************************************/
+
+#define TIVA_ADI4_AUX_MUX0_OFFSET                          0x0000
+#define TIVA_ADI4_AUX_MUX1_OFFSET                          0x0001
+#define TIVA_ADI4_AUX_MUX2_OFFSET                          0x0002
+#define TIVA_ADI4_AUX_MUX3_OFFSET                          0x0003
+#define TIVA_ADI4_AUX_ISRC_OFFSET                          0x0004  /* Current Source */
+#define TIVA_ADI4_AUX_COMP_OFFSET                          0x0005  /* Comparator */
+#define TIVA_ADI4_AUX_MUX4_OFFSET                          0x0007
+#define TIVA_ADI4_AUX_ADC0_OFFSET                          0x0008  /* ADC Control 0 */
+#define TIVA_ADI4_AUX_ADC1_OFFSET                          0x0009  /* ADC Control 1 */
+#define TIVA_ADI4_AUX_ADCREF0_OFFSET                       0x000a  /* ADC Reference 0 */
+#define TIVA_ADI4_AUX_ADCREF1_OFFSET                       0x000b  /* ADC Reference 1 */
+
+/* ADI3 AUX Register Addresses **************************************************************************************/
+
+#define TIVA_ADI4_AUX_MUX0                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX0_OFFSET)
+#define TIVA_ADI4_AUX_MUX1                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX1_OFFSET)
+#define TIVA_ADI4_AUX_MUX2                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX2_OFFSET)
+#define TIVA_ADI4_AUX_MUX3                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX3_OFFSET)
+#define TIVA_ADI4_AUX_ISRC                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ISRC_OFFSET)
+#define TIVA_ADI4_AUX_COMP                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_COMP_OFFSET)
+#define TIVA_ADI4_AUX_MUX4                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX4_OFFSET)
+#define TIVA_ADI4_AUX_ADC0                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADC0_OFFSET)
+#define TIVA_ADI4_AUX_ADC1                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADC1_OFFSET)
+#define TIVA_ADI4_AUX_ADCREF0                              (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF0_OFFSET)
+#define TIVA_ADI4_AUX_ADCREF1                              (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF1_OFFSET)
+
+/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */
+
+#define TIVA_ADI4_AUX_DIR                                  (TIVA_AUX_ADI4_BASE + TIVA_DDI_DIR_OFFSET)
+#define TIVA_ADI4_AUX_SET                                  (TIVA_AUX_ADI4_BASE + TIVA_DDI_SET_OFFSET)
+#define TIVA_ADI4_AUX_CLR                                  (TIVA_AUX_ADI4_BASE + TIVA_DDI_CLR_OFFSET)
+#define TIVA_ADI4_AUX_MASK4B                               (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK4B_OFFSET)
+#define TIVA_ADI4_AUX_MASK8B                               (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK8B_OFFSET)
+#define TIVA_ADI4_AUX_MASK16B                              (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK16B_OFFSET)
+
+/* ADI3 AUX Register Bitfield Definitions ***************************************************************************/
+
+/* TIVA_ADI4_AUX_MUX0 */
+
+#define ADI4_AUX_MUX0_COMPA_REF_SHIFT                      (0)       /* Bits 0-3 */
+#define ADI4_AUX_MUX0_COMPA_REF_MASK                       (15 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF(n)                       ((uint32_t)(n) << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_NC                       (0 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_DCOUPL                   (1 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_VSS                      (2 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_VDDS                     (4 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_ADCVREFP                 (8 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+
+/* TIVA_ADI4_AUX_MUX1 */
+
+#define ADI4_AUX_MUX1_COMPA_IN_SHIFT                       (0)       /* Bit 0-7 */
+#define ADI4_AUX_MUX1_COMPA_IN_MASK                        (0xff << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN(n)                        ((uint32_t)(n) << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_NC                        (0   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO7                    (1   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO6                    (2   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO5                    (4   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO4                    (8   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO3                    (16  << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO1                    (32  << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO1                    (64  << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO0                    (128 << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+
+/* TIVA_ADI4_AUX_MUX2 */
+
+#define ADI4_AUX_MUX2_COMPB_REF_SHIFT                      (0)       /* Bits 0-2 */
+#define ADI4_AUX_MUX2_COMPB_REF_MASK                       (7 << ADI4_AUX_MUX2_COMPB_REF_SHIFT)
+#  define ADI4_AUX_MUX2_COMPB_REF(n)                       ((uint32_t)(n) << ADI4_AUX_MUX2_COMPB_REF_SHIFT)
+#  define ADI4_AUX_MUX2_COMPB_REF_NC                       (0 << ADI4_AUX_MUX2_COMPB_REF_SHIFT)
+#  define ADI4_AUX_MUX2_COMPB_REF_DCOUPL                   (1 << ADI4_AUX_MUX2_COMPB_REF_SHIFT)
+#  define ADI4_AUX_MUX2_COMPB_REF_VSS                      (2 << ADI4_AUX_MUX2_COMPB_REF_SHIFT)
+#  define ADI4_AUX_MUX2_COMPB_REF_VDDS                     (4 << ADI4_AUX_MUX2_COMPB_REF_SHIFT)
+#define ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT                    (3)       /* Bits 3-7 */
+#define ADI4_AUX_MUX2_ADCCOMPB_IN_MASK                     (31 << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN(n)                     ((uint32_t)(n) << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_NC                     (0  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_ATEST0                 (1  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_ATEST1                 (2  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_DCOUPL                 (4  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_VSS                    (8  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_VDDS                   (16 << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+
+/* TIVA_ADI4_AUX_MUX3 */
+
+#define ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT                     (0)       /* Bits 0-7 */
+#define ADI4_AUX_MUX3_ADCCOMPB_IN_MASK                      (0xff << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN(n)                      ((uint32_t)(n) << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_NC                      (0   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO7                  (1   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO6                  (2   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO5                  (4   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO4                  (8   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO3                  (16  << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO2                  (32  << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO1                  (64  << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO0                  (128 << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+
+/* TIVA_ADI4_AUX_ISRC */
+
+#define ADI4_AUX_ISRC_EN                                    (1 << 0)  /* Bit 0:  Current source enable */
+#define ADI4_AUX_ISRC_TRIM_SHIFT                            (2)       /* Bits 2-7: Adjust current from current source */
+#define ADI4_AUX_ISRC_TRIM_MASK                             (0x3f << ADI4_AUX_ISRC_TRIM_SHIFT)
+#  define ADI4_AUX_ISRC_TRIM(n)                             ((uint32_t)(n) << ADI4_AUX_ISRC_TRIM_SHIFT)
+#  define ADI4_AUX_ISRC_TRIM_NC                             (0  << ADI4_AUX_ISRC_TRIM_SHIFT) /* No current connected */
+#  define ADI4_AUX_ISRC_TRIM_0p25U                          (1  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 0.25 uA */
+#  define ADI4_AUX_ISRC_TRIM_0p5U                           (2  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 0.5 uA */
+#  define ADI4_AUX_ISRC_TRIM_1p0U                           (4  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 1.0 uA */
+#  define ADI4_AUX_ISRC_TRIM_2p0U                           (8  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 2.0 uA */
+#  define ADI4_AUX_ISRC_TRIM_4p5U                           (16 << ADI4_AUX_ISRC_TRIM_SHIFT) /* 4.5 uA */
+#  define ADI4_AUX_ISRC_TRIM_11p75U                         (32 << ADI4_AUX_ISRC_TRIM_SHIFT) /* 11.75 uA */
+
+/* TIVA_ADI4_AUX_COMP */
+
+#define ADI4_AUX_COMP_COMPA_EN                              (1 << 1)  /* Bit 1:  COMPA enable */
+#define ADI4_AUX_COMP_COMPB_EN                              (1 << 2)  /* Bit 2:  COMPB enable */
+#define ADI4_AUX_COMP_COMPB_TRIM_SHIFT                      (3)       /* Bits 3-5 */
+#define ADI4_AUX_COMP_COMPB_TRIM_MASK                       (7 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT)
+#  define ADI4_AUX_COMP_COMPB_TRIM(n)                       ((uint32_t)(n) << ADI4_AUX_COMP_COMPB_TRIM_SHIFT)
+#  define ADI4_AUX_COMP_COMPB_TRIM_DIV1                     (0 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* No reference division */
+#  define ADI4_AUX_COMP_COMPB_TRIM_DIV2                     (1 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* Divide reference by 2 */
+#  define ADI4_AUX_COMP_COMPB_TRIM_DIV3                     (3 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* Divide reference by 3 */
+#  define ADI4_AUX_COMP_COMPB_TRIM_DIV4                     (7 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* Divide reference by 4 */
+#define ADI4_AUX_COMP_COMPA_REF_CURR_EN                     (1 << 6)  /* Bit 6:  Enables 2uA IPTAT current from ISRC to COMPA reference */
+#define ADI4_AUX_COMP_COMPA_REF_RES_EN                      (1 << 7)  /* Bit 7:  Enables 400kohm resistance from COMPA reference */
+
+/* TIVA_ADI4_AUX_MUX4 */
+
+#define ADI4_AUX_MUX4_COMPA_REF_SHIFT                       (0)       /* Bits 0-7 */
+#define ADI4_AUX_MUX4_COMPA_REF_MASK                        (0xff << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF(n)                        ((uint32_t)(n) << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_NC                        (0   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO7                    (1   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO6                    (2   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO5                    (4   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO4                    (8   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO3                    (16  << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO2                    (32  << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO1                    (64  << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO0                    (128 << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+
+/* TIVA_ADI4_AUX_ADC0 */
+
+#define ADI4_AUX_ADC0_EN                                    (1 << 0)  /* Bit 0:  ADC Enable */
+#define ADI4_AUX_ADC0_RESET_N                               (1 << 1)  /* Bit 1:  Reset ADC digital subchip, active low */
+#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT                  (3)       /* Bits 3-6: Controls the sampling duration
+                                                                       * before conversion when the ADC is operated
+                                                                       * in synchronous mode (SMPL_MODE = 0) */
+#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_MASK                   (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT)
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP(n)                   ((uint32_t)(n) << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT)
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p7_US               (3  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16 clocks = 2.7us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_5p3_US               (4  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 32 clocks = 5.3us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_10p6_US              (5  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 64 clocks = 10.6us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_21p3_US              (6  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 128 clocks = 21.3us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_42p6_US              (7  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 256 clocks = 42.6us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_85p3_US              (8  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 512 clocks = 85.3us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_170_US               (9  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 1024 clocks = 170us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_341_US               (10 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 2048 clocks = 341us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_682_US               (11 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 4096 clocks = 682us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_1p37_MS              (12 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 8192 clocks = 1.37ms */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p73_MS              (13 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16384 clocks = 2.73ms */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_5p46_MS              (14 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 32768 clocks = 5.46ms */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_10p9_MS              (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 65536 clocks = 10.9ms */
+#define ADI4_AUX_ADC0_SMPL_MODE                             (1 << 7)  /* Bit 7:  ADC Sampling mode */
+#  define ADI4_AUX_ADC0_SMPL_MODE_SYNCH                     (0)
+#  define ADI4_AUX_ADC0_SMPL_MODE_ASYNCH                    ADI4_AUX_ADC0_SMPL_MODE
+
+/* TIVA_ADI4_AUX_ADC1 */
+
+#define ADI4_AUX_ADC1_SCALE_DIS                             (1 << 0)  /* Bit 0 */
+
+/* TIVA_ADI4_AUX_ADCREF0 */
+
+#define ADI4_AUX_ADCREF0_EN                                 (1 << 0)  /* Bit 0:  ADC reference module enable */
+#define ADI4_AUX_ADCREF0_SRC                                (1 << 3)  /* Bit 3:  ADC reference source */
+#  define ADI4_AUX_ADCREF0_SRC_FIXED                        0
+#  define ADI4_AUX_ADCREF0_SRC_RELATIVE                     ADI4_AUX_ADCREF0_SRC
+#define ADI4_AUX_ADCREF0_EXT                                (1 << 4)  /* Bit 4 */
+#define ADI4_AUX_ADCREF0_IOMUX                              (1 << 5)  /* Bit 5 */
+#define ADI4_AUX_ADCREF0_REF_ON_IDLE                        (1 << 6)  /* Bit 6:  Enable ADCREF in IDLE state */
+
+
+/* TIVA_ADI4_AUX_ADCREF1 */
+
+#define ADI4_AUX_ADCREF1_VTRIM_SHIFT                        (0)       /* Bits 0-5: Trim output voltage of ADC fixed
+                                                                       * reference (64 steps, 2's complement) */
+#define ADI4_AUX_ADCREF1_VTRIM_MASK                         (0x3f << ADI4_AUX_ADCREF1_VTRIM_SHIFT)
+#  define ADI4_AUX_ADCREF1_VTRIM(n)                         ((uint32_t)(n) << ADI4_AUX_ADCREF1_VTRIM_SHIFT)
+#  define ADI4_AUX_ADCREF1_VTRIM_NOMINAL                    (0x00 << ADI4_AUX_ADCREF1_VTRIM_SHIFT) /* Nominal voltage 1.43V */
+#  define ADI4_AUX_ADCREF1_VTRIM_MAX                        (0x1f << ADI4_AUX_ADCREF1_VTRIM_SHIFT) /* Maximum voltage 1.6V */
+#  define ADI4_AUX_ADCREF1_VTRIM_MIN                        (0x20 << ADI4_AUX_ADCREF1_VTRIM_SHIFT) /* Minimum voltage 1.3V */
+
+#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI4_AUX_H */
diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
index 0571b3f512f..7657da6aee4 100644
--- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
+++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
@@ -1,7 +1,7 @@
 /********************************************************************************************************************
  * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *
  * Technical content derives from a TI header file that has a compatible BSD license:
@@ -78,6 +78,15 @@
 #define TIVA_ADI2_REFSYS_HPOSCCTL1                           (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET)
 #define TIVA_ADI2_REFSYS_HPOSCCTL2                           (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET)
 
+/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
+
+#define TIVA_ADI2_REFSYS_DIR                                 (TIVA_ADI2_BASE + TIVA_DDI_DIR_OFFSET)
+#define TIVA_ADI2_REFSYS_SET                                 (TIVA_ADI2_BASE + TIVA_DDI_SET_OFFSET)
+#define TIVA_ADI2_REFSYS_CLR                                 (TIVA_ADI2_BASE + TIVA_DDI_CLR_OFFSET)
+#define TIVA_ADI2_REFSYS_MASK4B                              (TIVA_ADI2_BASE + TIVA_DDI_MASK4B_OFFSET)
+#define TIVA_ADI2_REFSYS_MASK8B                              (TIVA_ADI2_BASE + TIVA_DDI_MASK8B_OFFSET)
+#define TIVA_ADI2_REFSYS_MASK16B                             (TIVA_ADI2_BASE + TIVA_DDI_MASK16B_OFFSET)
+
 /* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
 
 /* TIVA_ADI2_REFSYS_REFSYSCTL0 */
diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
index f27a54ed4d6..3bc7a4447da 100644
--- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
+++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
@@ -1,7 +1,7 @@
 /********************************************************************************************************************
  * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *
  * Technical content derives from a TI header file that has a compatible BSD license:
@@ -86,6 +86,15 @@
 #define TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP0                    (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP0_OFFSET)
 #define TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP1                    (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP1_OFFSET)
 
+/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
+
+#define TIVA_ADI3_REFSYS_DIR                                  (TIVA_ADI3_BASE + TIVA_DDI_DIR_OFFSET)
+#define TIVA_ADI3_REFSYS_SET                                  (TIVA_ADI3_BASE + TIVA_DDI_SET_OFFSET)
+#define TIVA_ADI3_REFSYS_CLR                                  (TIVA_ADI3_BASE + TIVA_DDI_CLR_OFFSET)
+#define TIVA_ADI3_REFSYS_MASK4B                               (TIVA_ADI3_BASE + TIVA_DDI_MASK4B_OFFSET)
+#define TIVA_ADI3_REFSYS_MASK8B                               (TIVA_ADI3_BASE + TIVA_DDI_MASK8B_OFFSET)
+#define TIVA_ADI3_REFSYS_MASK16B                              (TIVA_ADI3_BASE + TIVA_DDI_MASK16B_OFFSET)
+
 /* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
 
 /* TIVA_ADI3_REFSYS_ATESTCTL1 */
@@ -191,7 +200,7 @@
 #  define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_DEFAULT              (0 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)  /* Default, about 1.63V */
 #  define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL              (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)  /* Typical voltage after trim voltage 1.71V */
 #  define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX                  (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */
-#  define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN               (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V
+#  define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN               (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V */
 #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT                  (5)       /* Bits 5-7:  Set charge and re-charge current level */
                                                                         /*            2's complement encoding */
 #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK                   (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h
new file mode 100644
index 00000000000..18a38fcb206
--- /dev/null
+++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h
@@ -0,0 +1,265 @@
+/********************************************************************************************************************
+ * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Technical content derives from a TI header file that has a compatible BSD license:
+ *
+ *   Copyright (c) 2015-2017, Texas Instruments Incorporated
+ *   All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI4_AUX_H
+#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI4_AUX_H
+
+/********************************************************************************************************************
+ * Included Files
+ ********************************************************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/tiva_memorymap.h"
+
+/********************************************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************************************/
+
+/* ADI3 AUX Register Offsets ****************************************************************************************/
+
+#define TIVA_ADI4_AUX_MUX0_OFFSET                          0x0000
+#define TIVA_ADI4_AUX_MUX1_OFFSET                          0x0001
+#define TIVA_ADI4_AUX_MUX2_OFFSET                          0x0002
+#define TIVA_ADI4_AUX_MUX3_OFFSET                          0x0003
+#define TIVA_ADI4_AUX_ISRC_OFFSET                          0x0004  /* Current Source */
+#define TIVA_ADI4_AUX_COMP_OFFSET                          0x0005  /* Comparator */
+#define TIVA_ADI4_AUX_MUX4_OFFSET                          0x0007
+#define TIVA_ADI4_AUX_ADC0_OFFSET                          0x0008  /* ADC Control 0 */
+#define TIVA_ADI4_AUX_ADC1_OFFSET                          0x0009  /* ADC Control 1 */
+#define TIVA_ADI4_AUX_ADCREF0_OFFSET                       0x000a  /* ADC Reference 0 */
+#define TIVA_ADI4_AUX_ADCREF1_OFFSET                       0x000b  /* ADC Reference 1 */
+
+#ifdef CONFIG_ARCH_CHIP_CC13XX_V2
+#  define TIVA_ADI4_AUX_LPMBIAS_OFFSET                     0x000e
+#endif
+
+/* ADI3 AUX Register Addresses **************************************************************************************/
+
+#define TIVA_ADI4_AUX_MUX0                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX0_OFFSET)
+#define TIVA_ADI4_AUX_MUX1                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX1_OFFSET)
+#define TIVA_ADI4_AUX_MUX2                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX2_OFFSET)
+#define TIVA_ADI4_AUX_MUX3                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX3_OFFSET)
+#define TIVA_ADI4_AUX_ISRC                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ISRC_OFFSET)
+#define TIVA_ADI4_AUX_COMP                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_COMP_OFFSET)
+#define TIVA_ADI4_AUX_MUX4                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX4_OFFSET)
+#define TIVA_ADI4_AUX_ADC0                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADC0_OFFSET)
+#define TIVA_ADI4_AUX_ADC1                                 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADC1_OFFSET)
+#define TIVA_ADI4_AUX_ADCREF0                              (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF0_OFFSET)
+#define TIVA_ADI4_AUX_ADCREF1                              (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF1_OFFSET)
+
+#ifdef CONFIG_ARCH_CHIP_CC13XX_V2
+#  define TIVA_ADI4_AUX_LPMBIAS                            (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_LPMBIAS_OFFSET)
+#endif
+
+/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
+
+#define TIVA_ADI4_AUX_DIR                                  (TIVA_AUX_ADI4_BASE + TIVA_DDI_DIR_OFFSET)
+#define TIVA_ADI4_AUX_SET                                  (TIVA_AUX_ADI4_BASE + TIVA_DDI_SET_OFFSET)
+#define TIVA_ADI4_AUX_CLR                                  (TIVA_AUX_ADI4_BASE + TIVA_DDI_CLR_OFFSET)
+#define TIVA_ADI4_AUX_MASK4B                               (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK4B_OFFSET)
+#define TIVA_ADI4_AUX_MASK8B                               (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK8B_OFFSET)
+#define TIVA_ADI4_AUX_MASK16B                              (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK16B_OFFSET)
+
+/* ADI3 AUX Register Bitfield Definitions ***************************************************************************/
+
+/* TIVA_ADI4_AUX_MUX0 */
+
+#define ADI4_AUX_MUX0_COMPA_REF_SHIFT                      (0)       /* Bits 0-3 */
+#define ADI4_AUX_MUX0_COMPA_REF_MASK                       (15 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF(n)                       ((uint32_t)(n) << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_NC                       (0 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_DCOUPL                   (1 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_VSS                      (2 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_VDDS                     (4 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX0_COMPA_REF_ADCVREFP                 (8 << ADI4_AUX_MUX0_COMPA_REF_SHIFT)
+#define ADI4_AUX_MUX0_ADCCOMPB_IN                          (1 << 6)  /* Bit 6 */;
+#  define ADI4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V              ADI4_AUX_MUX0_ADCCOMPB_IN
+#  define ADI4_AUX_MUX0_ADCCOMPB_IN_NC                     (0)
+
+/* TIVA_ADI4_AUX_MUX1 */
+
+#define ADI4_AUX_MUX1_COMPA_IN_SHIFT                       (0)       /* Bit 0-7 */
+#define ADI4_AUX_MUX1_COMPA_IN_MASK                        (0xff << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN(n)                        ((uint32_t)(n) << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_NC                        (0   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO26                   (1   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO25                   (2   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO24                   (4   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO23                   (8   << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO22                   (16  << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO21                   (32  << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO20                   (64  << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+#  define ADI4_AUX_MUX1_COMPA_IN_AUXIO19                   (128 << ADI4_AUX_MUX1_COMPA_IN_SHIFT)
+
+/* TIVA_ADI4_AUX_MUX2 */
+
+#define ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT                   (0)       /* Bits 0-2 */
+#define ADI4_AUX_MUX2_DAC_VREF_SEL_MASK                    (7 << ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT)
+#  define ADI4_AUX_MUX2_DAC_VREF_SEL(n)                    ((uint32_t)(n) << ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT)
+#  define ADI4_AUX_MUX2_DAC_VREF_SEL_NC                    (0 << ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT)
+#  define ADI4_AUX_MUX2_DAC_VREF_SEL_DCOUPL                (1 << ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT)
+#  define ADI4_AUX_MUX2_DAC_VREF_SEL_ADCREF                (2 << ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT)
+#  define ADI4_AUX_MUX2_DAC_VREF_SEL_VDDS                  (4 << ADI4_AUX_MUX2_DAC_VREF_SEL_SHIFT)
+#define ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT                    (3)       /* Bits 3-7 */
+#define ADI4_AUX_MUX2_ADCCOMPB_IN_MASK                     (31 << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN(n)                     ((uint32_t)(n) << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_NC                     (0  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_ATEST0                 (1  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_ATEST1                 (2  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_DCOUPL                 (4  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_VSS                    (8  << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX2_ADCCOMPB_IN_VDDS                   (16 << ADI4_AUX_MUX2_ADCCOMPB_IN_SHIFT)
+
+/* TIVA_ADI4_AUX_MUX3 */
+
+#define ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT                     (0)       /* Bits 0-7 */
+#define ADI4_AUX_MUX3_ADCCOMPB_IN_MASK                      (0xff << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN(n)                      ((uint32_t)(n) << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_NC                      (0   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO26                 (1   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO25                 (2   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO24                 (4   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO23                 (8   << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO22                 (16  << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO21                 (32  << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO20                 (64  << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+#  define ADI4_AUX_MUX3_ADCCOMPB_IN_AUXIO19                 (128 << ADI4_AUX_MUX3_ADCCOMPB_IN_SHIFT)
+
+/* TIVA_ADI4_AUX_ISRC */
+
+#define ADI4_AUX_ISRC_EN                                    (1 << 0)  /* Bit 0:  Current source enable */
+#define ADI4_AUX_ISRC_TRIM_SHIFT                            (2)       /* Bits 2-7: Adjust current from current source */
+#define ADI4_AUX_ISRC_TRIM_MASK                             (0x3f << ADI4_AUX_ISRC_TRIM_SHIFT)
+#  define ADI4_AUX_ISRC_TRIM(n)                             ((uint32_t)(n) << ADI4_AUX_ISRC_TRIM_SHIFT)
+#  define ADI4_AUX_ISRC_TRIM_NC                             (0  << ADI4_AUX_ISRC_TRIM_SHIFT) /* No current connected */
+#  define ADI4_AUX_ISRC_TRIM_0p25U                          (1  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 0.25 uA */
+#  define ADI4_AUX_ISRC_TRIM_0p5U                           (2  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 0.5 uA */
+#  define ADI4_AUX_ISRC_TRIM_1p0U                           (4  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 1.0 uA */
+#  define ADI4_AUX_ISRC_TRIM_2p0U                           (8  << ADI4_AUX_ISRC_TRIM_SHIFT) /* 2.0 uA */
+#  define ADI4_AUX_ISRC_TRIM_4p5U                           (16 << ADI4_AUX_ISRC_TRIM_SHIFT) /* 4.5 uA */
+#  define ADI4_AUX_ISRC_TRIM_11p75U                         (32 << ADI4_AUX_ISRC_TRIM_SHIFT) /* 11.75 uA */
+
+/* TIVA_ADI4_AUX_COMP */
+
+#define ADI4_AUX_COMP_COMPA_EN                              (1 << 1)  /* Bit 1:  COMPA enable */
+#define ADI4_AUX_COMP_COMPB_EN                              (1 << 2)  /* Bit 2:  COMPB enable */
+
+#ifdef CONFIG_ARCH_CHIP_CC13XX_V2
+#  define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT           (3)       /* Bits 3-5 */
+#  define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK            (7 << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT)
+#    define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM(n)            ((uint32_t)(n) << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT)
+#endif
+
+#define ADI4_AUX_COMP_COMPA_REF_CURR_EN                     (1 << 6)  /* Bit 6:  Enables 2uA IPTAT current from ISRC to COMPA reference */
+#define ADI4_AUX_COMP_COMPA_REF_RES_EN                      (1 << 7)  /* Bit 7:  Enables 400kohm resistance from COMPA reference */
+
+/* TIVA_ADI4_AUX_MUX4 */
+
+#define ADI4_AUX_MUX4_COMPA_REF_SHIFT                       (0)       /* Bits 0-7 */
+#define ADI4_AUX_MUX4_COMPA_REF_MASK                        (0xff << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF(n)                        ((uint32_t)(n) << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_NC                        (0   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO26                   (1   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO25                   (2   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO24                   (4   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO23                   (8   << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO22                   (16  << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO21                   (32  << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO20                   (64  << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+#  define ADI4_AUX_MUX4_COMPA_REF_AUXIO19                   (128 << ADI4_AUX_MUX4_COMPA_REF_SHIFT)
+
+/* TIVA_ADI4_AUX_ADC0 */
+
+#define ADI4_AUX_ADC0_EN                                    (1 << 0)  /* Bit 0:  ADC Enable */
+#define ADI4_AUX_ADC0_RESET_N                               (1 << 1)  /* Bit 1:  Reset ADC digital subchip, active low */
+#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT                  (3)       /* Bits 3-6: Controls the sampling duration
+                                                                       * before conversion when the ADC is operated
+                                                                       * in synchronous mode (SMPL_MODE = 0) */
+#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_MASK                   (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT)
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP(n)                   ((uint32_t)(n) << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT)
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p7_US               (3  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16 clocks = 2.7us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_5p3_US               (4  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 32 clocks = 5.3us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_10p6_US              (5  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 64 clocks = 10.6us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_21p3_US              (6  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 128 clocks = 21.3us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_42p6_US              (7  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 256 clocks = 42.6us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_85p3_US              (8  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 512 clocks = 85.3us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_170_US               (9  << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 1024 clocks = 170us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_341_US               (10 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 2048 clocks = 341us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_682_US               (11 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 4096 clocks = 682us */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_1p37_MS              (12 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 8192 clocks = 1.37ms */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p73_MS              (13 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16384 clocks = 2.73ms */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_5p46_MS              (14 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 32768 clocks = 5.46ms */
+#  define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_10p9_MS              (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 65536 clocks = 10.9ms */
+#define ADI4_AUX_ADC0_SMPL_MODE                             (1 << 7)  /* Bit 7:  ADC Sampling mode */
+#  define ADI4_AUX_ADC0_SMPL_MODE_SYNCH                     (0)
+#  define ADI4_AUX_ADC0_SMPL_MODE_ASYNCH                    ADI4_AUX_ADC0_SMPL_MODE
+
+/* TIVA_ADI4_AUX_ADC1 */
+
+#define ADI4_AUX_ADC1_SCALE_DIS                             (1 << 0)  /* Bit 0 */
+
+/* TIVA_ADI4_AUX_ADCREF0 */
+
+#define ADI4_AUX_ADCREF0_EN                                 (1 << 0)  /* Bit 0:  ADC reference module enable */
+#define ADI4_AUX_ADCREF0_SRC                                (1 << 3)  /* Bit 3:  ADC reference source */
+#  define ADI4_AUX_ADCREF0_SRC_FIXED                        0
+#  define ADI4_AUX_ADCREF0_SRC_RELATIVE                     ADI4_AUX_ADCREF0_SRC
+#define ADI4_AUX_ADCREF0_EXT                                (1 << 4)  /* Bit 4 */
+#define ADI4_AUX_ADCREF0_IOMUX                              (1 << 5)  /* Bit 5 */
+#define ADI4_AUX_ADCREF0_REF_ON_IDLE                        (1 << 6)  /* Bit 6:  Enable ADCREF in IDLE state */
+
+
+/* TIVA_ADI4_AUX_ADCREF1 */
+
+#define ADI4_AUX_ADCREF1_VTRIM_SHIFT                        (0)       /* Bits 0-5: Trim output voltage of ADC fixed
+                                                                       * reference (64 steps, 2's complement) */
+#define ADI4_AUX_ADCREF1_VTRIM_MASK                         (0x3f << ADI4_AUX_ADCREF1_VTRIM_SHIFT)
+#  define ADI4_AUX_ADCREF1_VTRIM(n)                         ((uint32_t)(n) << ADI4_AUX_ADCREF1_VTRIM_SHIFT)
+#  define ADI4_AUX_ADCREF1_VTRIM_NOMINAL                    (0x00 << ADI4_AUX_ADCREF1_VTRIM_SHIFT) /* Nominal voltage 1.43V */
+#  define ADI4_AUX_ADCREF1_VTRIM_MAX                        (0x1f << ADI4_AUX_ADCREF1_VTRIM_SHIFT) /* Maximum voltage 1.6V */
+#  define ADI4_AUX_ADCREF1_VTRIM_MIN                        (0x20 << ADI4_AUX_ADCREF1_VTRIM_SHIFT) /* Minimum voltage 1.3V */
+
+/* TIVA_ADI4_AUX_LPMBIAS */
+
+#define ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT                (0)       /* Bits 0-5 */
+#define ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK                 (0x3f << ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT)
+#  define ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT(n)                 ((uint32_t)(n) << ADI4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI4_AUX_H */
diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h
index eae956ff982..5a823e6e870 100644
--- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h
+++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h
@@ -1,7 +1,7 @@
 /********************************************************************************************************************
  * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *
  * Technical content derives from a TI header file that has a compatible BSD license:
diff --git a/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h b/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h
index 5343a652ca6..a746c13116b 100644
--- a/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h
+++ b/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/tiva/hardware/tiva_adi2_refsys.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h b/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
index 10b50c5cb5b..fa562cb5362 100644
--- a/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
+++ b/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/arch/arm/src/tiva/hardware/tiva_adi4_aux.h b/arch/arm/src/tiva/hardware/tiva_adi4_aux.h
new file mode 100644
index 00000000000..1464108a478
--- /dev/null
+++ b/arch/arm/src/tiva/hardware/tiva_adi4_aux.h
@@ -0,0 +1,73 @@
+/************************************************************************************
+ * arch/arm/src/tiva/hardware/tiva_adi4_aux.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI4_AUX_H
+#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI4_AUX_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
+
+#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
+  /* These architectures do not support the ADI4 AUX block */
+#elif defined(CONFIG_ARCH_CHIP_CC13X0)
+#  include "hardware/cc13x0/cc13x0_adi4_aux.h"
+#elif defined(CONFIG_ARCH_CHIP_CC13X2)
+#  include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h"
+#else
+#  error "Unsupported Tiva/Stellaris/SimpleLink ADI4 AUX"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI4_AUX_H */