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Merged in masayuki2009/nuttx.nuttx/lc823450 (pull request #481)

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latest updates on lc823450

* arch/arm/src/lc823450: Conform to the NuttX coding style

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch/arm/src/lc823450: Merge the latest fix in lc823450_rtc.c

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch/arm/src/lc823450: Add ADC driver

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch/arm/src/lc823450: Add watchdog driver

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* configs/lc823450-xgevk: Enable ADC and watchdog driver

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Masayuki Ishikawa
2017-09-12 01:00:32 +00:00
committed by Gregory Nutt
parent acfa706df3
commit d95153706a
17 changed files with 1842 additions and 194 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/lc823450/lc823450_adc.c
+628
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File diff suppressed because it is too large Load Diff
arch/arm/src/lc823450/lc823450_adc.h
+122
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@@ -0,0 +1,122 @@
/****************************************************************************
* arch/arm/src/lc823450/chip/lc823450_adc.h
*
* Copyright (C) 2014-2017 Sony Corporation. All rights reserved.
* Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* Author: Nobutaka Toyoshima <Nobutaka.Toyoshima@jp.sony.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_LC823450_LC823450_ADC_H
#define __ARCH_ARM_SRC_LC823450_LC823450_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
/* Register Addresses *******************************************************/
#define ADC_REGBASE 0x40087000
#define rADC0DT (ADC_REGBASE + 0x00)
#define rADC1DT (ADC_REGBASE + 0x04)
#define rADC2DT (ADC_REGBASE + 0x08)
#define rADC3DT (ADC_REGBASE + 0x0C)
#define rADC4DT (ADC_REGBASE + 0x10)
#define rADC5DT (ADC_REGBASE + 0x14)
#define rADCCTL (ADC_REGBASE + 0x28)
#define rADCSTS (ADC_REGBASE + 0x2C)
#define rADCSMPL (ADC_REGBASE + 0x30)
#define rADCSTBY (ADC_REGBASE + 0x34)
/* Register Bitfield Definitions ********************************************/
/* ADC Control Register */
#define rADCCTL_fADCNTNU (1 << 9) /* Bit 9: ADC continuous conversion enable */
#define rADCCTL_fADACT (1 << 8) /* Bit 8: ADC activate enable */
#define rADCCTL_fADCHSCN (1 << 7) /* Bit 7: ADC channel scan enable */
#define rADCCTL_fADCNVCK_SHIFT (4)
#define rADCCTL_fADCNVCK_DIV2 (0 << rADCCTL_fADCNVCK_SHIFT)
#define rADCCTL_fADCNVCK_DIV4 (1 << rADCCTL_fADCNVCK_SHIFT)
#define rADCCTL_fADCNVCK_DIV8 (2 << rADCCTL_fADCNVCK_SHIFT)
#define rADCCTL_fADCNVCK_DIV16 (3 << rADCCTL_fADCNVCK_SHIFT)
#define rADCCTL_fADCNVCK_DIV32 (4 << rADCCTL_fADCNVCK_SHIFT)
#define rADCCTL_fADCNVCK_DIV64 (5 << rADCCTL_fADCNVCK_SHIFT)
#define rADCCTL_fADCHST_SHIFT (0)
/* ADC Status Register */
#define rADCSTS_fADCMPL (1 << 0) /* Bit 0: ADC Conversion Completion Flag */
/* ADC Standby Register */
#define rADCSTBY_STBY (1 << 0) /* Bit 0: Standby enable */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
FAR struct adc_dev_s *lc823450_adcinitialize(void);
#if defined(__cplusplus)
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LC823450_LC823450_ADC_H */
arch/arm/src/lc823450/lc823450_rtc.c
+41
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@@ -108,6 +108,21 @@
#define RTC_VDET_VDET 0x01 #define RTC_VDET_VDET 0x01
#define RTC_RTCINTCNT (RTC_REGBASE + 0x070) #define RTC_RTCINTCNT (RTC_REGBASE + 0x070)
#ifndef timespec_sub
#define timespec_sub(a, b, c) /* c = a - b */ \
do \
{\
(c)->tv_nsec = (a)->tv_nsec - (b)->tv_nsec; \
(c)->tv_sec = (a)->tv_sec - (b)->tv_sec; \
if ((c)->tv_nsec < 0) \
{\
(c)->tv_nsec += (1000 * 1000 * 1000); \
(c)->tv_sec--; \
}\
}\
while (0)
#endif /* timespec_sub */
/**************************************************************************** /****************************************************************************
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
@@ -148,6 +163,11 @@ static struct pm_callback_s pm_cb =
static int cboot = 1; static int cboot = 1;
#endif /* CONFIG_RTC_DIV */ #endif /* CONFIG_RTC_DIV */
#ifdef CONFIG_CLOCK_MONOTONIC
static struct timespec lastupdate_mono;
static struct timespec lastupdate_rtc;
#endif
/**************************************************************************** /****************************************************************************
* Public Data * Public Data
****************************************************************************/ ****************************************************************************/
@@ -542,6 +562,11 @@ int up_rtc_settime(FAR const struct timespec *ts)
up_rtc_set_default_datetime(tp); up_rtc_set_default_datetime(tp);
#endif /* CONFIG_RTC_SAVE_DEFAULT */ #endif /* CONFIG_RTC_SAVE_DEFAULT */
#ifdef CONFIG_CLOCK_MONOTONIC
clock_gettime(CLOCK_MONOTONIC, &lastupdate_mono);
lastupdate_rtc = *ts;
#endif
/* Start rtc update */ /* Start rtc update */
putreg8(0, RTC_RTCINT); putreg8(0, RTC_RTCINT);
@@ -649,6 +674,22 @@ int up_rtc_cancelalarm(void)
int up_rtc_getrawtime(FAR struct timespec *ts) int up_rtc_getrawtime(FAR struct timespec *ts)
{ {
struct tm tm; struct tm tm;
#ifdef CONFIG_CLOCK_MONOTONIC
struct timespec now, diff;
clock_gettime(CLOCK_MONOTONIC, &now);
timespec_sub(&now, &lastupdate_mono, &diff);
if (lastupdate_rtc.tv_sec != 0 && diff.tv_sec < 1)
{
/* Can not read RTC value until the end of first count (<1s) */
*ts = lastupdate_rtc;
return 0;
}
#endif
tm.tm_sec = getreg8(RTC_SEC); tm.tm_sec = getreg8(RTC_SEC);
tm.tm_min = getreg8(RTC_MIN); tm.tm_min = getreg8(RTC_MIN);
tm.tm_hour = getreg8(RTC_HOUR); tm.tm_hour = getreg8(RTC_HOUR);
arch/arm/src/lc823450/lc823450_sdc.c
+62 -58
View File
@@ -83,18 +83,18 @@ static sem_t _sdc_sem[2] =
SEM_INITIALIZER(1) SEM_INITIALIZER(1)
}; };
static SdDrCfg SdCh0; static struct SdDrCfg_s _sdch0;
static SdDrCfg SdCh1; static struct SdDrCfg_s _sdch1;
static SdDrCfg *cfg[2] = static struct SdDrCfg_s *_cfg[2] =
{ {
&SdCh0, &_sdch0,
&SdCh1 &_sdch1
}; };
static unsigned long work0[512/4]; static unsigned long _work0[512/4];
#ifdef CONFIG_LC823450_SDIF_SDC #ifdef CONFIG_LC823450_SDIF_SDC
static unsigned long work1[512/4]; static unsigned long _work1[512/4];
#endif #endif
#ifdef CONFIG_LC823450_SDC_CACHE #ifdef CONFIG_LC823450_SDC_CACHE
@@ -111,21 +111,22 @@ static uint32_t _sec_cache_add = 0xffffffff;
extern uint8_t cpu_ver; extern uint8_t cpu_ver;
extern SINT_T sddep0_hw_init(SdDrCfg *); extern SINT_T sddep0_hw_init(struct SdDrCfg_s *);
extern SINT_T sddep0_hw_exit(SdDrCfg *); extern SINT_T sddep0_hw_exit(struct SdDrCfg_s *);
extern SINT_T sddep1_hw_init(SdDrCfg *); extern SINT_T sddep1_hw_init(struct SdDrCfg_s *);
extern SINT_T sddep1_hw_exit(SdDrCfg *); extern SINT_T sddep1_hw_exit(struct SdDrCfg_s *);
extern SINT_T sddep_os_init(SdDrCfg *); extern SINT_T sddep_os_init(struct SdDrCfg_s *);
extern SINT_T sddep_os_exit(SdDrCfg *); extern SINT_T sddep_os_exit(struct SdDrCfg_s *);
extern void sddep_voltage_switch(SdDrCfg *cfg); extern void sddep_voltage_switch(struct SdDrCfg_s *cfg);
extern void sddep_set_clk(SdDrCfg *); extern void sddep_set_clk(struct SdDrCfg_s *);
extern SINT_T sddep_wait(UI_32, SdDrCfg *); extern SINT_T sddep_wait(UI_32, struct SdDrCfg_s *);
extern SINT_T sddep_wait_status(UI_32 req, UI_32 *status, SdDrCfg *cfg); extern SINT_T sddep_wait_status(UI_32 req, UI_32 *status,
struct SdDrCfg_s *cfg);
extern SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, extern SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type,
SdDrCfg *cfg); struct SdDrCfg_s *cfg);
extern SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type, extern SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type,
SdDrCfg *cfg); struct SdDrCfg_s *cfg);
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
@@ -156,12 +157,13 @@ static void _sdc_semgive(FAR sem_t *sem)
* Name: _lc823450_sdc_support_trim * Name: _lc823450_sdc_support_trim
****************************************************************************/ ****************************************************************************/
static int _lc823450_sdc_support_trim(SdDrCfg *cf) static int _lc823450_sdc_support_trim(struct SdDrCfg_s *cf)
{ {
/* NOTE: to avoid conflicts, SDDR_SUPPORT_TRIM() macro is not used here */ /* NOTE: to avoid conflicts, SDDR_SUPPORT_TRIM() macro is not used here */
int ret = ((SdDrRefMediaType(cf) == SDDR_MEDIA_TYPE_MMC) ? int ret = ((SdDrRefMediaType(cf) == SDDR_MEDIA_TYPE_MMC) ?
(((cf)->mEx.Mmc.mExtCsd_SEC_FEATURE_SUPPORT&(1UL << 4)) ? 1 : 0) : 0); (((cf)->ex.mmc.extcsd_sec_feature_support & (1UL << 4)) ?
1 : 0) : 0);
return ret; return ret;
} }
@@ -198,10 +200,12 @@ static void lc823450_sdc_access_led(uint32_t ch, unsigned long sector)
int lc823450_sdc_clearcardinfo(uint32_t ch) int lc823450_sdc_clearcardinfo(uint32_t ch)
{ {
int ret;
mcinfo("++++ start \n"); mcinfo("++++ start \n");
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
int ret = SdDrClearCardInfo(cfg[ch]); ret = SdDrClearCardInfo(_cfg[ch]);
#ifdef CONFIG_LC823450_SDC_CACHE #ifdef CONFIG_LC823450_SDC_CACHE
if (ch) if (ch)
@@ -228,39 +232,39 @@ int lc823450_sdc_initialize(uint32_t ch)
ASSERT(1 == cpu_ver); ASSERT(1 == cpu_ver);
SdDrCfg *psd = cfg[ch]; struct SdDrCfg_s *psd = _cfg[ch];
psd->mSysClk = lc823450_get_systemfreq(); psd->sysclk = lc823450_get_systemfreq();
psd->mDetectTime = DET_TIME; psd->detecttime = DET_TIME;
#ifdef CONFIG_LC823450_SDC_UHS1 #ifdef CONFIG_LC823450_SDC_UHS1
psd->mSetting = SDDR_SD_SWITCH_18V; psd->setting = SDDR_SD_SWITCH_18V;
#endif #endif
psd->mDepOsInit = sddep_os_init; psd->deposinit = sddep_os_init;
psd->mDepOsExit = sddep_os_exit; psd->deposexit = sddep_os_exit;
psd->mDepSetClk = sddep_set_clk; psd->depsetclk = sddep_set_clk;
psd->mDepWait = sddep_wait; psd->depwait = sddep_wait;
psd->mDepWaitStatus = sddep_wait_status; psd->depwaitstatus = sddep_wait_status;
psd->mDepReadData = sddep_read; psd->depreaddata = sddep_read;
psd->mDepWriteData = sddep_write; psd->depwritedata = sddep_write;
psd->mDepVoltageSwitch = sddep_voltage_switch; psd->depvoltageswitch = sddep_voltage_switch;
switch (ch) switch (ch)
{ {
case 0: case 0:
psd->mDepHwInit = sddep0_hw_init; psd->dephwinit = sddep0_hw_init;
psd->mDepHwExit = sddep0_hw_exit; psd->dephwexit = sddep0_hw_exit;
psd->mRegBase = SDIF0_BASE; psd->regbase = SDIF0_BASE;
psd->mWorkBuf = work0; psd->workbuf = _work0;
break; break;
#ifdef CONFIG_LC823450_SDIF_SDC #ifdef CONFIG_LC823450_SDIF_SDC
case 1: case 1:
psd->mDepHwInit = sddep1_hw_init; psd->dephwinit = sddep1_hw_init;
psd->mDepHwExit = sddep1_hw_exit; psd->dephwexit = sddep1_hw_exit;
psd->mRegBase = SDIF1_BASE; psd->regbase = SDIF1_BASE;
psd->mWorkBuf = work1; psd->workbuf = _work1;
break; break;
#endif #endif
@@ -270,7 +274,7 @@ int lc823450_sdc_initialize(uint32_t ch)
mcinfo("++++ start \n"); mcinfo("++++ start \n");
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrInitialize(cfg[ch]); ret = SdDrInitialize(_cfg[ch]);
_sdc_semgive(&_sdc_sem[ch]); _sdc_semgive(&_sdc_sem[ch]);
mcinfo("---- end ret=%d \n", ret); mcinfo("---- end ret=%d \n", ret);
@@ -287,7 +291,7 @@ int lc823450_sdc_finalize(uint32_t ch)
mcinfo("++++ start ch=%ld \n", ch); mcinfo("++++ start ch=%ld \n", ch);
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrFinalize(cfg[ch]); ret = SdDrFinalize(_cfg[ch]);
_sdc_semgive(&_sdc_sem[ch]); _sdc_semgive(&_sdc_sem[ch]);
mcinfo("---- end ret=%d \n", ret); mcinfo("---- end ret=%d \n", ret);
@@ -305,7 +309,7 @@ int lc823450_sdc_identifycard(uint32_t ch)
mcinfo("++++ start \n"); mcinfo("++++ start \n");
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrIdentifyCard(cfg[ch]); ret = SdDrIdentifyCard(_cfg[ch]);
#ifdef CONFIG_LC823450_SDC_CACHE #ifdef CONFIG_LC823450_SDC_CACHE
if (ch) if (ch)
@@ -324,13 +328,13 @@ int lc823450_sdc_identifycard(uint32_t ch)
* Name: lc823450_sdc_setclock * Name: lc823450_sdc_setclock
****************************************************************************/ ****************************************************************************/
int lc823450_sdc_setclock(uint32_t ch, uint32_t limitClk, uint32_t sysClk) int lc823450_sdc_setclock(uint32_t ch, uint32_t limitclk, uint32_t sysclk)
{ {
int ret; int ret;
mcinfo("++++ start ch=%ld limitClk=%ld sysClk=%ld\n", ch, limitClk, sysClk); mcinfo("++++ start ch=%ld limitClk=%ld sysClk=%ld\n", ch, limitClk, sysClk);
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrSetClock(limitClk, sysClk, cfg[ch]); ret = SdDrSetClock(limitclk, sysclk, _cfg[ch]);
_sdc_semgive(&_sdc_sem[ch]); _sdc_semgive(&_sdc_sem[ch]);
mcinfo("---- end ret=%d \n", ret); mcinfo("---- end ret=%d \n", ret);
@@ -349,7 +353,7 @@ int lc823450_sdc_refmediatype(uint32_t ch)
mcinfo("++++ start \n"); mcinfo("++++ start \n");
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrRefMediaType(cfg[ch]); ret = SdDrRefMediaType(_cfg[ch]);
_sdc_semgive(&_sdc_sem[ch]); _sdc_semgive(&_sdc_sem[ch]);
mcinfo("---- end ret=%d \n", ret); mcinfo("---- end ret=%d \n", ret);
@@ -361,14 +365,14 @@ int lc823450_sdc_refmediatype(uint32_t ch)
****************************************************************************/ ****************************************************************************/
int lc823450_sdc_getcardsize(uint32_t ch, int lc823450_sdc_getcardsize(uint32_t ch,
unsigned long *pSecNum, unsigned long *pSecSize) unsigned long *psecnum, unsigned long *psecsize)
{ {
int ret; int ret;
mcinfo("++++ start \n"); mcinfo("++++ start \n");
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrGetCardSize(pSecNum, pSecSize, cfg[ch]); ret = SdDrGetCardSize(psecnum, psecsize, _cfg[ch]);
_sdc_semgive(&_sdc_sem[ch]); _sdc_semgive(&_sdc_sem[ch]);
mcinfo("---- end ret=%d \n", ret); mcinfo("---- end ret=%d \n", ret);
@@ -409,9 +413,9 @@ int lc823450_sdc_readsector(uint32_t ch,
for (i = 0; i < 5; i++) for (i = 0; i < 5; i++)
{ {
#ifdef CONFIG_LC823450_SDIF_PATCH #ifdef CONFIG_LC823450_SDIF_PATCH
ret = fixedSdDrReadSector(addr, cnt, pbuf, type, cfg[ch]); ret = fixedSdDrReadSector(addr, cnt, pbuf, type, _cfg[ch]);
#else #else
ret = SdDrReadSector(addr, cnt, pbuf, type, cfg[ch]); ret = SdDrReadSector(addr, cnt, pbuf, type, _cfg[ch]);
#endif #endif
if (0 == ret) if (0 == ret)
{ {
@@ -486,7 +490,7 @@ int lc823450_sdc_writesector(uint32_t ch,
sched_add_bo((uint64_t)cnt); sched_add_bo((uint64_t)cnt);
#endif #endif
ret = SdDrWriteSector(addr, cnt, pbuf, type, cfg[ch]); ret = SdDrWriteSector(addr, cnt, pbuf, type, _cfg[ch]);
if (0 > ret) if (0 > ret)
{ {
@@ -505,7 +509,7 @@ int lc823450_sdc_writesector(uint32_t ch,
int lc823450_sdc_checktrim(uint32_t ch) int lc823450_sdc_checktrim(uint32_t ch)
{ {
return _lc823450_sdc_support_trim(cfg[ch]); return _lc823450_sdc_support_trim(_cfg[ch]);
} }
/**************************************************************************** /****************************************************************************
@@ -528,7 +532,7 @@ int lc823450_sdc_trimsector(uint32_t ch, unsigned long addr, unsigned short cnt)
sched_add_bt((uint64_t)cnt); sched_add_bt((uint64_t)cnt);
#endif #endif
ret = SdDrEraseSeq(0x00000001, addr, cnt, cfg[ch]); ret = SdDrEraseSeq(0x00000001, addr, cnt, _cfg[ch]);
if (0 > ret) if (0 > ret)
{ {
mcinfo("ret=%d ch=%d add=%ld cnt=%d \n", ret, ch, addr, cnt); mcinfo("ret=%d ch=%d add=%ld cnt=%d \n", ret, ch, addr, cnt);
@@ -551,7 +555,7 @@ int lc823450_sdc_cachectl(uint32_t ch, int ctrl)
mcinfo("++++ ch=%d, ctrl=%d \n", ch, ctrl); mcinfo("++++ ch=%d, ctrl=%d \n", ch, ctrl);
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrCacheCtrl(ctrl, cfg[ch]); ret = SdDrCacheCtrl(ctrl, _cfg[ch]);
_sdc_semgive(&_sdc_sem[ch]); _sdc_semgive(&_sdc_sem[ch]);
mcinfo("---- end ret=%d \n", ret); mcinfo("---- end ret=%d \n", ret);
@@ -569,7 +573,7 @@ int lc823450_sdc_changespeedmode(uint32_t ch, int mode)
mcinfo("++++ ch=%d, mode=%d \n", ch, mode); mcinfo("++++ ch=%d, mode=%d \n", ch, mode);
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrChangeSpeedMode(mode, cfg[ch]); ret = SdDrChangeSpeedMode(mode, _cfg[ch]);
if (0 == ret) if (0 == ret)
{ {
@@ -606,7 +610,7 @@ int lc823450_sdc_getcid(uint32_t ch, char *cidstr, int length)
mcinfo("++++ ch=%d \n", ch); mcinfo("++++ ch=%d \n", ch);
_sdc_semtake(&_sdc_sem[ch]); _sdc_semtake(&_sdc_sem[ch]);
ret = SdDrGetCid((UI_32 *)cid, cfg[ch]); ret = SdDrGetCid((UI_32 *)cid, _cfg[ch]);
if (0 == ret && length >= (2 * sizeof(cid) + 1)) if (0 == ret && length >= (2 * sizeof(cid) + 1))
{ {
arch/arm/src/lc823450/lc823450_sdc.h
+3 -3
View File
@@ -65,10 +65,10 @@ int lc823450_sdc_initialize(uint32_t ch);
int lc823450_sdc_finalize(uint32_t ch); int lc823450_sdc_finalize(uint32_t ch);
int lc823450_sdc_checkcarddetect(uint32_t ch); int lc823450_sdc_checkcarddetect(uint32_t ch);
int lc823450_sdc_identifycard(uint32_t ch); int lc823450_sdc_identifycard(uint32_t ch);
int lc823450_sdc_setclock(uint32_t ch, uint32_t limitClk, uint32_t sysClk); int lc823450_sdc_setclock(uint32_t ch, uint32_t limitclk, uint32_t sysclk);
int lc823450_sdc_refmediatype(uint32_t ch); int lc823450_sdc_refmediatype(uint32_t ch);
int lc823450_sdc_getcardsize(uint32_t ch, unsigned long *pSecNum, unsigned long *pSecSize); int lc823450_sdc_getcardsize(uint32_t ch, unsigned long *psecnum,
unsigned long *psecsize);
int lc823450_sdc_readsector(uint32_t ch, unsigned long addr, unsigned short cnt, int lc823450_sdc_readsector(uint32_t ch, unsigned long addr, unsigned short cnt,
void *pbuf, unsigned long type); void *pbuf, unsigned long type);
int lc823450_sdc_writesector(uint32_t ch, unsigned long addr, unsigned short cnt, int lc823450_sdc_writesector(uint32_t ch, unsigned long addr, unsigned short cnt,
arch/arm/src/lc823450/lc823450_sddrv_dep.c
+43 -38
View File
@@ -77,10 +77,10 @@
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_LC823450_SDC_DMA #ifdef CONFIG_LC823450_SDC_DMA
static DMA_HANDLE hrDma[2]; static DMA_HANDLE _hrdma[2];
static sem_t SemRWait[2]; static sem_t _sem_rwait[2];
static DMA_HANDLE hwDma[2]; static DMA_HANDLE _hwdma[2];
static sem_t SemWWait[2]; static sem_t _sem_wwait[2];
#endif /* CONFIG_LC823450_SDC_DMA */ #endif /* CONFIG_LC823450_SDC_DMA */
static uint64_t _sddep_timeout = (10 * 100); /* 10sec (in tick) */ static uint64_t _sddep_timeout = (10 * 100); /* 10sec (in tick) */
@@ -93,10 +93,10 @@ extern void sdif_powerctrl(bool);
* Name: _get_ch_from_cfg * Name: _get_ch_from_cfg
****************************************************************************/ ****************************************************************************/
static int _get_ch_from_cfg(SdDrCfg *cfg) static int _get_ch_from_cfg(struct SdDrCfg_s *cfg)
{ {
int ch = -1; int ch = -1;
switch (cfg->mRegBase) switch (cfg->regbase)
{ {
case SDIF0_BASE: case SDIF0_BASE:
ch = 0; ch = 0;
@@ -145,7 +145,7 @@ static void _sddep_semtake(FAR sem_t *sem)
* Name: sddep0_hw_init * Name: sddep0_hw_init
****************************************************************************/ ****************************************************************************/
SINT_T sddep0_hw_init(SdDrCfg *cfg) SINT_T sddep0_hw_init(struct SdDrCfg_s *cfg)
{ {
irqstate_t flags = enter_critical_section(); irqstate_t flags = enter_critical_section();
@@ -176,7 +176,7 @@ SINT_T sddep0_hw_init(SdDrCfg *cfg)
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_LC823450_SDIF_SDC #ifdef CONFIG_LC823450_SDIF_SDC
SINT_T sddep1_hw_init(SdDrCfg *cfg) SINT_T sddep1_hw_init(struct SdDrCfg_s *cfg)
{ {
int i; int i;
@@ -209,7 +209,7 @@ SINT_T sddep1_hw_init(SdDrCfg *cfg)
* Name: sddep0_hw_exit * Name: sddep0_hw_exit
****************************************************************************/ ****************************************************************************/
SINT_T sddep0_hw_exit(SdDrCfg *cfg) SINT_T sddep0_hw_exit(struct SdDrCfg_s *cfg)
{ {
irqstate_t flags = enter_critical_section(); irqstate_t flags = enter_critical_section();
@@ -226,7 +226,7 @@ SINT_T sddep0_hw_exit(SdDrCfg *cfg)
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_LC823450_SDIF_SDC #ifdef CONFIG_LC823450_SDIF_SDC
SINT_T sddep1_hw_exit(SdDrCfg *cfg) SINT_T sddep1_hw_exit(struct SdDrCfg_s *cfg)
{ {
irqstate_t flags = enter_critical_section(); irqstate_t flags = enter_critical_section();
@@ -268,7 +268,7 @@ SINT_T sddep1_hw_exit(SdDrCfg *cfg)
* Name: sddep_voltage_switch * Name: sddep_voltage_switch
****************************************************************************/ ****************************************************************************/
void sddep_voltage_switch(SdDrCfg *cfg) void sddep_voltage_switch(struct SdDrCfg_s *cfg)
{ {
#ifdef CONFIG_LC823450_SDC_UHS1 #ifdef CONFIG_LC823450_SDC_UHS1
/* GPIO06=H 1.8v */ /* GPIO06=H 1.8v */
@@ -283,15 +283,15 @@ void sddep_voltage_switch(SdDrCfg *cfg)
* Name: sddep_os_init * Name: sddep_os_init
****************************************************************************/ ****************************************************************************/
SINT_T sddep_os_init(SdDrCfg *cfg) SINT_T sddep_os_init(struct SdDrCfg_s *cfg)
{ {
int ch = _get_ch_from_cfg(cfg); int ch = _get_ch_from_cfg(cfg);
#ifdef CONFIG_LC823450_SDC_DMA #ifdef CONFIG_LC823450_SDC_DMA
hrDma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); _hrdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
sem_init(&SemRWait[ch], 0, 0); sem_init(&_sem_rwait[ch], 0, 0);
hwDma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); _hwdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
sem_init(&SemWWait[ch], 0, 0); sem_init(&_sem_wwait[ch], 0, 0);
#endif /* CONFIG_LC823450_SDC_DMA */ #endif /* CONFIG_LC823450_SDC_DMA */
return 0; return 0;
} }
@@ -300,7 +300,7 @@ SINT_T sddep_os_init(SdDrCfg *cfg)
* Name: sddep_os_exit * Name: sddep_os_exit
****************************************************************************/ ****************************************************************************/
SINT_T sddep_os_exit(SdDrCfg *cfg) SINT_T sddep_os_exit(struct SdDrCfg_s *cfg)
{ {
return 0; return 0;
} }
@@ -309,21 +309,21 @@ SINT_T sddep_os_exit(SdDrCfg *cfg)
* Name: sddep_set_clk * Name: sddep_set_clk
****************************************************************************/ ****************************************************************************/
void sddep_set_clk(SdDrCfg *cfg) void sddep_set_clk(struct SdDrCfg_s *cfg)
{ {
if (cfg->mClkDiv == 1) if (cfg->clkdiv == 1)
{ {
DEBUG_PRINT("clock div = 1\n"); DEBUG_PRINT("clock div = 1\n");
} }
DEBUG_PRINT("clock = %d Hz\n", cfg->mSysClk / cfg->mClkDiv); DEBUG_PRINT("clock = %d Hz\n", cfg->sysclk / cfg->clkdiv);
} }
/**************************************************************************** /****************************************************************************
* Name: sddep_wait * Name: sddep_wait
****************************************************************************/ ****************************************************************************/
SINT_T sddep_wait(UI_32 ms, SdDrCfg *cfg) SINT_T sddep_wait(UI_32 ms, struct SdDrCfg_s *cfg)
{ {
#ifdef CONFIG_HRT_TIMER #ifdef CONFIG_HRT_TIMER
up_hrttimer_usleep(ms * 1000); up_hrttimer_usleep(ms * 1000);
@@ -356,7 +356,8 @@ uint64_t sddep_set_timeout(uint64_t t)
* Name: sddep_wait_status * Name: sddep_wait_status
****************************************************************************/ ****************************************************************************/
SINT_T sddep_wait_status(UI_32 req_status, UI_32 *status, SdDrCfg *cfg) SINT_T sddep_wait_status(UI_32 req_status, UI_32 *status,
struct SdDrCfg_s *cfg)
{ {
systime_t tick0 = clock_systimer(); systime_t tick0 = clock_systimer();
int ret = 0; int ret = 0;
@@ -364,7 +365,7 @@ SINT_T sddep_wait_status(UI_32 req_status, UI_32 *status, SdDrCfg *cfg)
while (1) while (1)
{ {
systime_t tick1 = clock_systimer(); systime_t tick1 = clock_systimer();
*status = sdif_get_status(cfg->mRegBase); *status = sdif_get_status(cfg->regbase);
if (req_status & (*status)) if (req_status & (*status))
{ {
break; break;
@@ -385,7 +386,8 @@ SINT_T sddep_wait_status(UI_32 req_status, UI_32 *status, SdDrCfg *cfg)
* Name: sddep_read * Name: sddep_read
****************************************************************************/ ****************************************************************************/
SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg) SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type,
struct SdDrCfg_s *cfg)
{ {
#ifdef CONFIG_LC823450_SDC_DMA #ifdef CONFIG_LC823450_SDC_DMA
int ch = _get_ch_from_cfg(cfg); int ch = _get_ch_from_cfg(cfg);
@@ -393,7 +395,7 @@ SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
{ {
case SDDR_RW_INC_WORD: case SDDR_RW_INC_WORD:
case SDDR_RW_NOINC_WORD: case SDDR_RW_NOINC_WORD:
lc823450_dmasetup(hrDma[ch], lc823450_dmasetup(_hrdma[ch],
LC823450_DMA_SRCWIDTH_WORD | LC823450_DMA_SRCWIDTH_WORD |
LC823450_DMA_DSTWIDTH_WORD | LC823450_DMA_DSTWIDTH_WORD |
(type == SDDR_RW_INC_WORD ? LC823450_DMA_DSTINC : 0), (type == SDDR_RW_INC_WORD ? LC823450_DMA_DSTINC : 0),
@@ -402,7 +404,7 @@ SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
case SDDR_RW_INC_HWORD: case SDDR_RW_INC_HWORD:
case SDDR_RW_NOINC_HWORD: case SDDR_RW_NOINC_HWORD:
lc823450_dmasetup(hrDma[ch], lc823450_dmasetup(_hrdma[ch],
LC823450_DMA_SRCWIDTH_WORD | LC823450_DMA_SRCWIDTH_WORD |
LC823450_DMA_DSTWIDTH_HWORD | LC823450_DMA_DSTWIDTH_HWORD |
(type == SDDR_RW_INC_HWORD ? LC823450_DMA_DSTINC : 0), (type == SDDR_RW_INC_HWORD ? LC823450_DMA_DSTINC : 0),
@@ -411,7 +413,7 @@ SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
case SDDR_RW_INC_BYTE: case SDDR_RW_INC_BYTE:
case SDDR_RW_NOINC_BYTE: case SDDR_RW_NOINC_BYTE:
lc823450_dmasetup(hrDma[ch], lc823450_dmasetup(_hrdma[ch],
LC823450_DMA_SRCWIDTH_WORD | LC823450_DMA_SRCWIDTH_WORD |
LC823450_DMA_DSTWIDTH_BYTE | LC823450_DMA_DSTWIDTH_BYTE |
(type == SDDR_RW_INC_BYTE ? LC823450_DMA_DSTINC : 0), (type == SDDR_RW_INC_BYTE ? LC823450_DMA_DSTINC : 0),
@@ -419,13 +421,13 @@ SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
break; break;
} }
lc823450_dmastart(hrDma[ch], dma_callback, &SemRWait[ch]); lc823450_dmastart(_hrdma[ch], dma_callback, &_sem_rwait[ch]);
_sddep_semtake(&SemRWait[ch]); _sddep_semtake(&_sem_rwait[ch]);
return 0; return 0;
#else #else
SINT_T i; SINT_T i;
UI_32 *p = (UI_32 *)src; UI_32 *p = (UI_32 *)src;
UI_32 *buf = cfg->mWorkBuf; UI_32 *buf = cfg->workbuf;
for (i = 0; i < size/sizeof(UI_32); i++) for (i = 0; i < size/sizeof(UI_32); i++)
{ {
@@ -473,7 +475,8 @@ SINT_T sddep_read(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
* Name: sddep_write * Name: sddep_write
****************************************************************************/ ****************************************************************************/
SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg) SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type,
struct SdDrCfg_s *cfg)
{ {
#ifdef CONFIG_LC823450_SDC_DMA #ifdef CONFIG_LC823450_SDC_DMA
int ch = _get_ch_from_cfg(cfg); int ch = _get_ch_from_cfg(cfg);
@@ -481,7 +484,7 @@ SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
{ {
case SDDR_RW_INC_WORD: case SDDR_RW_INC_WORD:
case SDDR_RW_NOINC_WORD: case SDDR_RW_NOINC_WORD:
lc823450_dmasetup(hwDma[ch], lc823450_dmasetup(_hwdma[ch],
LC823450_DMA_SRCWIDTH_WORD | LC823450_DMA_SRCWIDTH_WORD |
LC823450_DMA_DSTWIDTH_WORD | LC823450_DMA_DSTWIDTH_WORD |
(type == SDDR_RW_INC_WORD ? LC823450_DMA_SRCINC : 0), (type == SDDR_RW_INC_WORD ? LC823450_DMA_SRCINC : 0),
@@ -490,7 +493,7 @@ SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
case SDDR_RW_INC_HWORD: case SDDR_RW_INC_HWORD:
case SDDR_RW_NOINC_HWORD: case SDDR_RW_NOINC_HWORD:
lc823450_dmasetup(hwDma[ch], lc823450_dmasetup(_hwdma[ch],
LC823450_DMA_SRCWIDTH_HWORD | LC823450_DMA_SRCWIDTH_HWORD |
LC823450_DMA_DSTWIDTH_WORD | LC823450_DMA_DSTWIDTH_WORD |
(type == SDDR_RW_INC_HWORD ? LC823450_DMA_SRCINC : 0), (type == SDDR_RW_INC_HWORD ? LC823450_DMA_SRCINC : 0),
@@ -499,20 +502,22 @@ SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type, SdDrCfg *cfg)
case SDDR_RW_INC_BYTE: case SDDR_RW_INC_BYTE:
case SDDR_RW_NOINC_BYTE: case SDDR_RW_NOINC_BYTE:
lc823450_dmasetup(hwDma[ch], lc823450_dmasetup(_hwdma[ch],
LC823450_DMA_SRCWIDTH_BYTE | LC823450_DMA_SRCWIDTH_BYTE |
LC823450_DMA_DSTWIDTH_WORD | LC823450_DMA_DSTWIDTH_WORD |
(type == SDDR_RW_INC_BYTE ? LC823450_DMA_SRCINC : 0), (type == SDDR_RW_INC_BYTE ? LC823450_DMA_SRCINC : 0),
(uint32_t)src, (uint32_t)dst, size); (uint32_t)src, (uint32_t)dst, size);
break; break;
} }
lc823450_dmastart(hwDma[ch], dma_callback, &SemWWait[ch]);
_sddep_semtake(&SemWWait[ch]); lc823450_dmastart(_hwdma[ch], dma_callback, &_sem_wwait[ch]);
return 0; _sddep_semtake(&_sem_wwait[ch]);
return 0;
#else #else
SINT_T i; SINT_T i;
UI_32 *p = (UI_32 *)dst; UI_32 *p = (UI_32 *)dst;
UI_32 *buf = cfg->mWorkBuf; UI_32 *buf = cfg->workbuf;
switch (type) switch (type)
{ {
arch/arm/src/lc823450/lc823450_sddrv_if.h
+96 -86
View File
@@ -101,66 +101,71 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* SD specific info */ /* SD specific info */
typedef struct t_SdInfo
struct SdInfo_s
{ {
UI_32 mScr[2]; UI_32 scr[2];
UI_32 mSdStatus[16]; UI_32 sdstatus[16];
} SdInfo; };
/* MMC specific info */ /* MMC specific info */
typedef struct t_MmcInfo
{
UI_32 mExtCsd_CACHE_SIZE; /* ExtCsd [252:249] */
UI_32 mExtCsd_SEC_COUNT; /* ExtCsd [215:212] */
UI_8 mExtCsd_SEC_FEATURE_SUPPORT; /* ExtCsd [231] */ struct MmcInfo_s
UI_8 mExtCsd_BOOT_SIZE_MULT; /* ExtCsd [226] */ {
UI_8 mExtCsd_DEVICE_TYPE; /* ExtCsd [196] */ UI_32 extcsd_cache_size; /* ExtCsd [252:249] */
UI_8 mExtCsd_HS_TIMING; /* ExtCsd [185] */ UI_32 extcsd_sec_count; /* ExtCsd [215:212] */
UI_8 mExtCsd_PARTITION_CONFIG; /* ExtCsd [179] */
UI_8 mExtCsd_BOOT_CONFIG_PROT; /* ExtCsd [178] */ UI_8 extcsd_sec_feature_support; /* ExtCsd [231] */
UI_8 mExtCsd_BOOT_BUS_WIDTH; /* ExtCsd [177] */ UI_8 extcsd_boot_size_mult; /* ExtCsd [226] */
UI_8 mExtCsd_CACHE_CTRL; /* ExtCsd [ 33] */ UI_8 extcsd_device_type; /* ExtCsd [196] */
} MmcInfo; UI_8 extcsd_hs_timing; /* ExtCsd [185] */
UI_8 extcsd_partition_config; /* ExtCsd [179] */
UI_8 extcsd_boot_config_prot; /* ExtCsd [178] */
UI_8 extcsd_boot_bus_width; /* ExtCsd [177] */
UI_8 extcsd_cache_ctrl; /* ExtCsd [ 33] */
};
/* SdDr configuration */ /* SdDr configuration */
typedef struct t_SdDrCfg
{
UI_32 mRegBase; /* SD Host I/F register base address */
UI_32 mSysClk; /* System Clock */
UI_32 mDetectTime; /* Card detection time */
UI_32 mSetting; /* WP CD settings */
void *mWorkBuf; /* Work buffer (512 byte) */
SINT_T (*mDepHwInit)(struct t_SdDrCfg *); struct SdDrCfg_s
SINT_T (*mDepHwExit)(struct t_SdDrCfg *); {
SINT_T (*mDepOsInit)(struct t_SdDrCfg *); UI_32 regbase; /* SD Host I/F register base address */
SINT_T (*mDepOsExit)(struct t_SdDrCfg *); UI_32 sysclk; /* System Clock */
void (*mDepSetClk)(struct t_SdDrCfg *); UI_32 detecttime; /* Card detection time */
SINT_T (*mDepWait)(UI_32, struct t_SdDrCfg *); UI_32 setting; /* WP CD settings */
SINT_T (*mDepWaitStatus)(UI_32 req, UI_32 *status, struct t_SdDrCfg *cfg); void *workbuf; /* Work buffer (512 byte) */
SINT_T (*mDepReadData)(void *src, void *dst, UI_32 size, SINT_T type, struct t_SdDrCfg *cfg);
SINT_T (*mDepWriteData)(void *src, void *dst, UI_32 size, SINT_T type, struct t_SdDrCfg *cfg); SINT_T (*dephwinit)(struct SdDrCfg_s *);
void (*mDepVoltageSwitch)(struct t_SdDrCfg *); SINT_T (*dephwexit)(struct SdDrCfg_s *);
SINT_T (*deposinit)(struct SdDrCfg_s *);
SINT_T (*deposexit)(struct SdDrCfg_s *);
void (*depsetclk)(struct SdDrCfg_s *);
SINT_T (*depwait)(UI_32, struct SdDrCfg_s *);
SINT_T (*depwaitstatus)(UI_32 req, UI_32 *status, struct SdDrCfg_s *cfg);
SINT_T (*depreaddata)(void *src, void *dst, UI_32 size, SINT_T type,
struct SdDrCfg_s *cfg);
SINT_T (*depwritedata)(void *src, void *dst, UI_32 size, SINT_T type,
struct SdDrCfg_s *cfg);
void (*depvoltageswitch)(struct SdDrCfg_s *);
/* To here, external members to be set */ /* To here, external members to be set */
/* From here, internal mermbers (no need to set) */ /* From here, internal mermbers (no need to set) */
UI_32 mInfo; /* Misc info (e.g. driver state) */ UI_32 info; /* Misc info (e.g. driver state) */
UI_32 mSecNum; /* The number of sectors */ UI_32 secnum; /* The number of sectors */
UI_32 mLimitSdClk; /* Max SD clock */ UI_32 limitsdclk; /* Max SD clock */
UI_32 mClkDiv; /* Clock divider */ UI_32 clkdiv; /* Clock divider */
UI_32 mEraseTmOut; /* Timeout for Erase/Trim */ UI_32 erasetmout; /* Timeout for Erase/Trim */
UI_32 mCid[4]; /* CID */ UI_32 cid[4]; /* CID */
UI_32 mCsd[4]; /* CSD */ UI_32 csd[4]; /* CSD */
union { union {
SdInfo Sd; /* SD specific info */ struct SdInfo_s sd; /* SD specific info */
MmcInfo Mmc; /* MMC specific info */ struct MmcInfo_s mmc; /* MMC specific info */
} mEx; } ex;
UI_32 mReserved; UI_32 reserved;
} SdDrCfg; };
/**************************************************************************** /****************************************************************************
@@ -181,63 +186,68 @@ extern "C"
****************************************************************************/ ****************************************************************************/
SINT_T SdDrRefVersion(void); SINT_T SdDrRefVersion(void);
SINT_T SdDrInitialize(SdDrCfg *cfg); SINT_T SdDrInitialize(struct SdDrCfg_s *cfg);
SINT_T SdDrFinalize(SdDrCfg *cfg); SINT_T SdDrFinalize(struct SdDrCfg_s *cfg);
SINT_T SdDrIdentifyCard(SdDrCfg *cfg); SINT_T SdDrIdentifyCard(struct SdDrCfg_s *cfg);
SINT_T SdDrCheckCardIdentify(SdDrCfg *cfg); SINT_T SdDrCheckCardIdentify(struct SdDrCfg_s *cfg);
SINT_T SdDrCheckWriteEnable(SdDrCfg *cfg); SINT_T SdDrCheckWriteEnable(struct SdDrCfg_s *cfg);
SINT_T SdDrCheckCardDetect(SdDrCfg *cfg); SINT_T SdDrCheckCardDetect(struct SdDrCfg_s *cfg);
SINT_T SdDrCheckCardRemoved(SdDrCfg *cfg); SINT_T SdDrCheckCardRemoved(struct SdDrCfg_s *cfg);
SINT_T SdDrGetCardSize(UI_32 *secNum, UI_32 *secSize, SdDrCfg *cfg); SINT_T SdDrGetCardSize(UI_32 *secnum, UI_32 *secsize, struct SdDrCfg_s *cfg);
SINT_T SdDrGetCid(UI_32 *cid, SdDrCfg *cfg); SINT_T SdDrGetCid(UI_32 *cid, struct SdDrCfg_s *cfg);
SINT_T SdDrGetCsd(UI_32 *csd, SdDrCfg *cfg); SINT_T SdDrGetCsd(UI_32 *csd, struct SdDrCfg_s *cfg);
SINT_T SdDrGetScr(UI_32 *scr, SdDrCfg *cfg); SINT_T SdDrGetScr(UI_32 *scr, struct SdDrCfg_s *cfg);
SINT_T SdDrGetExtCsd(UI_32 *extCsd, SdDrCfg *cfg); SINT_T SdDrGetExtCsd(UI_32 *extcsd, struct SdDrCfg_s *cfg);
SINT_T SdDrClearCardInfo(SdDrCfg *cfg); SINT_T SdDrClearCardInfo(struct SdDrCfg_s *cfg);
SINT_T SdDrReadSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type, SINT_T SdDrReadSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type,
SdDrCfg *cfg); struct SdDrCfg_s *cfg);
SINT_T SdDrWriteSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type, SINT_T SdDrWriteSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type,
SdDrCfg *cfg); struct SdDrCfg_s *cfg);
SINT_T SdDrEraseSector(UI_32 addr, UI_32 cnt, SdDrCfg *cfg); SINT_T SdDrEraseSector(UI_32 addr, UI_32 cnt, struct SdDrCfg_s *cfg);
SINT_T SdDrSetClock(UI_32 limitClk, UI_32 sysClk, SdDrCfg *cfg); SINT_T SdDrSetClock(UI_32 limitclk, UI_32 sysclk, struct SdDrCfg_s *cfg);
SINT_T SdDrChangeSpeedMode(SINT_T mode, SdDrCfg *cfg); SINT_T SdDrChangeSpeedMode(SINT_T mode, struct SdDrCfg_s *cfg);
SINT_T SdDrRefMediaType(SdDrCfg *cfg); SINT_T SdDrRefMediaType(struct SdDrCfg_s *cfg);
SINT_T SdDrSleep(SdDrCfg *cfg); SINT_T SdDrSleep(struct SdDrCfg_s *cfg);
SINT_T SdDrAwake(SdDrCfg *cfg); SINT_T SdDrAwake(struct SdDrCfg_s *cfg);
SINT_T SdDrSelectAccessPartition(UI_32 partNumber, SdDrCfg *cfg); SINT_T SdDrSelectAccessPartition(UI_32 partnumber, struct SdDrCfg_s *cfg);
SINT_T SdDrConfigBootMode(SINT_T enable, SINT_T ack, UI_32 bootPartNumber, SINT_T SdDrConfigBootMode(SINT_T enable, SINT_T ack, UI_32 bootpartnumber,
UI_32 bootBusWidth, SdDrCfg *cfg); UI_32 bootbuswidth, struct SdDrCfg_s *cfg);
SINT_T SdDrGetPartitionSize(UI_32 partNumber, UI_32 *secNum, SdDrCfg *cfg); SINT_T SdDrGetPartitionSize(UI_32 partnumber, UI_32 *secNum,
struct SdDrCfg_s *cfg);
SINT_T SdDrCheckSDXC(SdDrCfg *cfg); SINT_T SdDrCheckSDXC(struct SdDrCfg_s *cfg);
SINT_T SdDrEraseSeq(UI_32 type, UI_32 addr, UI_32 cnt, SdDrCfg *cfg); SINT_T SdDrEraseSeq(UI_32 type, UI_32 addr, UI_32 cnt, struct SdDrCfg_s *cfg);
#define SdDrTrimSector(addr,cnt,cfg) SdDrEraseSeq(0x00000001,addr,cnt,cfg) #define SdDrTrimSector(addr, cnt, cfg) \
#define SdDrSTrimSector1(addr,cnt,cfg) SdDrEraseSeq(0x80000001,addr,cnt,cfg) SdDrEraseSeq(0x00000001, addr, cnt, cfg)
#define SdDrSTrimSector2(cfg) SdDrEraseSeq(0x80008000, 0, 1,cfg) #define SdDrSTrimSector1(addr, cnt, cfg) \
SdDrEraseSeq(0x80000001, addr, cnt, cfg)
#define SdDrSTrimSector2(cfg) \
SdDrEraseSeq(0x80008000, 0, 1, cfg)
SINT_T SdDrGeneralCommand(SINT_T arg, UI_32 size, void *buf, SINT_T type, SINT_T SdDrGeneralCommand(SINT_T arg, UI_32 size, void *buf, SINT_T type,
SdDrCfg *cfg); struct SdDrCfg_s *cfg);
SINT_T SdDrCacheCtrl(SINT_T ctrl, SdDrCfg *cfg); SINT_T SdDrCacheCtrl(SINT_T ctrl, struct SdDrCfg_s *cfg);
#define SDDR_SUPPORT_TRIM(cfg) \ #define SDDR_SUPPORT_TRIM(cfg) \
((SdDrRefMediaType(cfg) == SDDR_MEDIA_TYPE_MMC) ? \ ((SdDrRefMediaType(cfg) == SDDR_MEDIA_TYPE_MMC) ? \
(((cfg)->mEx.Mmc.mExtCsd_SEC_FEATURE_SUPPORT&(1UL << 4)) ? 1 : 0) : 0) (((cfg)->ex.mmc.extcsd_sec_feature_support & (1UL << 4)) ? 1 : 0) : 0)
#define SDDR_SUPPORT_CACHE(cfg) \ #define SDDR_SUPPORT_CACHE(cfg) \
((SdDrRefMediaType(cfg) == SDDR_MEDIA_TYPE_MMC) ? \ ((SdDrRefMediaType(cfg) == SDDR_MEDIA_TYPE_MMC) ? \
((cfg)->mEx.Mmc.mExtCsd_CACHE_SIZE ? 1:0) : 0) ((cfg)->ex.mmc.extcsd_cache_size ? 1:0) : 0)
SINT_T SdDrBkopsGetStatus(SdDrCfg *cfg); SINT_T SdDrBkopsGetStatus(struct SdDrCfg_s *cfg);
SINT_T SdDrBkopsEnable(SINT_T ena, SdDrCfg *cfg); SINT_T SdDrBkopsEnable(SINT_T ena, struct SdDrCfg_s *cfg);
SINT_T SdDrBkopsStart(SdDrCfg *cfg); SINT_T SdDrBkopsStart(struct SdDrCfg_s *cfg);
SINT_T SdDrHpiEnable(SINT_T ena, SdDrCfg *cfg); SINT_T SdDrHpiEnable(SINT_T ena, struct SdDrCfg_s *cfg);
SINT_T SdDrHpiExec(SINT_T check, SdDrCfg *cfg); SINT_T SdDrHpiExec(SINT_T check, struct SdDrCfg_s *cfg);
SINT_T fixedSdDrReadSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type, SdDrCfg *cfg); SINT_T fixedSdDrReadSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type,
struct SdDrCfg_s *cfg);
UI_32 sdif_get_status(UI_32); UI_32 sdif_get_status(UI_32);
arch/arm/src/lc823450/lc823450_wdt.c
+604
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/lc823450/lc823450_wdt.h
+82
View File
@@ -0,0 +1,82 @@
/****************************************************************************
* arch/arm/src/lc823450/lc823450_wdt.h
*
* Copyright (C) 2014-2017 Sony Corporation. All rights reserved.
* Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* Author: Nobutaka Toyoshima <Nobutaka.Toyoshima@jp.sony.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_LC823450_LC823450_WDT_H
#define __ARCH_ARM_SRC_LC823450_LC823450_WDT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
int lc823450_wdt_initialize(void);
#ifdef CONFIG_WATCHDOG_WORK
void lc823450_wdg_work_enable(int en);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
#endif /* __ARCH_ARM_SRC_LC823450_LC823450_WDT_H */
configs/lc823450-xgevk/README.txt
+35 -3
View File
@@ -12,7 +12,8 @@ LC823450 related documents are available at
http://www.onsemi.com/PowerSolutions/supportDoc.do?type=AppNotes&rpn=LC823450 http://www.onsemi.com/PowerSolutions/supportDoc.do?type=AppNotes&rpn=LC823450
This port is intended to test LC823450 features including SMP. This port is intended to test LC823450 features including SMP.
Supported peripherals are UART, TIMER, RTC, GPIO, DMA, I2C, SPI, LCD, eMMC, and USB device. Supported peripherals:
UART, TIMER, RTC, GPIO, DMA, I2C, SPI, LCD, eMMC, USB, WDT, ADC.
Settings Settings
^^^^^^^^ ^^^^^^^^
@@ -97,8 +98,39 @@ Please note that card hotplugging is not supported.
nsh> msconn nsh> msconn
nsh> msdis nsh> msdis
7. ADC
nsh> adc
adc_main: g_adcstate.count: 1
adc_main: Hardware initialized. Opening the ADC device: /dev/adc0
Sample:
1: channel: 0 value: 366
2: channel: 1 value: 691
3: channel: 2 value: 752
4: channel: 3 value: 963
5: channel: 4 value: 6
6: channel: 5 value: 0
8. WDT
nsh> wdog
ping elapsed=0
ping elapsed=500
ping elapsed=1000
ping elapsed=1500
ping elapsed=2000
ping elapsed=2500
ping elapsed=3000
ping elapsed=3500
ping elapsed=4000
ping elapsed=4500
NO ping elapsed=5000
NO ping elapsed=5500
NO ping elapsed=6000
TODO TODO
^^^^ ^^^^
The following peripherals will be supported. The following features will be supported.
ADC, Audio, etc. IPL2 (eMMC boot), Audio, etc.
configs/lc823450-xgevk/nsh/defconfig
+8 -1
View File
@@ -1,3 +1,5 @@
CONFIG_ADC=y
CONFIG_ANALOG=y
CONFIG_AQM_1248A=y CONFIG_AQM_1248A=y
CONFIG_ARCH="arm" CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="lc823450-xgevk" CONFIG_ARCH_BOARD="lc823450-xgevk"
@@ -6,6 +8,7 @@ CONFIG_ARCH_CHIP_LC823450=y
CONFIG_ARCH_FLOAT_H=y CONFIG_ARCH_FLOAT_H=y
CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STDARG_H=y CONFIG_ARCH_STDARG_H=y
CONFIG_BOARDCTL_RESET=y
CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_BOARD_LOOPSPERMSEC=12061
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_C99_BOOL8=y CONFIG_C99_BOOL8=y
@@ -19,6 +22,9 @@ CONFIG_DEBUG_WARN=y
CONFIG_DEV_ZERO=y CONFIG_DEV_ZERO=y
CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_MQUEUE=y
CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_EXAMPLES_ADC_GROUPSIZE=6
CONFIG_EXAMPLES_ADC_SWTRIG=y
CONFIG_EXAMPLES_ADC=y
CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLO=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NXHELLO_BPP=1 CONFIG_EXAMPLES_NXHELLO_BPP=1
@@ -26,6 +32,7 @@ CONFIG_EXAMPLES_NXHELLO=y
CONFIG_EXAMPLES_OSTEST=y CONFIG_EXAMPLES_OSTEST=y
CONFIG_EXAMPLES_PIPE=y CONFIG_EXAMPLES_PIPE=y
CONFIG_EXAMPLES_SMP=y CONFIG_EXAMPLES_SMP=y
CONFIG_EXAMPLES_WATCHDOG=y
CONFIG_EXPERIMENTAL=y CONFIG_EXPERIMENTAL=y
CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS=y
CONFIG_FS_WRITABLE=y CONFIG_FS_WRITABLE=y
@@ -38,6 +45,7 @@ CONFIG_LC823450_I2C1=y
# CONFIG_LC823450_SDIF is not set # CONFIG_LC823450_SDIF is not set
CONFIG_LC823450_SPI_DMA=y CONFIG_LC823450_SPI_DMA=y
CONFIG_LC823450_UART0=y CONFIG_LC823450_UART0=y
CONFIG_LC823450_WDT=y
CONFIG_LCD_ST7565=y CONFIG_LCD_ST7565=y
CONFIG_LCD=y CONFIG_LCD=y
CONFIG_LIB_KBDCODEC=y CONFIG_LIB_KBDCODEC=y
@@ -55,7 +63,6 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_BASENAME=y CONFIG_NSH_DISABLE_BASENAME=y
CONFIG_NSH_DISABLE_CP=y CONFIG_NSH_DISABLE_CP=y
CONFIG_NSH_DISABLE_DD=y CONFIG_NSH_DISABLE_DD=y
CONFIG_NSH_DISABLE_DELROUTE=y
CONFIG_NSH_DISABLE_DIRNAME=y CONFIG_NSH_DISABLE_DIRNAME=y
CONFIG_NSH_DISABLE_EXEC=y CONFIG_NSH_DISABLE_EXEC=y
CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_GET=y
configs/lc823450-xgevk/src/Makefile
+4
View File
@@ -48,6 +48,10 @@ ifeq ($(CONFIG_LC823450_SDIF),y)
CSRCS += lc823450_sdif.c CSRCS += lc823450_sdif.c
endif endif
ifeq ($(CONFIG_ADC),y)
CSRCS += lc823450_adc.c
endif
ifeq ($(CONFIG_USBMSC),y) ifeq ($(CONFIG_USBMSC),y)
CSRCS += lc823450_usbmsc.c CSRCS += lc823450_usbmsc.c
endif endif
configs/lc823450-xgevk/src/lc823450-xgevk.h
+14 -2
View File
@@ -62,6 +62,18 @@
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Name: lc823450_adc_setup
*
* Description:
* Initialize ADC and register the ADC driver.
*
****************************************************************************/
#ifdef CONFIG_ADC
int lc823450_adc_setup(void);
#endif
/**************************************************************************** /****************************************************************************
* Name: lc823450_bringup * Name: lc823450_bringup
* *
@@ -74,9 +86,9 @@
int lc823450_bringup(void); int lc823450_bringup(void);
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: lc823450_bma250initialize * Name: lc823450_bma250initialize
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_BMA250 #ifdef CONFIG_BMA250
int lc823450_bma250initialize(FAR const char *devpath); int lc823450_bma250initialize(FAR const char *devpath);
configs/lc823450-xgevk/src/lc823450_adc.c
+77
View File
@@ -0,0 +1,77 @@
/****************************************************************************
* configs/lc823450-xgevk/src/lc823450_adc.c
*
* Copyright (C) 2017 Sony Corporation. All rights reserved.
* Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/board.h>
#include <nuttx/analog/adc.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "lc823450-xgevk.h"
#include "lc823450_adc.h"
/************************************************************************************
* Name: lc823450_adc_setup
*
* Description:
* Initialize ADC and register the ADC driver.
*
************************************************************************************/
int lc823450_adc_setup(void)
{
struct adc_dev_s *adc;
/* Call lc823450_adcinitialize() to get an instance of the ADC interface */
adc = lc823450_adcinitialize();
if (adc == NULL)
{
aerr("ERROR: Failed to get ADC interface\n");
return -ENODEV;
}
return OK;
}
configs/lc823450-xgevk/src/lc823450_appinit.c
+11 -1
View File
@@ -143,6 +143,16 @@ static void lc823450_i2ctool(void)
int board_app_initialize(uintptr_t arg) int board_app_initialize(uintptr_t arg)
{ {
int ret;
#ifdef CONFIG_ADC
ret = lc823450_adc_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: lc82450_adc_setup failed: %d\n", ret);
}
#endif
/* Register I2C drivers on behalf of the I2C tool */ /* Register I2C drivers on behalf of the I2C tool */
lc823450_i2ctool(); lc823450_i2ctool();
@@ -150,7 +160,7 @@ int board_app_initialize(uintptr_t arg)
#ifdef CONFIG_LC823450_MTD #ifdef CONFIG_LC823450_MTD
/* Initialize eMMC */ /* Initialize eMMC */
int ret = lc823450_mtd_initialize(CONFIG_MTD_DEVNO_EMMC); ret = lc823450_mtd_initialize(CONFIG_MTD_DEVNO_EMMC);
if (ret != OK) if (ret != OK)
{ {
syslog(LOG_ERR, "Failed to initialize eMMC: ret=%d\n", ret); syslog(LOG_ERR, "Failed to initialize eMMC: ret=%d\n", ret);
configs/lc823450-xgevk/src/lc823450_bringup.c
+4
View File
@@ -63,6 +63,10 @@ int lc823450_bringup(void)
{ {
int ret; int ret;
#ifdef CONFIG_WATCHDOG
lc823450_wdt_initialize();
#endif
#ifdef CONFIG_FS_PROCFS #ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */ /* Mount the procfs file system */
configs/lc823450-xgevk/usb/defconfig
+8 -2
View File
@@ -1,3 +1,5 @@
CONFIG_ADC=y
CONFIG_ANALOG=y
CONFIG_AQM_1248A=y CONFIG_AQM_1248A=y
CONFIG_ARCH="arm" CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="lc823450-xgevk" CONFIG_ARCH_BOARD="lc823450-xgevk"
@@ -6,6 +8,7 @@ CONFIG_ARCH_CHIP_LC823450=y
CONFIG_ARCH_FLOAT_H=y CONFIG_ARCH_FLOAT_H=y
CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STDARG_H=y CONFIG_ARCH_STDARG_H=y
CONFIG_BOARDCTL_RESET=y
CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_BOARD_LOOPSPERMSEC=12061
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_C99_BOOL8=y CONFIG_C99_BOOL8=y
@@ -21,6 +24,9 @@ CONFIG_DISABLE_MQUEUE=y
CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_ELF_BUFFERSIZE=512 CONFIG_ELF_BUFFERSIZE=512
CONFIG_ELF=y CONFIG_ELF=y
CONFIG_EXAMPLES_ADC_GROUPSIZE=6
CONFIG_EXAMPLES_ADC_SWTRIG=y
CONFIG_EXAMPLES_ADC=y
CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLO=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NXHELLO_BPP=1 CONFIG_EXAMPLES_NXHELLO_BPP=1
@@ -28,6 +34,7 @@ CONFIG_EXAMPLES_NXHELLO=y
CONFIG_EXAMPLES_OSTEST=y CONFIG_EXAMPLES_OSTEST=y
CONFIG_EXAMPLES_PIPE=y CONFIG_EXAMPLES_PIPE=y
CONFIG_EXAMPLES_SMP=y CONFIG_EXAMPLES_SMP=y
CONFIG_EXAMPLES_WATCHDOG=y
CONFIG_EXPERIMENTAL=y CONFIG_EXPERIMENTAL=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
@@ -45,6 +52,7 @@ CONFIG_LC823450_SDIF_SDC=y
CONFIG_LC823450_SPI_DMA=y CONFIG_LC823450_SPI_DMA=y
CONFIG_LC823450_UART0=y CONFIG_LC823450_UART0=y
CONFIG_LC823450_UART1=y CONFIG_LC823450_UART1=y
CONFIG_LC823450_WDT=y
CONFIG_LCD_ST7565=y CONFIG_LCD_ST7565=y
CONFIG_LCD=y CONFIG_LCD=y
CONFIG_LIB_KBDCODEC=y CONFIG_LIB_KBDCODEC=y
@@ -52,7 +60,6 @@ CONFIG_LIBM=y
CONFIG_MAX_TASKS=64 CONFIG_MAX_TASKS=64
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MEMSET_OPTSPEED=y CONFIG_MEMSET_OPTSPEED=y
CONFIG_MTD_MMCL=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_NAME_MAX=765 CONFIG_NAME_MAX=765
CONFIG_NETUTILS_CODECS=y CONFIG_NETUTILS_CODECS=y
@@ -62,7 +69,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_ARGCAT is not set
CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_CMDOPT_DD_STATS=y CONFIG_NSH_CMDOPT_DD_STATS=y
CONFIG_NSH_DISABLE_DELROUTE=y
CONFIG_NSH_DISABLE_EXEC=y CONFIG_NSH_DISABLE_EXEC=y
CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_GET=y
CONFIG_NSH_DISABLE_HEXDUMP=y CONFIG_NSH_DISABLE_HEXDUMP=y