diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index df137147922..01194134c2b 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -240,6 +240,7 @@ config ARCH_CHIP_SAM3A config ARCH_CHIP_SAM4CM bool default n + select ARCH_HAVE_MULTICPU select ARCH_HAVE_TICKLESS config ARCH_CHIP_SAM4L diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index dab10fb45e1..9b4e75079ad 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -50,13 +50,17 @@ CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S CMN_ASRCS += up_testset.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c -CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c +CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c +ifneq ($(CONFIG_SMP),y) +CMN_CSRCS += up_idle.c +endif + # Configuration-dependent common files ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) @@ -198,14 +202,22 @@ endif ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y) ifeq ($(CONFIG_SAM34_TC),y) CHIP_CSRCS += sam4cm_tc.c + ifeq ($(CONFIG_SAM34_ONESHOT),y) CHIP_CSRCS += sam4cm_oneshot.c sam4cm_oneshot_lowerhalf.c -endif +endif # CONFIG_SAM34_ONESHOT + ifeq ($(CONFIG_SAM34_FREERUN),y) CHIP_CSRCS += sam4cm_freerun.c -endif +endif # CONFIG_SAM34_FREERUN + ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += sam4cm_tickless.c -endif -endif -endif +endif # CONFIG_SCHED_TICKLESS +endif # CONFIG_SAM34_TC + +ifeq ($(CONFIG_SMP),y) +CHIP_CSRCS += sam4cm_cpuindex.c sam4cm_cpuidlestack.c +CHIP_CSRCS += sam4cm_cpupause.c sam4cm_cpustart.c sam4cm_idle.c +endif # CONFIG_SMP +endif # CONFIG_ARCH_CHIP_SAM4CM diff --git a/arch/arm/src/sam34/chip/sam4cm_memorymap.h b/arch/arm/src/sam34/chip/sam4cm_memorymap.h index c0b2de041b8..d719e268c01 100644 --- a/arch/arm/src/sam34/chip/sam4cm_memorymap.h +++ b/arch/arm/src/sam34/chip/sam4cm_memorymap.h @@ -65,6 +65,7 @@ /* Internal SRAM memory region */ #define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */ +#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */ #define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ /* 0x24000000-0x3fffffff: Undefined */ /* Peripherals address region */ diff --git a/arch/arm/src/sam34/chip/sam_pmc.h b/arch/arm/src/sam34/chip/sam_pmc.h index 6514d1f42e4..d7a75f6b038 100644 --- a/arch/arm/src/sam34/chip/sam_pmc.h +++ b/arch/arm/src/sam34/chip/sam_pmc.h @@ -402,10 +402,10 @@ # define PMC_MCKR_CPCSS_SHIFT (16) # define PMC_MCKR_CPCSS_MASK (0x7 << PMC_MCKR_CPCSS_SHIFT) # define PMC_MCKR_CPCSS_SLOW (0 << PMC_MCKR_CPCSS_SHIFT) /* Slow Clock */ -# define PMC_MCKR_CCPSS_MAIN (1 << PMC_MCKR_CPCSS_SHIFT) /* Main Clock */ -# define PMC_MCKR_CCPSS_PLLA (2 << PMC_MCKR_CPCSS_SHIFT) /* PLLA Clock */ -# define PMC_MCKR_CCPSS_PLLB (3 << PMC_MCKR_CPCSS_SHIFT) /* PLLB Clock */ -# define PMC_MCKR_CCPSS_MCK (4 << PMC_MCKR_CPCSS_SHIFT) /* Master Clock */ +# define PMC_MCKR_CPCSS_MAIN (1 << PMC_MCKR_CPCSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CPCSS_PLLA (2 << PMC_MCKR_CPCSS_SHIFT) /* PLLA Clock */ +# define PMC_MCKR_CPCSS_PLLB (3 << PMC_MCKR_CPCSS_SHIFT) /* PLLB Clock */ +# define PMC_MCKR_CPCSS_MCK (4 << PMC_MCKR_CPCSS_SHIFT) /* Master Clock */ # define PMC_MCKR_CPPRES_SHIFT (20) # define PMC_MCKR_CPPRES_MASK (0xF << PMC_MCKR_CPPRES_SHIFT) # define PMC_MCKR_CPPRES(D) (((D) - 1) << PMC_MCKR_CPPRES_SHIFT) @@ -547,13 +547,14 @@ /* Peripheral Clock Status Register 1 */ #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ - defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) + defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) || \ + defined(CONFIG_ARCH_CHIP_SAM4CM) # define PMC_PIDH(n) (1 << ((n) - 32)) # define PMC_PID32 (1 << 0) /* Bit 0: PID32 */ # define PMC_PID33 (1 << 1) /* Bit 1: PID33 */ # define PMC_PID34 (1 << 2) /* Bit 2: PID34 */ # if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ - defined(CONFIG_ARCH_CHIP_SAM4E) + defined(CONFIG_ARCH_CHIP_SAM4E) || defined(CONFIG_ARCH_CHIP_SAM4CM) # define PMC_PID35 (1 << 3) /* Bit 3: PID35 */ # define PMC_PID36 (1 << 4) /* Bit 4: PID36 */ # define PMC_PID37 (1 << 5) /* Bit 5: PID37 */ diff --git a/arch/arm/src/sam34/sam4cm_cpuidlestack.c b/arch/arm/src/sam34/sam4cm_cpuidlestack.c new file mode 100644 index 00000000000..411ebfaad77 --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpuidlestack.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpuidlestack.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + asm("WFI"); + +#endif +} + +/**************************************************************************** + * Name: up_cpu_idlestack + * + * Description: + * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and + * setup up stack-related information in the IDLE task's TCB. This + * function is always called before up_cpu_start(). This function is + * only called for the CPU's initial IDLE task; up_create_task is used for + * all normal tasks, pthreads, and kernel threads for all CPUs. + * + * The initial IDLE task is a special case because the CPUs can be started + * in different wans in different environments: + * + * 1. The CPU may already have been started and waiting in a low power + * state for up_cpu_start(). In this case, the IDLE thread's stack + * has already been allocated and is already in use. Here + * up_cpu_idlestack() only has to provide information about the + * already allocated stack. + * + * 2. The CPU may be disabled but started when up_cpu_start() is called. + * In this case, a new stack will need to be created for the IDLE + * thread and this function is then equivalent to: + * + * return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - cpu: CPU index that indicates which CPU the IDLE task is + * being created for. + * - tcb: The TCB of new CPU IDLE task + * - stack_size: The requested stack size for the IDLE task. At least + * this much must be allocated. This should be + * CONFIG_SMP_STACK_SIZE. + * + ****************************************************************************/ + +int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) +{ +#if CONFIG_SMP_NCPUS > 1 + (void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); +#endif + return OK; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/sam34/sam4cm_cpuindex.c b/arch/arm/src/sam34/sam4cm_cpuindex.c new file mode 100644 index 00000000000..867d36e5c1b --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpuindex.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpuindex.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "mpu.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +int up_cpu_index(void) +{ + /* MPU is not supported on CM4P1 */ + + return (getreg32(MPU_TYPE) == 0) ? 1 : 0; +} + +#endif /* CONFIG_SMP */ + + diff --git a/arch/arm/src/sam34/sam4cm_cpupause.c b/arch/arm/src/sam34/sam4cm_cpupause.c new file mode 100644 index 00000000000..9b9d126f252 --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpupause.c @@ -0,0 +1,328 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpupause.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" +#include "chip/sam4cm_ipc.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if 0 +# define DPRINTF(fmt, args...) _err(fmt, ##args) +#else +# define DPRINTF(fmt, args...) do {} while (0) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* These spinlocks are used in the SMP configuration in order to implement + * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m]. + * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and + * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second + * blocks CPUm in the interrupt handler. + * + * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler + * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m] + * so that it will be ready for the next pause operation. + */ + +static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_pausereq + * + * Description: + * Return true if a pause request is pending for this CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = a pause request is pending. + * false = no pasue request is pending. + * + ****************************************************************************/ + +bool up_cpu_pausereq(int cpu) +{ + return spin_islocked(&g_cpu_paused[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ + FAR struct tcb_s *tcb = this_task(); + + /* Update scheduler parameters */ + + sched_suspend_scheduler(tcb); + + /* Save the current context at CURRENT_REGS into the TCB at the head + * of the assigned task list for this CPU. + */ + + up_savestate(tcb->xcp.regs); + + /* Wait for the spinlock to be released */ + + spin_unlock(&g_cpu_paused[cpu]); + spin_lock(&g_cpu_wait[cpu]); + + /* Restore the exception context of the tcb at the (new) head of the + * assigned task list. + */ + + tcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(tcb); + + /* Then switch contexts. Any necessary address environment changes + * will be made when the interrupt returns. + */ + + up_restorestate(tcb->xcp.regs); + spin_unlock(&g_cpu_wait[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: arm_pause_handler + * + * Description: + * Inter-CPU interrupt handler + * + * Input Parameters: + * Standard interrupt handler inputs + * + * Returned Value: + * Should always return OK + * + ****************************************************************************/ + +int arm_pause_handler(int irq, void *c) +{ + int cpu = up_cpu_index(); + + /* Clear : Pause IRQ */ + /* IPC Interrupt Clear Command Register (write-only) */ + + if (1 == cpu) + { + DPRINTF("CPU0 -> CPU1\n"); + putreg32(0x1, SAM_IPC1_ICCR); + } + else + { + DPRINTF("CPU1 -> CPU0\n"); + putreg32(0x1, SAM_IPC0_ICCR); + } + + /* Check for false alarms. Such false could occur as a consequence of + * some deadlock breaking logic that might have already serviced the SG2 + * interrupt by calling up_cpu_paused. + */ + + if (spin_islocked(&g_cpu_paused[cpu])) + { + return up_cpu_paused(cpu); + } + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_pause + * + * Description: + * Save the state of the current task at the head of the + * g_assignedtasks[cpu] task list and then pause task execution on the + * CPU. + * + * This function is called by the OS when the logic executing on one CPU + * needs to modify the state of the g_assignedtasks[cpu] list for another + * CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be stopped/ + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_pause(int cpu) +{ + DPRINTF("cpu=%d\n",cpu); + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 + * handler from returning until up_cpu_resume() is called; g_cpu_paused + * is a handshake that will prefent this function from returning until + * the CPU is actually paused. + */ + + spin_lock(&g_cpu_wait[cpu]); + spin_lock(&g_cpu_paused[cpu]); + + DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) && + spin_islocked(&g_cpu_paused[cpu])); + + /* Execute Pause IRQ to CPU(cpu) */ + /* Set IPC Interrupt (IRQ0) (write-only) */ + + if (cpu == 1) + { + putreg32(0x1, SAM_IPC1_ISCR); + } + else + { + putreg32(0x1, SAM_IPC0_ISCR); + } + + /* Wait for the other CPU to unlock g_cpu_paused meaning that + * it is fully paused and ready for up_cpu_resume(); + */ + + spin_lock(&g_cpu_paused[cpu]); + + spin_unlock(&g_cpu_paused[cpu]); + + /* On successful return g_cpu_wait will be locked, the other CPU will be + * spinninf on g_cpu_wait and will not continue until g_cpu_resume() is + * called. g_cpu_paused will be unlocked in any case. + */ + + return 0; +} + +/**************************************************************************** + * Name: up_cpu_resume + * + * Description: + * Restart the cpu after it was paused via up_cpu_pause(), restoring the + * state of the task at the head of the g_assignedtasks[cpu] list, and + * resume normal tasking. + * + * This function is called after up_cpu_pause in order resume operation of + * the CPU after modifying its g_assignedtasks[cpu] list. + * + * Input Parameters: + * cpu - The index of the CPU being re-started. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_resume(int cpu) +{ + DPRINTF("cpu=%d\n",cpu); + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Release the spinlock. Releasing the spinlock will cause the SGI2 + * handler on 'cpu' to continue and return from interrupt to the newly + * established thread. + */ + + DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) && + !spin_islocked(&g_cpu_paused[cpu])); + + spin_unlock(&g_cpu_wait[cpu]); + + return 0; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c new file mode 100644 index 00000000000..44c8d9508c9 --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpustart.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "sched/sched.h" +#include "init/init.h" +#include "up_internal.h" +#include "chip/sam_pmc.h" +#include "chip/sam_rstc.h" +#include "chip/sam4cm_ipc.h" +#include "sam4cm_periphclks.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if 0 +# define DPRINTF(fmt, args...) _err(fmt, ##args) +#else +# define DPRINTF(fmt, args...) do {} while (0) +#endif + +#define CPU1_VECTOR_RESETV (SAM_INTSRAM1_BASE) +#define CPU1_VECTOR_ISTACK (SAM_INTSRAM1_BASE + 4) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile static spinlock_t g_cpu1_boot; +extern int arm_pause_handler(int irq, void *c); + +/**************************************************************************** + * Name: cpu1_boot + * + * Description: + * This is the boot vector for CM4P1 + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void cpu1_boot(void) +{ + int cpu; + + /* Disable CMCC1 */ + + putreg32(0, 0x48018008); + while ((getreg32(0x4801800c) & 0x01) != 0); + + cpu = up_cpu_index(); + DPRINTF("cpu = %d\n", cpu); + + if (cpu == 1) + { + /* Use CPU0 vectors */ + + putreg32((uint32_t)&_stext, NVIC_VECTAB); + sam_ipc1_enableclk(); + + /* Clear : write-only */ + + putreg32(0x1, SAM_IPC1_ICCR); + + /* Enable : write-only */ + + putreg32(0x1, SAM_IPC1_IECR); + irq_attach(SAM_IRQ_IPC1, arm_pause_handler); + up_enable_irq(SAM_IRQ_IPC1); + } + + spin_unlock(&g_cpu1_boot); + + /* Then transfer control to the IDLE task */ + + (void)os_idle_task(0, NULL); +} + +/**************************************************************************** + * Name: up_cpu_start + * + * Description: + * In an SMP configution, only one CPU is initially active (CPU 0). System + * initialization occurs on that single thread. At the completion of the + * initialization of the OS, just before beginning normal multitasking, + * the additional CPUs would be started by calling this function. + * + * Each CPU is provided the entry point to is IDLE task when started. A + * TCB for each CPU's IDLE task has been initialized and placed in the + * CPU's g_assignedtasks[cpu] list. Not stack has been alloced or + * initialized. + * + * The OS initialization logic calls this function repeatedly until each + * CPU has been started, 1 through (CONFIG_SMP_NCPUS-1). + * + * Input Parameters: + * cpu - The index of the CPU being started. This will be a numeric + * value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU + * 0 is already active) + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_start(int cpu) +{ + struct tcb_s *tcb = current_task(cpu); + + DPRINTF("cpu=%d\n",cpu); + + if (cpu != 1) + return -1; + + /* Reset coprocessor */ + + putreg32(0x5a000000, SAM_RSTC_CPMR); + + /* Enable Coprocessor Bus Master Clock (write-only) */ + + putreg32(PMC_CPKEY | PMC_CPBMCK, SAM_PMC_SCER); + + /* Enable Coprocessor Clock (write-only) */ + + putreg32(PMC_CPKEY | PMC_CPCK, SAM_PMC_SCER); + + /* Set Coprocessor Clock Prescalar */ + + modifyreg32(SAM_PMC_MCKR, PMC_MCKR_CPPRES_MASK, 0); + + /* Set Coprocessor Clock Source */ + + modifyreg32(SAM_PMC_MCKR, PMC_MCKR_CPCSS_MASK, PMC_MCKR_CPCSS_PLLB); + + /* Unreset coprocessor pheripheral */ + + putreg32(0x5a000010, SAM_RSTC_CPMR); + + /* Enable clock for SRAM1 where CPU1 starts (write-only) */ + + putreg32(PMC_PID42, SAM_PMC_PCER1); + + /* Clear SRAM1 */ + + memset((void *)SAM_INTSRAM1_BASE, 0, 16 * 1024); + + /* Copy initial vectors for CPU1 */ + + putreg32((uint32_t)tcb->adj_stack_ptr, CPU1_VECTOR_RESETV); + putreg32((uint32_t)cpu1_boot, CPU1_VECTOR_ISTACK); + + spin_lock(&g_cpu1_boot); + + /* Unreset coprocessor */ + + putreg32(0x5a000011, SAM_RSTC_CPMR); + + /* IRQ setup CPU1->CPU0 */ + + sam_ipc0_enableclk(); + putreg32(0x1, SAM_IPC0_ICCR); /* clear : write-only */ + putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */ + irq_attach(SAM_IRQ_IPC0, arm_pause_handler); + up_enable_irq(SAM_IRQ_IPC0); + + spin_lock(&g_cpu1_boot); + + /* CPU1 boot done */ + + spin_unlock(&g_cpu1_boot); + + return 0; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/sam34/sam4cm_idle.c b/arch/arm/src/sam34/sam4cm_idle.c new file mode 100644 index 00000000000..9c3810136cf --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_idle.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_idle.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + asm("WFI"); + +#endif +} diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 68f17774347..0b3286d0cac 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -84,7 +84,11 @@ * CURRENT_REGS for portability. */ +#ifdef CONFIG_SMP +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +#else volatile uint32_t *g_current_regs[1]; +#endif /* This is the address of the exception vector table (determined by the * linker script). diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c index abae1da7615..71537f1c38b 100644 --- a/arch/arm/src/sam34/sam_start.c +++ b/arch/arm/src/sam34/sam_start.c @@ -241,6 +241,13 @@ void __start(void) const uint32_t *src; uint32_t *dest; +#ifdef CONFIG_SMP + /* Disable CMCC0 */ + + putreg32(0, 0x4007c008); + while ((getreg32(0x4007c00c) & 0x01) != 0); +#endif + #ifdef CONFIG_ARMV7M_STACKCHECK /* Set the stack limit before we attempt to call any functions */