diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index dd2cabc1950..5dd4809caf1 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -43,6 +43,8 @@ config STM32L4_STM32L4X3 select STM32L4_HAVE_USART1 select STM32L4_HAVE_USART2 select STM32L4_HAVE_USART3 + select STM32L4_HAVE_LPTIM1 + select STM32L4_HAVE_LPTIM2 select STM32L4_HAVE_SAI1 select STM32L4_HAVE_SAI2 @@ -54,6 +56,8 @@ config STM32L4_STM32L4X6 select STM32L4_HAVE_USART3 select STM32L4_HAVE_UART4 select STM32L4_HAVE_UART5 + select STM32L4_HAVE_LPTIM1 + select STM32L4_HAVE_LPTIM2 select STM32L4_HAVE_SAI1 select STM32L4_HAVE_SAI2 @@ -130,6 +134,14 @@ config STM32L4_HAVE_LTDC bool default n +config STM32L4_HAVE_LPTIM1 + bool + default n + +config STM32L4_HAVE_LPTIM2 + bool + default n + config STM32L4_HAVE_SAI1 bool default n @@ -174,8 +186,8 @@ config STM32L4_USART default n config STM32L4_LPTIM - bool - default n + bool + default n # These are the peripheral selections proper @@ -446,8 +458,8 @@ config STM32L4_TIM7 default n config STM32L4_LCD - bool "LCD" - default n + bool "LCD" + default n config STM32L4_SPI2 bool "SPI2" @@ -533,13 +545,14 @@ config STM32L4_DAC2 select STM32L4_DAC config STM32L4_OPAMP - bool "OPAMP" - default n + bool "OPAMP" + default n config STM32L4_LPTIM1 bool "LPTIM1" default n - select STM32L4_LPTIM + select STM32L4_LPTIM + depends on STM32L4_HAVE_LPTIM1 config STM32L4_LPUART1 bool "LPUART1" @@ -548,13 +561,14 @@ config STM32L4_LPUART1 select ARCH_HAVE_LPUART1 config STM32L4_SWPMI - bool "SWPMI" - default n + bool "SWPMI" + default n config STM32L4_LPTIM2 bool "LPTIM2" default n - select STM32L4_LPTIM + select STM32L4_LPTIM + depends on STM32L4_HAVE_LPTIM2 comment "APB2 Peripherals" @@ -614,8 +628,8 @@ config STM32L4_SAI2 default n config STM32L4_DFSDM - bool "DFSDM" - default n + bool "DFSDM" + default n comment "Other Peripherals" diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 7d5ecb8bacc..436a750af3d 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -195,6 +195,10 @@ ifeq ($(CONFIG_STM32L4_SAI),y) CHIP_CSRCS += stm32l4_sai.c endif +ifeq ($(CONFIG_STM32L4_LPTIM),y) +CHIP_CSRCS += stm32l4_lptim.c +endif + ifeq ($(CONFIG_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif diff --git a/arch/arm/src/stm32l4/chip/stm32l4_lptim.h b/arch/arm/src/stm32l4/chip/stm32l4_lptim.h new file mode 100644 index 00000000000..1822effec45 --- /dev/null +++ b/arch/arm/src/stm32l4/chip/stm32l4_lptim.h @@ -0,0 +1,117 @@ +/**************************************************************************************************** + * arch/arm/src/stm32l4/stm32l4_lptim.h + * + * Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. + * Copyright (C) 2009, 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ +#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ +#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ +#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */ +#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ +#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ +#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ + +/* Register Addresses *******************************************************************************/ + +/* Low-Power Timers - LPTIM1 and LPTIM2 */ + +#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET) +#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET) +#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET) +#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET) +#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET) +#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET) +#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET) +#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET) + +#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET) +#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET) +#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET) +#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET) +#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET) +#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET) +#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET) +#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +#define LPTIM_CFGR_CKSEL (1 << 0) /* Bit 0: Clock selector */ +#define LPTIM_CFGR_CKPOL_SHIFT (1) /* Bits 2-1: Clock Polarity */ +#define LPTIM_CFGR_CKPOL_MASK (3 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKFLT_SHIFT (3) /* Bits 4-3: Digital filter for external clock */ +#define LPTIM_CFGR_CKFLTN_MASK (3 << LPTIM_CFGR_CKFLT_SHIFT) + /* Bit 5: reserved */ +#define LPTIM_CFGR_TRGFLT_SHIFT (6) /* Bits 7-6: Digital filter for trigger */ +#define LPTIM_CFGR_TRGFLT_MASK (3 << LPTIM_CFGR_TRGFLT_SHIFT) + /* Bit 8: reserved */ +#define LPTIM_CFGR_PRESC_SHIFT (9) /* Bits 11-9: clock pre-scaler */ +#define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT) +# define LPTIM_CFGR_PRESCd1 (0 << LPTIM_CFGR_PRESC_SHIFT) /* 000: divide by 1 */ +# define LPTIM_CFGR_PRESCd2 (1 << LPTIM_CFGR_PRESC_SHIFT) /* 001: divide by 2 */ +# define LPTIM_CFGR_PRESCd4 (2 << LPTIM_CFGR_PRESC_SHIFT) /* 010: divide by 4 */ +# define LPTIM_CFGR_PRESCd8 (3 << LPTIM_CFGR_PRESC_SHIFT) /* 011: divide by 8 */ +# define LPTIM_CFGR_PRESCd16 (4 << LPTIM_CFGR_PRESC_SHIFT) /* 100: divide by 16 */ +# define LPTIM_CFGR_PRESCd32 (5 << LPTIM_CFGR_PRESC_SHIFT) /* 101: divide by 32 */ +# define LPTIM_CFGR_PRESCd64 (6 << LPTIM_CFGR_PRESC_SHIFT) /* 110: divide by 64 */ +# define LPTIM_CFGR_PRESCd128 (7 << LPTIM_CFGR_PRESC_SHIFT) /* 111: divide by 128 */ + /* Bit 12: reserved */ +#define LPTIM_CFGR_TRIGSEL_SHIFT (13) /* Bits 15-13: Trigger selector */ +#define LPTIM_CFGR_TRIGSEL_MASK (7 << LPTIM_CFGR_TRIGSEL_SHIFT) + /* Bit 16: reserved */ +#define LPTIM_CFGR_TRIGEN_SHIFT (17) /* Bits 18-17: Trigger enable and polarity */ +#define LPTIM_CFGR_TRIGEN_MASK (3 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TIMOUT (1 << 19) /* Bit 19: Timeout enable */ +#define LPTIM_CFGR_WAVE (1 << 20) /* Bit 20: Waveform shape */ +#define LPTIM_CFGR_WAVPOL (1 << 21) /* Bit 21: Waveform polarity */ +#define LPTIM_CFGR_PRELOAD (1 << 22) /* Bit 22: Update mode enable */ +#define LPTIM_CFGR_COUNTMODE (1 << 23) /* Bit 23: Count mode enable */ +#define LPTIM_CFGR_ENC (1 << 24) /* Bit 24: Encoder mode enable (LPTIM1 only) */ + +#define LPTIM_CR_ENABLE (1 << 0) /* Bit 0: Enable */ +#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Single Mode */ +#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Continuous Mode */ + +#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h b/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h index 906e53dccb5..0b2b537f1e4 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H +#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H /************************************************************************************ * Included Files @@ -49,5 +49,5 @@ # error "Unsupported STM32 L4 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_rng.h b/arch/arm/src/stm32l4/chip/stm32l4_rng.h index 434b77c1c26..7812110b620 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_rng.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_rng.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H -#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H +#ifndef __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H +#define __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H /************************************************************************************ * Included Files @@ -74,4 +74,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H */ +#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_sai.h b/arch/arm/src/stm32l4/chip/stm32l4_sai.h index a7ab977a0fc..f411fb72baf 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_sai.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H -#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H +#ifndef __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H +#define __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H /************************************************************************************ * Included Files @@ -256,4 +256,4 @@ /* SAI Data Register (32-bit data) */ -#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H */ +#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c new file mode 100644 index 00000000000..4833472120c --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -0,0 +1,548 @@ +/************************************************************************************ + * arm/arm/src/stm3l42/stm32l4_lptim.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With modifications and updates by: + * + * Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ +/************************************************************************************ + * Copyright (c) 2015 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "stm32l4.h" +#include "stm32l4_gpio.h" +#include "stm32l4_lptim.h" + +#if defined(CONFIG_STM32L4_LPTIM1) || defined(CONFIG_STM32L4_LPTIM2) + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* TIM Device Structure */ + +struct stm32l4_lptim_priv_s +{ + const struct stm32l4_lptim_ops_s *ops; + stm32l4_lptim_mode_t mode; + uint32_t base; /* LPTIMn base address */ + uint32_t freq; /* Clocking for the LPTIM module */ +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer); +static inline void stm32l4_modifyreg32(FAR struct stm32l4_lptim_dev_s *dev, + uint8_t offset, uint32_t clearbits, + uint32_t setbits); +static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev); +static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev); +static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev); +static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, + uint32_t *cfg); +static int stm32l4_lptim_setmode(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_mode_t mode); +static int stm32l4_lptim_setclock(FAR struct stm32l4_lptim_dev_s *dev, + uint32_t freq); +static int stm32l4_lptim_setchannel(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, int enable); + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = +{ + .setmode = &stm32l4_lptim_setmode, + .setclock = &stm32l4_lptim_setclock, + .setchannel = &stm32l4_lptim_setchannel, +}; + +#if CONFIG_STM32L4_LPTIM1 +static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = +{ + .ops = &stm32l4_lptim_ops, + .mode = STM32L4_LPTIM_MODE_UNUSED, + .base = STM32L4_LPTIM1_BASE, + .freq = STM32L4_LPTIM1_FREQUENCY, /* Must be efined in board.h */ +}; +#endif + +#if CONFIG_STM32L4_LPTIM2 +static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = +{ + .ops = &stm32l4_lptim_ops, + .mode = STM32L4_LPTIM_MODE_UNUSED, + .base = STM32L4_LPTIM2_BASE, + .freq = STM32L4_LPTIM2_FREQUENCY, /* Must be efined in board.h */ +}; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_lptim_getstruct + ************************************************************************************/ + +static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) +{ + switch (timer) + { +#if CONFIG_STM32L4_LPTIM1 + case 1: + return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv; +#endif +#if CONFIG_STM32L4_LPTIM2 + case 2: + return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv; +#endif + default: + return NULL; + } +} + +/************************************************************************************ + * Name: stm32l4_modifyreg32 + ************************************************************************************/ + +static inline void stm32l4_modifyreg32(FAR struct stm32l4_lptim_dev_s *dev, + uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(((struct stm32l4_lptim_priv_s *)dev)->base + offset, clearbits, setbits); +} + +/************************************************************************************ + * Name: stm32l4_lptim_enable + ************************************************************************************/ + +static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); + break; +#endif +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); + break; +#endif + + default: + return ERROR; + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_disable + ************************************************************************************/ + +static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); + break; +#endif +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); + break; +#endif + + default: + return ERROR; + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_reset + ************************************************************************************/ + +static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); + modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); + break; +#endif +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); + modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); + break; +#endif + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_get_gpioconfig + ************************************************************************************/ + +static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, + uint32_t *cfg) +{ + DEBUGASSERT(dev != NULL && cfg != NULL); + + channel &= STM32L4_LPTIM_CH_MASK; + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + switch (channel) + { +# if defined(GPIO_LPTIM1_OUT_1) + case 1: + *cfg = GPIO_LPTIM1_OUT_1; + break; +# endif +# if defined(GPIO_LPTIM1_OUT_2) + case 2: + *cfg = GPIO_LPTIM1_OUT_2; + break; +# endif +# if defined(GPIO_LPTIM1_OUT_3) + case 3: + *cfg = GPIO_LPTIM1_OUT_3; + break; +# endif + default: + return ERROR; + } + break; +#endif /* CONFIG_STM32L4_LPTIM1 */ + +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + switch (channel) + { +# if defined(GPIO_LPTIM2_OUT_1) + case 1: + *cfg = GPIO_LPTIM2_OUT_1; + break; +# endif +# if defined(GPIO_LPTIM2_OUT_2) + case 2: + *cfg = GPIO_LPTIM2_OUT_2; + break; +# endif +# if defined(GPIO_LPTIM2_OUT_3) + case 3: + *cfg = GPIO_LPTIM2_OUT_3; + break; +# endif + default: + return ERROR; + } + break; +#endif /* CONFIG_STM32L4_LPTIM2 */ + + default: + return ERROR; + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_setmode + ************************************************************************************/ + +static int stm32l4_lptim_setmode(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_mode_t mode) +{ + const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + + STM32L4_LPTIM_CR_OFFSET; + + DEBUGASSERT(dev != NULL); + + /* Mode */ + + switch (mode & STM32L4_LPTIM_MODE_MASK) + { + case STM32L4_LPTIM_MODE_DISABLED: + modifyreg32(addr, LPTIM_CR_ENABLE, 0); + break; + + case STM32L4_LPTIM_MODE_SINGLE: + modifyreg32(addr, 0, LPTIM_CR_ENABLE); + modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); + break; + + case STM32L4_LPTIM_MODE_CONTINUOUS: + modifyreg32(addr, 0, LPTIM_CR_ENABLE); + modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); + break; + + default: + return ERROR; + } + + /* Save mode */ + + ((struct stm32l4_lptim_priv_s *)dev)->mode = mode; + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_setclock + ************************************************************************************/ + +static int stm32l4_lptim_setclock(FAR struct stm32l4_lptim_dev_s *dev, + uint32_t freq) +{ + FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev; + uint32_t setbits; + uint32_t actual; + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + stm32l4_lptim_disable(dev); + return 0; + } + + if (freq >= priv->freq >> 0) + { + /* More than clock source. This is as fast as we can go */ + + setbits = LPTIM_CFGR_PRESCd1; + actual = priv->freq >> 0; + } + else if (freq >= priv->freq >> 1) + { + setbits = LPTIM_CFGR_PRESCd2; + actual = priv->freq >> 1; + } + else if (freq >= priv->freq >> 2) + { + setbits = LPTIM_CFGR_PRESCd4; + actual = priv->freq >> 2; + } + else if (freq >= priv->freq >> 3) + { + setbits = LPTIM_CFGR_PRESCd8; + actual = priv->freq >> 3; + } + else if (freq >= priv->freq >> 4) + { + setbits = LPTIM_CFGR_PRESCd16; + actual = priv->freq >> 4; + } + else if (freq >= priv->freq >> 5) + { + setbits = LPTIM_CFGR_PRESCd32; + actual = priv->freq >> 5; + } + else if (freq >= priv->freq >> 6) + { + setbits = LPTIM_CFGR_PRESCd64; + actual = priv->freq >> 6; + } + else + { + /* This is as slow as we can go */ + + setbits = LPTIM_CFGR_PRESCd128; + actual = priv->freq >> 7; + } + + stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + setbits); + stm32l4_lptim_enable(dev); + + return actual; +} + +/************************************************************************************ + * Name: stm32l4_lptim_setchannel + ************************************************************************************/ + +static int stm32l4_lptim_setchannel(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, int enable) +{ + int ret = OK; + uint32_t cfg = 0; + + ASSERT(dev); + + /* Configure GPIOs */ + + ret = stm32l4_lptim_get_gpioconfig(dev, channel, &cfg); + if (!ret) + { + if (enable) + { + stm32l4_configgpio(cfg); + } + else + { + stm32l4_unconfiggpio(cfg); + } + } + + return ret; +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_lptim_init + ************************************************************************************/ + +FAR struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) +{ + struct stm32l4_lptim_dev_s *dev = NULL; + + /* Get structure and enable power */ + + dev = stm32l4_lptim_getstruct(timer); + if (!dev) + { + return NULL; + } + + /* Is device already allocated */ + + if (((struct stm32l4_lptim_priv_s *)dev)->mode != STM32L4_LPTIM_MODE_UNUSED) + { + return NULL; + } + + /* Enable power */ + + stm32l4_lptim_enable(dev); + + /* Reset timer */ + + stm32l4_lptim_reset(dev); + + /* Mark it as used */ + + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED; + + return dev; +} + +/************************************************************************************ + * Name: stm32l4_lptim_deinit + ************************************************************************************/ + +int stm32l4_lptim_deinit(FAR struct stm32l4_lptim_dev_s * dev) +{ + ASSERT(dev); + + /* Disable power */ + + stm32l4_lptim_disable(dev); + + /* Mark it as free */ + + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED; + + return OK; +} + +#endif /* CONFIG_STM32L4_LPTIM1 || CONFIG_STM32L4_LPTIM2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h new file mode 100644 index 00000000000..bd7f7eb7851 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -0,0 +1,171 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_lptim.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With modifications and updates by: + * + * Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ +/************************************************************************************ + * Copyright (c) 2015 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/stm32l4_lptim.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helpers **************************************************************************/ + +#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* LPTIM Device Structure */ + +struct stm32l4_lptim_dev_s +{ + struct stm32l4_lptim_ops_s *ops; +}; + +/* LPTIM Modes of Operation */ + +typedef enum +{ + STM32L4_LPTIM_MODE_UNUSED = -1, + + /* MODES */ + + STM32L4_LPTIM_MODE_DISABLED = 0x0000, + STM32L4_LPTIM_MODE_SINGLE = 0x0001, + STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002, + STM32L4_LPTIM_MODE_MASK = 0x003f, +} stm32l4_lptim_mode_t; + +/* LPTIM Channel Modes */ + +typedef enum +{ + STM32L4_LPTIM_CH_DISABLED = 0x0000, + + /* CHANNELS */ + + STM32L4_LPTIM_CH_CHINVALID = 0x0000, + STM32L4_LPTIM_CH_CH1 = 0x0001, + STM32L4_LPTIM_CH_CH2 = 0x0002, + STM32L4_LPTIM_CH_CH3 = 0x0003, + STM32L4_LPTIM_CH_MASK = 0x000f, +} stm32l4_lptim_channel_t; + +/* LPTIM Operations */ + +struct stm32l4_lptim_ops_s +{ + int (*setmode)(FAR struct stm32l4_lptim_dev_s *dev, stm32l4_lptim_mode_t mode); + int (*setclock)(FAR struct stm32l4_lptim_dev_s *dev, uint32_t freq); + int (*setchannel)(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, int enable); +}; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/* Get timer structure, power-up, reset, and mark it as used */ + +FAR struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer); + +/* Power-down timer, mark it as unused */ + +int stm32l4_lptim_deinit(FAR struct stm32l4_lptim_dev_s * dev); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index cdeb0ee590e..0d64e0a72ca 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -124,6 +124,5 @@ void stm32l4_usbsuspend(FAR struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */ - +#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 599ed7c4cc8..73abae16c5b 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -105,7 +105,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_PWR) && defined(CONFIG_RTC) +#if defined(CONFIG_STM32L4_PWR) && defined(CONFIG_RTC) static inline void rcc_resetbkp(void) { bool init_stat; diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 222f5bc7c0c..404f8325ad5 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -54,8 +54,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ /**************************************************************************** * Public Types @@ -146,7 +146,7 @@ bool rtc_is_inits(void); * ****************************************************************************/ -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS int stm32l4_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index dfef76a9b10..e8c05428ee4 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -1750,8 +1750,8 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); + cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } break; @@ -1762,8 +1762,8 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); + cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } break;