mirror of
https://github.com/apache/nuttx.git
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Added STM32FF76xxx and STM32FF7xx families
This commit is contained in:
David Sidrane
committed by
Gregory Nutt
Gregory Nutt
parent
86b29dc64c
commit
d8ea955d69
+235
-62
@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/include/stm32f7/chip.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -45,99 +45,272 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
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/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
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* STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
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*
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* ----------- ---------------- ----- -------- ------------ --------
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* PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
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* ----------- ---------------- ----- -------- ------------ --------
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* STM32F745Vx LQFP100 82 4/3 16 No
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* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
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* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
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* STM32F745Bx LQFP208 168 6/3 24 No
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* STM32F745Nx TFBGA216 68 6/3 24 No
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* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
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* SPI ADC LCD
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* PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
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* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
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* STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
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*
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* STM32F746Vx LQFP100 82 4/3 16 Yes
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* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
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* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
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* STM32F746Bx LQFP208 168 6/3 24 Yes
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* STM32F746Nx TFBGA216 168 6/3 24 Yes
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* STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU
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*
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* STM32F756Vx LQFP100 82 4/3 16 Yes
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* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
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* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
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* STM32F756Bx LQFP208 168 6/3 24 Yes
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* STM32F756Nx TFBGA216 168 6/3 24 Yes
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* ----------- ---------------- ----- -------- ------------ --------
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* STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
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* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
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* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
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* STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
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* STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
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*
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* STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
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*
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* STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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*
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* STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
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*
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* STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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* STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
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*
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* STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
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*
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* STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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*
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* STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
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*
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* STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
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* STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
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* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
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*
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* Parts STM32F74xxE have 512Kb of FLASH
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* Parts STM32F74xxG have 1024Kb of FLASH
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* Parts STM32F74xxI have 2048Kb of FLASH
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*
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* The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden
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* with CONFIG_STM32F7_FLASH_OVERRIDE_x
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*
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* The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
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* selection.
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
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defined(CONFIG_ARCH_CHIP_STM32F756)
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#if defined(CONFIG_ARCH_CHIP_STM32F745)
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# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
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# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
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# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
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# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
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#elif defined(CONFIG_ARCH_CHIP_STM32F746)
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# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
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# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
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# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
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# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
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#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
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# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
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# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
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# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
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# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
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#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
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defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
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defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
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defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \
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defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \
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defined(CONFIG_ARCH_CHIP_STM32F746BG) || \
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defined(CONFIG_ARCH_CHIP_STM32F746VG) || \
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defined(CONFIG_ARCH_CHIP_STM32F746VE) || \
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defined(CONFIG_ARCH_CHIP_STM32F746BE) || \
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defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \
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defined(CONFIG_ARCH_CHIP_STM32F746IE) || \
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defined(CONFIG_ARCH_CHIP_STM32F746NG) || \
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defined(CONFIG_ARCH_CHIP_STM32F746NE) || \
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defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \
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defined(CONFIG_ARCH_CHIP_STM32F746IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F756NG) || \
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defined(CONFIG_ARCH_CHIP_STM32F756BG) || \
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defined(CONFIG_ARCH_CHIP_STM32F756IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F756VG) || \
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defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \
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defined(CONFIG_ARCH_CHIP_STM32F765NI) || \
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defined(CONFIG_ARCH_CHIP_STM32F765VI) || \
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defined(CONFIG_ARCH_CHIP_STM32F765VG) || \
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defined(CONFIG_ARCH_CHIP_STM32F765BI) || \
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defined(CONFIG_ARCH_CHIP_STM32F765NG) || \
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defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \
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defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \
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defined(CONFIG_ARCH_CHIP_STM32F765IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F765BG) || \
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defined(CONFIG_ARCH_CHIP_STM32F765II) || \
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defined(CONFIG_ARCH_CHIP_STM32F767NG) || \
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defined(CONFIG_ARCH_CHIP_STM32F767IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F767VG) || \
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defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \
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defined(CONFIG_ARCH_CHIP_STM32F767NI) || \
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defined(CONFIG_ARCH_CHIP_STM32F767VI) || \
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defined(CONFIG_ARCH_CHIP_STM32F767BG) || \
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defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \
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defined(CONFIG_ARCH_CHIP_STM32F767II) || \
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defined(CONFIG_ARCH_CHIP_STM32F769BI) || \
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defined(CONFIG_ARCH_CHIP_STM32F769II) || \
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defined(CONFIG_ARCH_CHIP_STM32F769BG) || \
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defined(CONFIG_ARCH_CHIP_STM32F769NI) || \
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defined(CONFIG_ARCH_CHIP_STM32F769AI) || \
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defined(CONFIG_ARCH_CHIP_STM32F769NG) || \
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defined(CONFIG_ARCH_CHIP_STM32F769IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \
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defined(CONFIG_ARCH_CHIP_STM32F777VI) || \
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defined(CONFIG_ARCH_CHIP_STM32F777NI) || \
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defined(CONFIG_ARCH_CHIP_STM32F777BI) || \
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defined(CONFIG_ARCH_CHIP_STM32F777II) || \
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defined(CONFIG_ARCH_CHIP_STM32F778AI) || \
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defined(CONFIG_ARCH_CHIP_STM32F779II) || \
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defined(CONFIG_ARCH_CHIP_STM32F779NI) || \
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defined(CONFIG_ARCH_CHIP_STM32F779BI) || \
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defined(CONFIG_ARCH_CHIP_STM32F779AI)
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#else
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# error STM32 F7 chip not identified
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#endif
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# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
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# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
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# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
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/* Size SRAM */
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
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# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
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# else
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# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV7M_HAVE_ITCM)
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# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
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# else
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# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
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# endif
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X)
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# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
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# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
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# else
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# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV7M_HAVE_ITCM)
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# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
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# else
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# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
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# endif
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#else
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# error STM32 F7 chip Family not identified
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#endif
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/* Common to all Family members */
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# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
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# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32F7_NRNG 1 /* Random number generator (RNG) */
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# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
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# define STM32F7_NUSART 4 /* USART1-3 and 6 */
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# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
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# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
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# define STM32F7_NI2C 4 /* I2C1-4 */
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# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
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# define STM32F7_NCAN 2 /* CAN1-2 */
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# define STM32F7_NSAI 2 /* SAI1-2 */
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# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
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# define STM32F7_NSDMMC 1 /* SDMMC interface */
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# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
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# define STM32F7_NDMA 2 /* DMA1-2 */
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# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
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# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
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# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
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# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32F7_NCRC 1 /* CRC */
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/* TBD FPU Configuration */
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#if defined(CONFIG_ARCH_HAVE_FPU)
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#else
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# error STM32 F7 chip not identified
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#endif
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#if defined(CONFIG_ARCH_HAVE_DPFPU)
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#else
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#endif
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/* Diversification based on Family and package */
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#if defined(CONFIG_STM32F7_HAVE_FSMC)
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# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
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#else
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# define STM32F7_NFSMC 0 /* No FSMC memory controller */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
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# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
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#else
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# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_RNG)
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# define STM32F7_NRNG 1 /* Random number generator (RNG) */
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#else
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# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
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# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
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#else
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# define STM32F7_NSPI 4 /* SPI1-4 V series */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
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# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
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#else
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# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_CAN3)
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# define STM32F7_NCAN 3 /* CAN1-3 */
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#else
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# define STM32F7_NCAN 2 /* CAN1-2 */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_DCMI)
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# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
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#else
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# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
|
||||
# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
|
||||
#else
|
||||
# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
|
||||
#endif
|
||||
#if defined (CONFIG_STM32F7_HAVE_LTDC)
|
||||
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
||||
#else
|
||||
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DMA2D)
|
||||
# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
|
||||
#else
|
||||
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_JPEG)
|
||||
#define STM32F7_NJPEG 1 /* One JPEG Converter */
|
||||
#else
|
||||
#define STM32F7_NJPEG 0 /* No JPEG Converter */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_CRYP)
|
||||
#define STM32F7_NCRYP 1 /* One CRYP engine */
|
||||
#else
|
||||
#define STM32F7_NCRYP 0 /* No CRYP engine */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_HASH)
|
||||
#define STM32F7_NHASH 1 /* One HASH engine */
|
||||
#else
|
||||
#define STM32F7_NHASH 0 /* No HASH engine */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DFSDM)
|
||||
#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
|
||||
#else
|
||||
#define STM32F7_NDFSDM 0 /* No Digital filters */
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
|
||||
@@ -78,6 +78,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include <arch/stm32f7/stm32f76xx77xx_irq.h>
|
||||
#else
|
||||
# error "Unsupported STM32 F7 chip"
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,215 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
|
||||
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
|
||||
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
|
||||
*
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
|
||||
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
|
||||
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
|
||||
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
|
||||
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
|
||||
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
|
||||
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
|
||||
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
|
||||
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
|
||||
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
|
||||
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
|
||||
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
|
||||
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
|
||||
#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
|
||||
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
|
||||
#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
|
||||
#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
|
||||
#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
|
||||
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
|
||||
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
|
||||
|
||||
#define NR_INTERRUPTS 110
|
||||
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS NR_VECTORS
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */
|
||||
Reference in New Issue
Block a user