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arch/arm/src/stm32f7/stm32_qspi.c: Update for new universal cache conrols.

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This commit is contained in:
Gregory Nutt
2019-03-20 09:49:26 -06:00
parent da1a561b6e
commit d7851cf38d
1 changed files with 4 additions and 4 deletions
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arch/arm/src/stm32f7/stm32_qspi.c
+4 -4
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@@ -56,13 +56,13 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/wdog.h> #include <nuttx/wdog.h>
#include <nuttx/clock.h> #include <nuttx/clock.h>
#include <nuttx/cache.h>
#include <nuttx/kmalloc.h> #include <nuttx/kmalloc.h>
#include <nuttx/semaphore.h> #include <nuttx/semaphore.h>
#include <nuttx/spi/qspi.h> #include <nuttx/spi/qspi.h>
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
#include "cache.h"
#include "stm32_gpio.h" #include "stm32_gpio.h"
#include "stm32_dma.h" #include "stm32_dma.h"
@@ -1426,7 +1426,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv,
dmaflags = (QSPI_DMA_PRIO | DMA_SCR_MSIZE_8BITS | dmaflags = (QSPI_DMA_PRIO | DMA_SCR_MSIZE_8BITS |
DMA_SCR_PSIZE_8BITS | DMA_SCR_MINC | DMA_SCR_DIR_M2P); DMA_SCR_PSIZE_8BITS | DMA_SCR_MINC | DMA_SCR_DIR_M2P);
arch_clean_dcache(meminfo->buffer, meminfo->buffer + meminfo->buflen); up_clean_dcache(meminfo->buffer, meminfo->buffer + meminfo->buflen);
} }
else else
{ {
@@ -1484,8 +1484,8 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv,
if (QSPIMEM_ISREAD(meminfo->flags)) if (QSPIMEM_ISREAD(meminfo->flags))
{ {
arch_invalidate_dcache(meminfo->buffer, up_invalidate_dcache(meminfo->buffer,
meminfo->buffer + meminfo->buflen); meminfo->buffer + meminfo->buflen);
} }
/* Cancel the watchdog timeout */ /* Cancel the watchdog timeout */